[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / timer-prima2.c

/*
 * System timer for CSR SiRFprimaII
 *
 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/bitops.h>
#include <linux/irq.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/of_address.h>
#include <linux/sched_clock.h>

#define PRIMA2_CLOCK_FREQ 1000000

#define SIRFSOC_TIMER_COUNTER_LO	0x0000
#define SIRFSOC_TIMER_COUNTER_HI	0x0004
#define SIRFSOC_TIMER_MATCH_0		0x0008
#define SIRFSOC_TIMER_MATCH_1		0x000C
#define SIRFSOC_TIMER_MATCH_2		0x0010
#define SIRFSOC_TIMER_MATCH_3		0x0014
#define SIRFSOC_TIMER_MATCH_4		0x0018
#define SIRFSOC_TIMER_MATCH_5		0x001C
#define SIRFSOC_TIMER_STATUS		0x0020
#define SIRFSOC_TIMER_INT_EN		0x0024
#define SIRFSOC_TIMER_WATCHDOG_EN	0x0028
#define SIRFSOC_TIMER_DIV		0x002C
#define SIRFSOC_TIMER_LATCH		0x0030
#define SIRFSOC_TIMER_LATCHED_LO	0x0034
#define SIRFSOC_TIMER_LATCHED_HI	0x0038

#define SIRFSOC_TIMER_WDT_INDEX		5

#define SIRFSOC_TIMER_LATCH_BIT	 BIT(0)

#define SIRFSOC_TIMER_REG_CNT 11

static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
	SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
	SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
	SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
};

static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];

static void __iomem *sirfsoc_timer_base;

/* timer0 interrupt handler */
static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *ce = dev_id;

	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
		BIT(0)));

	/* clear timer0 interrupt */
	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);

	ce->event_handler(ce);

	return IRQ_HANDLED;
}

/* read 64-bit timer counter */
static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
{
	u64 cycles;

	/* latch the 64-bit timer counter */
	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
	cycles = (cycles << 32) |
		readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

	return cycles;
}

static int sirfsoc_timer_set_next_event(unsigned long delta,
	struct clock_event_device *ce)
{
	unsigned long now, next;

	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	next = now + delta;
	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

	return next - now > delta ? -ETIME : 0;
}

static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
{
	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

	writel_relaxed(val & ~BIT(0),
		       sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	return 0;
}

static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
{
	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

	writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	return 0;
}

static void sirfsoc_clocksource_suspend(struct clocksource *cs)
{
	int i;

	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
		sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
		sirfsoc_timer_reg_val[i] =
			readl_relaxed(sirfsoc_timer_base +
				sirfsoc_timer_reg_list[i]);
}

static void sirfsoc_clocksource_resume(struct clocksource *cs)
{
	int i;

	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
		writel_relaxed(sirfsoc_timer_reg_val[i],
			sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
		sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
}

static struct clock_event_device sirfsoc_clockevent = {
	.name = "sirfsoc_clockevent",
	.rating = 200,
	.features = CLOCK_EVT_FEAT_ONESHOT,
	.set_state_shutdown = sirfsoc_timer_shutdown,
	.set_state_oneshot = sirfsoc_timer_set_oneshot,
	.set_next_event = sirfsoc_timer_set_next_event,
};

static struct clocksource sirfsoc_clocksource = {
	.name = "sirfsoc_clocksource",
	.rating = 200,
	.mask = CLOCKSOURCE_MASK(64),
	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	.read = sirfsoc_timer_read,
	.suspend = sirfsoc_clocksource_suspend,
	.resume = sirfsoc_clocksource_resume,
};

static struct irqaction sirfsoc_timer_irq = {
	.name = "sirfsoc_timer0",
	.flags = IRQF_TIMER,
	.irq = 0,
	.handler = sirfsoc_timer_interrupt,
	.dev_id = &sirfsoc_clockevent,
};

/* Overwrite weak default sched_clock with more precise one */
static u64 notrace sirfsoc_read_sched_clock(void)
{
	return sirfsoc_timer_read(NULL);
}

static void __init sirfsoc_clockevent_init(void)
{
	sirfsoc_clockevent.cpumask = cpumask_of(0);
	clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
					2, -2);
}

/* initialize the kernel jiffy timer source */
static int __init sirfsoc_prima2_timer_init(struct device_node *np)
{
	unsigned long rate;
	struct clk *clk;
	int ret;

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Failed to enable clock\n");
		return ret;
	}

	rate = clk_get_rate(clk);

	if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
		pr_err("Invalid clock rate\n");
		return -EINVAL;
	}

	sirfsoc_timer_base = of_iomap(np, 0);
	if (!sirfsoc_timer_base) {
		pr_err("unable to map timer cpu registers\n");
		return -ENXIO;
	}

	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);

	writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
		sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);

	ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
	if (ret) {
		pr_err("Failed to register clocksource\n");
		return ret;
	}

	sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);

	ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
	if (ret) {
		pr_err("Failed to setup irq\n");
		return ret;
	}

	sirfsoc_clockevent_init();

	return 0;
}
TIMER_OF_DECLARE(sirfsoc_prima2_timer,
	"sirf,prima2-tick", sirfsoc_prima2_timer_init);
Commit	Line	Data
02c981c0 BD	1	/*
	2	* System timer for CSR SiRFprimaII
	3	*
	4	* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/kernel.h>
	10	#include <linux/interrupt.h>
	11	#include <linux/clockchips.h>
	12	#include <linux/clocksource.h>
	13	#include <linux/bitops.h>
	14	#include <linux/irq.h>
	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/slab.h>
	18	#include <linux/of.h>
67d71344	19	#include <linux/of_irq.h>
02c981c0	20	#include <linux/of_address.h>
38ff87f7	21	#include <linux/sched_clock.h>
02c981c0	22
980c51ab UKK	23	#define PRIMA2_CLOCK_FREQ 1000000
980c51ab UKK	24
02c981c0 BD	25	#define SIRFSOC_TIMER_COUNTER_LO 0x0000
	26	#define SIRFSOC_TIMER_COUNTER_HI 0x0004
	27	#define SIRFSOC_TIMER_MATCH_0 0x0008
	28	#define SIRFSOC_TIMER_MATCH_1 0x000C
	29	#define SIRFSOC_TIMER_MATCH_2 0x0010
	30	#define SIRFSOC_TIMER_MATCH_3 0x0014
	31	#define SIRFSOC_TIMER_MATCH_4 0x0018
	32	#define SIRFSOC_TIMER_MATCH_5 0x001C
	33	#define SIRFSOC_TIMER_STATUS 0x0020
	34	#define SIRFSOC_TIMER_INT_EN 0x0024
	35	#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
	36	#define SIRFSOC_TIMER_DIV 0x002C
	37	#define SIRFSOC_TIMER_LATCH 0x0030
	38	#define SIRFSOC_TIMER_LATCHED_LO 0x0034
	39	#define SIRFSOC_TIMER_LATCHED_HI 0x0038
	40
	41	#define SIRFSOC_TIMER_WDT_INDEX 5
	42
	43	#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
	44
e5598a85 BS	45	#define SIRFSOC_TIMER_REG_CNT 11
	46
	47	static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
	48	SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
	49	SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
	50	SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
	51	SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
	52	};
	53
	54	static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
	55
02c981c0	56	static void __iomem *sirfsoc_timer_base;
02c981c0 BD	57
	58	/* timer0 interrupt handler */
	59	static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
	60	{
	61	struct clock_event_device *ce = dev_id;
	62
4c1ad709 BS	63	WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
4c1ad709 BS	64	BIT(0)));
02c981c0 BD	65
	66	/* clear timer0 interrupt */
	67	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
	68
	69	ce->event_handler(ce);
	70
	71	return IRQ_HANDLED;
	72	}
	73
	74	/* read 64-bit timer counter */
a5a1d1c2	75	static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
02c981c0 BD	76	{
	77	u64 cycles;
	78
	79	/* latch the 64-bit timer counter */
4c1ad709 BS	80	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	81	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0	82	cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
4c1ad709 BS	83	cycles = (cycles << 32) \|
4c1ad709 BS	84	readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
02c981c0 BD	85
	86	return cycles;
	87	}
	88
	89	static int sirfsoc_timer_set_next_event(unsigned long delta,
	90	struct clock_event_device *ce)
	91	{
	92	unsigned long now, next;
	93
4c1ad709 BS	94	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	95	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0 BD	96	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	97	next = now + delta;
	98	writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
4c1ad709 BS	99	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	100	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
02c981c0 BD	101	now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
	102
	103	return next - now > delta ? -ETIME : 0;
	104	}
	105
53cba064	106	static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
02c981c0 BD	107	{
02c981c0 BD	108	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
53cba064 VK	109
	110	writel_relaxed(val & ~BIT(0),
	111	sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	112	return 0;
	113	}
	114
	115	static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
	116	{
	117	u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	118
	119	writel_relaxed(val \| BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
	120	return 0;
02c981c0 BD	121	}
02c981c0 BD	122
e5598a85 BS	123	static void sirfsoc_clocksource_suspend(struct clocksource *cs)
	124	{
	125	int i;
	126
4c1ad709 BS	127	writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
4c1ad709 BS	128	sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
e5598a85 BS	129
e5598a85 BS	130	for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
4c1ad709 BS	131	sirfsoc_timer_reg_val[i] =
	132	readl_relaxed(sirfsoc_timer_base +
	133	sirfsoc_timer_reg_list[i]);
e5598a85 BS	134	}
	135
	136	static void sirfsoc_clocksource_resume(struct clocksource *cs)
	137	{
	138	int i;
	139
debeaf6c	140	for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
4c1ad709 BS	141	writel_relaxed(sirfsoc_timer_reg_val[i],
4c1ad709 BS	142	sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
e5598a85	143
4c1ad709 BS	144	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
	145	sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	146	writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
	147	sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
e5598a85 BS	148	}
e5598a85 BS	149
02c981c0 BD	150	static struct clock_event_device sirfsoc_clockevent = {
	151	.name = "sirfsoc_clockevent",
	152	.rating = 200,
	153	.features = CLOCK_EVT_FEAT_ONESHOT,
53cba064 VK	154	.set_state_shutdown = sirfsoc_timer_shutdown,
53cba064 VK	155	.set_state_oneshot = sirfsoc_timer_set_oneshot,
02c981c0 BD	156	.set_next_event = sirfsoc_timer_set_next_event,
	157	};
	158
	159	static struct clocksource sirfsoc_clocksource = {
	160	.name = "sirfsoc_clocksource",
	161	.rating = 200,
	162	.mask = CLOCKSOURCE_MASK(64),
	163	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	164	.read = sirfsoc_timer_read,
e5598a85 BS	165	.suspend = sirfsoc_clocksource_suspend,
e5598a85 BS	166	.resume = sirfsoc_clocksource_resume,
02c981c0 BD	167	};
	168
	169	static struct irqaction sirfsoc_timer_irq = {
	170	.name = "sirfsoc_timer0",
	171	.flags = IRQF_TIMER,
	172	.irq = 0,
	173	.handler = sirfsoc_timer_interrupt,
	174	.dev_id = &sirfsoc_clockevent,
	175	};
	176
	177	/* Overwrite weak default sched_clock with more precise one */
130e6b25	178	static u64 notrace sirfsoc_read_sched_clock(void)
02c981c0	179	{
130e6b25	180	return sirfsoc_timer_read(NULL);
02c981c0 BD	181	}
	182
	183	static void __init sirfsoc_clockevent_init(void)
	184	{
02c981c0	185	sirfsoc_clockevent.cpumask = cpumask_of(0);
980c51ab	186	clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
838a2ae8	187	2, -2);
02c981c0 BD	188	}
	189
	190	/* initialize the kernel jiffy timer source */
de23484d	191	static int __init sirfsoc_prima2_timer_init(struct device_node *np)
02c981c0 BD	192	{
02c981c0 BD	193	unsigned long rate;
198678b0	194	struct clk *clk;
de23484d	195	int ret;
198678b0	196
c7cff54d	197	clk = of_clk_get(np, 0);
de23484d	198	if (IS_ERR(clk)) {
ac9ce6d1	199	pr_err("Failed to get clock\n");
de23484d DL	200	return PTR_ERR(clk);
de23484d DL	201	}
38941522	202
de23484d DL	203	ret = clk_prepare_enable(clk);
de23484d DL	204	if (ret) {
ac9ce6d1	205	pr_err("Failed to enable clock\n");
de23484d DL	206	return ret;
de23484d DL	207	}
38941522	208
02c981c0 BD	209	rate = clk_get_rate(clk);
02c981c0 BD	210
de23484d	211	if (rate < PRIMA2_CLOCK_FREQ \|\| rate % PRIMA2_CLOCK_FREQ) {
ac9ce6d1	212	pr_err("Invalid clock rate\n");
de23484d DL	213	return -EINVAL;
de23484d DL	214	}
02c981c0	215
275786b7	216	sirfsoc_timer_base = of_iomap(np, 0);
de23484d DL	217	if (!sirfsoc_timer_base) {
	218	pr_err("unable to map timer cpu registers\n");
	219	return -ENXIO;
	220	}
275786b7 AB	221
275786b7 AB	222	sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
bc8d849d	223
980c51ab	224	writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
4c1ad709	225	sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
02c981c0 BD	226	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
	227	writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
	228	writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
	229
de23484d DL	230	ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
de23484d DL	231	if (ret) {
ac9ce6d1	232	pr_err("Failed to register clocksource\n");
de23484d DL	233	return ret;
de23484d DL	234	}
02c981c0	235
980c51ab	236	sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
bc8d849d	237
de23484d DL	238	ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
de23484d DL	239	if (ret) {
ac9ce6d1	240	pr_err("Failed to setup irq\n");
de23484d DL	241	return ret;
de23484d DL	242	}
02c981c0 BD	243
02c981c0 BD	244	sirfsoc_clockevent_init();
de23484d DL	245
de23484d DL	246	return 0;
02c981c0	247	}
17273395	248	TIMER_OF_DECLARE(sirfsoc_prima2_timer,
4c1ad709	249	"sirf,prima2-tick", sirfsoc_prima2_timer_init);