[mirror_ubuntu-jammy-kernel.git] / drivers / clocksource / timer-sp804.c

/*
 *  linux/drivers/clocksource/timer-sp.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_clk.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <clocksource/timer-sp804.h>

#include "timer-sp.h"

static long __init sp804_get_clock_rate(struct clk *clk)
{
	long rate;
	int err;

	err = clk_prepare(clk);
	if (err) {
		pr_err("sp804: clock failed to prepare: %d\n", err);
		clk_put(clk);
		return err;
	}

	err = clk_enable(clk);
	if (err) {
		pr_err("sp804: clock failed to enable: %d\n", err);
		clk_unprepare(clk);
		clk_put(clk);
		return err;
	}

	rate = clk_get_rate(clk);
	if (rate < 0) {
		pr_err("sp804: clock failed to get rate: %ld\n", rate);
		clk_disable(clk);
		clk_unprepare(clk);
		clk_put(clk);
	}

	return rate;
}

static void __iomem *sched_clock_base;

static u64 notrace sp804_read(void)
{
	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}

void __init sp804_timer_disable(void __iomem *base)
{
	writel(0, base + TIMER_CTRL);
}

int  __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
						     const char *name,
						     struct clk *clk,
						     int use_sched_clock)
{
	long rate;

	if (!clk) {
		clk = clk_get_sys("sp804", name);
		if (IS_ERR(clk)) {
			pr_err("sp804: clock not found: %d\n",
			       (int)PTR_ERR(clk));
			return PTR_ERR(clk);
		}
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return -EINVAL;

	/* setup timer 0 as free-running clocksource */
	writel(0, base + TIMER_CTRL);
	writel(0xffffffff, base + TIMER_LOAD);
	writel(0xffffffff, base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, name,
		rate, 200, 32, clocksource_mmio_readl_down);

	if (use_sched_clock) {
		sched_clock_base = base;
		sched_clock_register(sp804_read, 32, rate);
	}

	return 0;
}


static void __iomem *clkevt_base;
static unsigned long clkevt_reload;

/*
 * IRQ handler for the timer
 */
static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static inline void timer_shutdown(struct clock_event_device *evt)
{
	writel(0, clkevt_base + TIMER_CTRL);
}

static int sp804_shutdown(struct clock_event_device *evt)
{
	timer_shutdown(evt);
	return 0;
}

static int sp804_set_periodic(struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
			     TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;

	timer_shutdown(evt);
	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int sp804_set_next_event(unsigned long next,
	struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
			     TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;

	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device sp804_clockevent = {
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_DYNIRQ,
	.set_state_shutdown	= sp804_shutdown,
	.set_state_periodic	= sp804_set_periodic,
	.set_state_oneshot	= sp804_shutdown,
	.tick_resume		= sp804_shutdown,
	.set_next_event		= sp804_set_next_event,
	.rating			= 300,
};

static struct irqaction sp804_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= sp804_timer_interrupt,
	.dev_id		= &sp804_clockevent,
};

int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
{
	struct clock_event_device *evt = &sp804_clockevent;
	long rate;

	if (!clk)
		clk = clk_get_sys("sp804", name);
	if (IS_ERR(clk)) {
		pr_err("sp804: %s clock not found: %d\n", name,
			(int)PTR_ERR(clk));
		return PTR_ERR(clk);
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return -EINVAL;

	clkevt_base = base;
	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
	evt->name = name;
	evt->irq = irq;
	evt->cpumask = cpu_possible_mask;

	writel(0, base + TIMER_CTRL);

	setup_irq(irq, &sp804_timer_irq);
	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);

	return 0;
}

static int __init sp804_of_init(struct device_node *np)
{
	static bool initialized = false;
	void __iomem *base;
	int irq, ret = -EINVAL;
	u32 irq_num = 0;
	struct clk *clk1, *clk2;
	const char *name = of_get_property(np, "compatible", NULL);

	base = of_iomap(np, 0);
	if (!base)
		return -ENXIO;

	/* Ensure timers are disabled */
	writel(0, base + TIMER_CTRL);
	writel(0, base + TIMER_2_BASE + TIMER_CTRL);

	if (initialized || !of_device_is_available(np)) {
		ret = -EINVAL;
		goto err;
	}

	clk1 = of_clk_get(np, 0);
	if (IS_ERR(clk1))
		clk1 = NULL;

	/* Get the 2nd clock if the timer has 3 timer clocks */
	if (of_clk_get_parent_count(np) == 3) {
		clk2 = of_clk_get(np, 1);
		if (IS_ERR(clk2)) {
			pr_err("sp804: %pOFn clock not found: %d\n", np,
				(int)PTR_ERR(clk2));
			clk2 = NULL;
		}
	} else
		clk2 = clk1;

	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0)
		goto err;

	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	if (irq_num == 2) {

		ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
		if (ret)
			goto err;

		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
		if (ret)
			goto err;
	} else {

		ret = __sp804_clockevents_init(base, irq, clk1 , name);
		if (ret)
			goto err;

		ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
							      name, clk2, 1);
		if (ret)
			goto err;
	}
	initialized = true;

	return 0;
err:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);

static int __init integrator_cp_of_init(struct device_node *np)
{
	static int init_count = 0;
	void __iomem *base;
	int irq, ret = -EINVAL;
	const char *name = of_get_property(np, "compatible", NULL);
	struct clk *clk;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to iomap\n");
		return -ENXIO;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	/* Ensure timer is disabled */
	writel(0, base + TIMER_CTRL);

	if (init_count == 2 || !of_device_is_available(np))
		goto err;

	if (!init_count) {
		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
		if (ret)
			goto err;
	} else {
		irq = irq_of_parse_and_map(np, 0);
		if (irq <= 0)
			goto err;

		ret = __sp804_clockevents_init(base, irq, clk, name);
		if (ret)
			goto err;
	}

	init_count++;
	return 0;
err:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
Commit	Line	Data
e3887714	1	/*
0b7402dc	2	* linux/drivers/clocksource/timer-sp.c
e3887714 RK	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
7ff550de	21	#include <linux/clk.h>
e3887714 RK	22	#include <linux/clocksource.h>
e3887714 RK	23	#include <linux/clockchips.h>
7ff550de	24	#include <linux/err.h>
e3887714 RK	25	#include <linux/interrupt.h>
	26	#include <linux/irq.h>
	27	#include <linux/io.h>
7a0eca71 RH	28	#include <linux/of.h>
7a0eca71 RH	29	#include <linux/of_address.h>
b799cac7	30	#include <linux/of_clk.h>
7a0eca71	31	#include <linux/of_irq.h>
38ff87f7	32	#include <linux/sched_clock.h>
e3887714	33
0b7402dc SH	34	#include <clocksource/timer-sp804.h>
	35
	36	#include "timer-sp.h"
e3887714	37
7a0eca71	38	static long __init sp804_get_clock_rate(struct clk *clk)
7ff550de	39	{
7ff550de RK	40	long rate;
	41	int err;
	42
6f5ad963 RK	43	err = clk_prepare(clk);
6f5ad963 RK	44	if (err) {
7a0eca71	45	pr_err("sp804: clock failed to prepare: %d\n", err);
6f5ad963 RK	46	clk_put(clk);
	47	return err;
	48	}
	49
7ff550de RK	50	err = clk_enable(clk);
7ff550de RK	51	if (err) {
7a0eca71	52	pr_err("sp804: clock failed to enable: %d\n", err);
6f5ad963	53	clk_unprepare(clk);
7ff550de RK	54	clk_put(clk);
	55	return err;
	56	}
	57
	58	rate = clk_get_rate(clk);
	59	if (rate < 0) {
7a0eca71	60	pr_err("sp804: clock failed to get rate: %ld\n", rate);
7ff550de	61	clk_disable(clk);
6f5ad963	62	clk_unprepare(clk);
7ff550de RK	63	clk_put(clk);
	64	}
	65
	66	return rate;
	67	}
	68
a7bf6162 RH	69	static void __iomem *sched_clock_base;
a7bf6162 RH	70
9b12f3a8	71	static u64 notrace sp804_read(void)
a7bf6162 RH	72	{
	73	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
	74	}
	75
1e5f0519 SH	76	void __init sp804_timer_disable(void __iomem *base)
	77	{
	78	writel(0, base + TIMER_CTRL);
	79	}
	80
2ef2538b	81	int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
a7bf6162	82	const char *name,
7a0eca71	83	struct clk *clk,
a7bf6162	84	int use_sched_clock)
e3887714	85	{
7a0eca71 RH	86	long rate;
	87
	88	if (!clk) {
	89	clk = clk_get_sys("sp804", name);
	90	if (IS_ERR(clk)) {
	91	pr_err("sp804: clock not found: %d\n",
	92	(int)PTR_ERR(clk));
2ef2538b	93	return PTR_ERR(clk);
7a0eca71 RH	94	}
	95	}
	96
	97	rate = sp804_get_clock_rate(clk);
7ff550de	98	if (rate < 0)
2ef2538b	99	return -EINVAL;
7ff550de	100
e3887714	101	/* setup timer 0 as free-running clocksource */
bfe45e0b RK	102	writel(0, base + TIMER_CTRL);
	103	writel(0xffffffff, base + TIMER_LOAD);
	104	writel(0xffffffff, base + TIMER_VALUE);
e3887714	105	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
bfe45e0b	106	base + TIMER_CTRL);
e3887714	107
fb593cf3	108	clocksource_mmio_init(base + TIMER_VALUE, name,
7ff550de	109	rate, 200, 32, clocksource_mmio_readl_down);
a7bf6162 RH	110
	111	if (use_sched_clock) {
	112	sched_clock_base = base;
9b12f3a8	113	sched_clock_register(sp804_read, 32, rate);
a7bf6162	114	}
2ef2538b DL	115
2ef2538b DL	116	return 0;
e3887714 RK	117	}
	118
	119
	120	static void __iomem *clkevt_base;
23828a7a	121	static unsigned long clkevt_reload;
e3887714 RK	122
	123	/*
	124	* IRQ handler for the timer
	125	*/
	126	static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
	127	{
	128	struct clock_event_device *evt = dev_id;
	129
	130	/* clear the interrupt */
	131	writel(1, clkevt_base + TIMER_INTCLR);
	132
	133	evt->event_handler(evt);
	134
	135	return IRQ_HANDLED;
	136	}
	137
daea7283	138	static inline void timer_shutdown(struct clock_event_device *evt)
e3887714	139	{
daea7283 VK	140	writel(0, clkevt_base + TIMER_CTRL);
daea7283 VK	141	}
e3887714	142
daea7283 VK	143	static int sp804_shutdown(struct clock_event_device *evt)
	144	{
	145	timer_shutdown(evt);
	146	return 0;
	147	}
e3887714	148
daea7283 VK	149	static int sp804_set_periodic(struct clock_event_device *evt)
	150	{
	151	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
	152	TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
e3887714	153
daea7283 VK	154	timer_shutdown(evt);
daea7283 VK	155	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
e3887714	156	writel(ctrl, clkevt_base + TIMER_CTRL);
daea7283	157	return 0;
e3887714 RK	158	}
	159
	160	static int sp804_set_next_event(unsigned long next,
	161	struct clock_event_device *evt)
	162	{
daea7283 VK	163	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
daea7283 VK	164	TIMER_CTRL_ONESHOT \| TIMER_CTRL_ENABLE;
e3887714 RK	165
e3887714 RK	166	writel(next, clkevt_base + TIMER_LOAD);
daea7283	167	writel(ctrl, clkevt_base + TIMER_CTRL);
e3887714 RK	168
	169	return 0;
	170	}
	171
	172	static struct clock_event_device sp804_clockevent = {
daea7283 VK	173	.features = CLOCK_EVT_FEAT_PERIODIC \|
	174	CLOCK_EVT_FEAT_ONESHOT \|
	175	CLOCK_EVT_FEAT_DYNIRQ,
	176	.set_state_shutdown = sp804_shutdown,
	177	.set_state_periodic = sp804_set_periodic,
	178	.set_state_oneshot = sp804_shutdown,
	179	.tick_resume = sp804_shutdown,
	180	.set_next_event = sp804_set_next_event,
	181	.rating = 300,
e3887714 RK	182	};
	183
	184	static struct irqaction sp804_timer_irq = {
	185	.name = "timer",
728fae6f	186	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
e3887714 RK	187	.handler = sp804_timer_interrupt,
	188	.dev_id = &sp804_clockevent,
	189	};
	190
2ef2538b	191	int __init __sp804_clockevents_init(void __iomem base, unsigned int irq, struct clk clk, const char *name)
e3887714 RK	192	{
e3887714 RK	193	struct clock_event_device *evt = &sp804_clockevent;
7a0eca71 RH	194	long rate;
	195
	196	if (!clk)
	197	clk = clk_get_sys("sp804", name);
	198	if (IS_ERR(clk)) {
	199	pr_err("sp804: %s clock not found: %d\n", name,
	200	(int)PTR_ERR(clk));
2ef2538b	201	return PTR_ERR(clk);
7a0eca71	202	}
23828a7a	203
7a0eca71	204	rate = sp804_get_clock_rate(clk);
23828a7a	205	if (rate < 0)
2ef2538b	206	return -EINVAL;
e3887714 RK	207
e3887714 RK	208	clkevt_base = base;
23828a7a	209	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
57cc4f7d RK	210	evt->name = name;
57cc4f7d RK	211	evt->irq = irq;
ea3aacf5	212	evt->cpumask = cpu_possible_mask;
e3887714	213
7a0eca71 RH	214	writel(0, base + TIMER_CTRL);
7a0eca71 RH	215
57cc4f7d	216	setup_irq(irq, &sp804_timer_irq);
7c324d83	217	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
2ef2538b DL	218
2ef2538b DL	219	return 0;
e3887714	220	}
7a0eca71	221
2ef2538b	222	static int __init sp804_of_init(struct device_node *np)
7a0eca71 RH	223	{
	224	static bool initialized = false;
	225	void __iomem *base;
2ef2538b	226	int irq, ret = -EINVAL;
7a0eca71 RH	227	u32 irq_num = 0;
	228	struct clk clk1, clk2;
	229	const char *name = of_get_property(np, "compatible", NULL);
	230
	231	base = of_iomap(np, 0);
2ef2538b DL	232	if (!base)
2ef2538b DL	233	return -ENXIO;
7a0eca71 RH	234
	235	/* Ensure timers are disabled */
	236	writel(0, base + TIMER_CTRL);
	237	writel(0, base + TIMER_2_BASE + TIMER_CTRL);
	238
2ef2538b DL	239	if (initialized \|\| !of_device_is_available(np)) {
2ef2538b DL	240	ret = -EINVAL;
7a0eca71	241	goto err;
2ef2538b	242	}
7a0eca71 RH	243
	244	clk1 = of_clk_get(np, 0);
	245	if (IS_ERR(clk1))
	246	clk1 = NULL;
	247
1bde9906	248	/* Get the 2nd clock if the timer has 3 timer clocks */
b799cac7	249	if (of_clk_get_parent_count(np) == 3) {
7a0eca71 RH	250	clk2 = of_clk_get(np, 1);
7a0eca71 RH	251	if (IS_ERR(clk2)) {
2a4849d2	252	pr_err("sp804: %pOFn clock not found: %d\n", np,
7a0eca71	253	(int)PTR_ERR(clk2));
1bde9906	254	clk2 = NULL;
7a0eca71 RH	255	}
	256	} else
	257	clk2 = clk1;
	258
	259	irq = irq_of_parse_and_map(np, 0);
	260	if (irq <= 0)
	261	goto err;
	262
	263	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	264	if (irq_num == 2) {
2ef2538b DL	265
	266	ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
	267	if (ret)
	268	goto err;
	269
	270	ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
	271	if (ret)
	272	goto err;
7a0eca71	273	} else {
2ef2538b DL	274
	275	ret = __sp804_clockevents_init(base, irq, clk1 , name);
	276	if (ret)
	277	goto err;
	278
	279	ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
	280	name, clk2, 1);
	281	if (ret)
	282	goto err;
7a0eca71 RH	283	}
	284	initialized = true;
	285
2ef2538b	286	return 0;
7a0eca71 RH	287	err:
7a0eca71 RH	288	iounmap(base);
2ef2538b	289	return ret;
7a0eca71	290	}
17273395	291	TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
870e2928	292
2ef2538b	293	static int __init integrator_cp_of_init(struct device_node *np)
870e2928 RH	294	{
	295	static int init_count = 0;
	296	void __iomem *base;
2ef2538b	297	int irq, ret = -EINVAL;
870e2928	298	const char *name = of_get_property(np, "compatible", NULL);
9cf31380	299	struct clk *clk;
870e2928 RH	300
870e2928 RH	301	base = of_iomap(np, 0);
2ef2538b	302	if (!base) {
ac9ce6d1	303	pr_err("Failed to iomap\n");
2ef2538b DL	304	return -ENXIO;
	305	}
	306
9cf31380	307	clk = of_clk_get(np, 0);
2ef2538b	308	if (IS_ERR(clk)) {
ac9ce6d1	309	pr_err("Failed to get clock\n");
2ef2538b DL	310	return PTR_ERR(clk);
2ef2538b DL	311	}
870e2928 RH	312
	313	/* Ensure timer is disabled */
	314	writel(0, base + TIMER_CTRL);
	315
	316	if (init_count == 2 \|\| !of_device_is_available(np))
	317	goto err;
	318
2ef2538b DL	319	if (!init_count) {
	320	ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
	321	if (ret)
	322	goto err;
	323	} else {
870e2928 RH	324	irq = irq_of_parse_and_map(np, 0);
	325	if (irq <= 0)
	326	goto err;
	327
2ef2538b DL	328	ret = __sp804_clockevents_init(base, irq, clk, name);
	329	if (ret)
	330	goto err;
870e2928 RH	331	}
	332
	333	init_count++;
2ef2538b	334	return 0;
870e2928 RH	335	err:
870e2928 RH	336	iounmap(base);
2ef2538b	337	return ret;
870e2928	338	}
17273395	339	TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);