[mirror_ubuntu-artful-kernel.git] / drivers / clocksource / timer-sp804.c

/*
 *  linux/drivers/clocksource/timer-sp.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sched_clock.h>

#include <clocksource/timer-sp804.h>

#include "timer-sp.h"

static long __init sp804_get_clock_rate(struct clk *clk)
{
	long rate;
	int err;

	err = clk_prepare(clk);
	if (err) {
		pr_err("sp804: clock failed to prepare: %d\n", err);
		clk_put(clk);
		return err;
	}

	err = clk_enable(clk);
	if (err) {
		pr_err("sp804: clock failed to enable: %d\n", err);
		clk_unprepare(clk);
		clk_put(clk);
		return err;
	}

	rate = clk_get_rate(clk);
	if (rate < 0) {
		pr_err("sp804: clock failed to get rate: %ld\n", rate);
		clk_disable(clk);
		clk_unprepare(clk);
		clk_put(clk);
	}

	return rate;
}

static void __iomem *sched_clock_base;

static u64 notrace sp804_read(void)
{
	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
}

void __init sp804_timer_disable(void __iomem *base)
{
	writel(0, base + TIMER_CTRL);
}

int  __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
						     const char *name,
						     struct clk *clk,
						     int use_sched_clock)
{
	long rate;

	if (!clk) {
		clk = clk_get_sys("sp804", name);
		if (IS_ERR(clk)) {
			pr_err("sp804: clock not found: %d\n",
			       (int)PTR_ERR(clk));
			return PTR_ERR(clk);
		}
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return -EINVAL;

	/* setup timer 0 as free-running clocksource */
	writel(0, base + TIMER_CTRL);
	writel(0xffffffff, base + TIMER_LOAD);
	writel(0xffffffff, base + TIMER_VALUE);
	writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
		base + TIMER_CTRL);

	clocksource_mmio_init(base + TIMER_VALUE, name,
		rate, 200, 32, clocksource_mmio_readl_down);

	if (use_sched_clock) {
		sched_clock_base = base;
		sched_clock_register(sp804_read, 32, rate);
	}

	return 0;
}


static void __iomem *clkevt_base;
static unsigned long clkevt_reload;

/*
 * IRQ handler for the timer
 */
static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	/* clear the interrupt */
	writel(1, clkevt_base + TIMER_INTCLR);

	evt->event_handler(evt);

	return IRQ_HANDLED;
}

static inline void timer_shutdown(struct clock_event_device *evt)
{
	writel(0, clkevt_base + TIMER_CTRL);
}

static int sp804_shutdown(struct clock_event_device *evt)
{
	timer_shutdown(evt);
	return 0;
}

static int sp804_set_periodic(struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
			     TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;

	timer_shutdown(evt);
	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
	writel(ctrl, clkevt_base + TIMER_CTRL);
	return 0;
}

static int sp804_set_next_event(unsigned long next,
	struct clock_event_device *evt)
{
	unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE |
			     TIMER_CTRL_ONESHOT | TIMER_CTRL_ENABLE;

	writel(next, clkevt_base + TIMER_LOAD);
	writel(ctrl, clkevt_base + TIMER_CTRL);

	return 0;
}

static struct clock_event_device sp804_clockevent = {
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT |
				  CLOCK_EVT_FEAT_DYNIRQ,
	.set_state_shutdown	= sp804_shutdown,
	.set_state_periodic	= sp804_set_periodic,
	.set_state_oneshot	= sp804_shutdown,
	.tick_resume		= sp804_shutdown,
	.set_next_event		= sp804_set_next_event,
	.rating			= 300,
};

static struct irqaction sp804_timer_irq = {
	.name		= "timer",
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.handler	= sp804_timer_interrupt,
	.dev_id		= &sp804_clockevent,
};

int __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name)
{
	struct clock_event_device *evt = &sp804_clockevent;
	long rate;

	if (!clk)
		clk = clk_get_sys("sp804", name);
	if (IS_ERR(clk)) {
		pr_err("sp804: %s clock not found: %d\n", name,
			(int)PTR_ERR(clk));
		return PTR_ERR(clk);
	}

	rate = sp804_get_clock_rate(clk);
	if (rate < 0)
		return -EINVAL;

	clkevt_base = base;
	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
	evt->name = name;
	evt->irq = irq;
	evt->cpumask = cpu_possible_mask;

	writel(0, base + TIMER_CTRL);

	setup_irq(irq, &sp804_timer_irq);
	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);

	return 0;
}

static int __init sp804_of_init(struct device_node *np)
{
	static bool initialized = false;
	void __iomem *base;
	int irq, ret = -EINVAL;
	u32 irq_num = 0;
	struct clk *clk1, *clk2;
	const char *name = of_get_property(np, "compatible", NULL);

	base = of_iomap(np, 0);
	if (!base)
		return -ENXIO;

	/* Ensure timers are disabled */
	writel(0, base + TIMER_CTRL);
	writel(0, base + TIMER_2_BASE + TIMER_CTRL);

	if (initialized || !of_device_is_available(np)) {
		ret = -EINVAL;
		goto err;
	}

	clk1 = of_clk_get(np, 0);
	if (IS_ERR(clk1))
		clk1 = NULL;

	/* Get the 2nd clock if the timer has 3 timer clocks */
	if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
		clk2 = of_clk_get(np, 1);
		if (IS_ERR(clk2)) {
			pr_err("sp804: %s clock not found: %d\n", np->name,
				(int)PTR_ERR(clk2));
			clk2 = NULL;
		}
	} else
		clk2 = clk1;

	irq = irq_of_parse_and_map(np, 0);
	if (irq <= 0)
		goto err;

	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	if (irq_num == 2) {

		ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
		if (ret)
			goto err;

		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
		if (ret)
			goto err;
	} else {

		ret = __sp804_clockevents_init(base, irq, clk1 , name);
		if (ret)
			goto err;

		ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
							      name, clk2, 1);
		if (ret)
			goto err;
	}
	initialized = true;

	return 0;
err:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);

static int __init integrator_cp_of_init(struct device_node *np)
{
	static int init_count = 0;
	void __iomem *base;
	int irq, ret = -EINVAL;
	const char *name = of_get_property(np, "compatible", NULL);
	struct clk *clk;

	base = of_iomap(np, 0);
	if (!base) {
		pr_err("Failed to iomap\n");
		return -ENXIO;
	}

	clk = of_clk_get(np, 0);
	if (IS_ERR(clk)) {
		pr_err("Failed to get clock\n");
		return PTR_ERR(clk);
	}

	/* Ensure timer is disabled */
	writel(0, base + TIMER_CTRL);

	if (init_count == 2 || !of_device_is_available(np))
		goto err;

	if (!init_count) {
		ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
		if (ret)
			goto err;
	} else {
		irq = irq_of_parse_and_map(np, 0);
		if (irq <= 0)
			goto err;

		ret = __sp804_clockevents_init(base, irq, clk, name);
		if (ret)
			goto err;
	}

	init_count++;
	return 0;
err:
	iounmap(base);
	return ret;
}
TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
Commit	Line	Data
e3887714	1	/*
0b7402dc	2	* linux/drivers/clocksource/timer-sp.c
e3887714 RK	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
7ff550de	21	#include <linux/clk.h>
e3887714 RK	22	#include <linux/clocksource.h>
e3887714 RK	23	#include <linux/clockchips.h>
7ff550de	24	#include <linux/err.h>
e3887714 RK	25	#include <linux/interrupt.h>
	26	#include <linux/irq.h>
	27	#include <linux/io.h>
7a0eca71 RH	28	#include <linux/of.h>
	29	#include <linux/of_address.h>
	30	#include <linux/of_irq.h>
38ff87f7	31	#include <linux/sched_clock.h>
e3887714	32
0b7402dc SH	33	#include <clocksource/timer-sp804.h>
	34
	35	#include "timer-sp.h"
e3887714	36
7a0eca71	37	static long __init sp804_get_clock_rate(struct clk *clk)
7ff550de	38	{
7ff550de RK	39	long rate;
	40	int err;
	41
6f5ad963 RK	42	err = clk_prepare(clk);
6f5ad963 RK	43	if (err) {
7a0eca71	44	pr_err("sp804: clock failed to prepare: %d\n", err);
6f5ad963 RK	45	clk_put(clk);
	46	return err;
	47	}
	48
7ff550de RK	49	err = clk_enable(clk);
7ff550de RK	50	if (err) {
7a0eca71	51	pr_err("sp804: clock failed to enable: %d\n", err);
6f5ad963	52	clk_unprepare(clk);
7ff550de RK	53	clk_put(clk);
	54	return err;
	55	}
	56
	57	rate = clk_get_rate(clk);
	58	if (rate < 0) {
7a0eca71	59	pr_err("sp804: clock failed to get rate: %ld\n", rate);
7ff550de	60	clk_disable(clk);
6f5ad963	61	clk_unprepare(clk);
7ff550de RK	62	clk_put(clk);
	63	}
	64
	65	return rate;
	66	}
	67
a7bf6162 RH	68	static void __iomem *sched_clock_base;
a7bf6162 RH	69
9b12f3a8	70	static u64 notrace sp804_read(void)
a7bf6162 RH	71	{
	72	return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
	73	}
	74
1e5f0519 SH	75	void __init sp804_timer_disable(void __iomem *base)
	76	{
	77	writel(0, base + TIMER_CTRL);
	78	}
	79
2ef2538b	80	int __init __sp804_clocksource_and_sched_clock_init(void __iomem *base,
a7bf6162	81	const char *name,
7a0eca71	82	struct clk *clk,
a7bf6162	83	int use_sched_clock)
e3887714	84	{
7a0eca71 RH	85	long rate;
	86
	87	if (!clk) {
	88	clk = clk_get_sys("sp804", name);
	89	if (IS_ERR(clk)) {
	90	pr_err("sp804: clock not found: %d\n",
	91	(int)PTR_ERR(clk));
2ef2538b	92	return PTR_ERR(clk);
7a0eca71 RH	93	}
	94	}
	95
	96	rate = sp804_get_clock_rate(clk);
7ff550de	97	if (rate < 0)
2ef2538b	98	return -EINVAL;
7ff550de	99
e3887714	100	/* setup timer 0 as free-running clocksource */
bfe45e0b RK	101	writel(0, base + TIMER_CTRL);
	102	writel(0xffffffff, base + TIMER_LOAD);
	103	writel(0xffffffff, base + TIMER_VALUE);
e3887714	104	writel(TIMER_CTRL_32BIT \| TIMER_CTRL_ENABLE \| TIMER_CTRL_PERIODIC,
bfe45e0b	105	base + TIMER_CTRL);
e3887714	106
fb593cf3	107	clocksource_mmio_init(base + TIMER_VALUE, name,
7ff550de	108	rate, 200, 32, clocksource_mmio_readl_down);
a7bf6162 RH	109
	110	if (use_sched_clock) {
	111	sched_clock_base = base;
9b12f3a8	112	sched_clock_register(sp804_read, 32, rate);
a7bf6162	113	}
2ef2538b DL	114
2ef2538b DL	115	return 0;
e3887714 RK	116	}
	117
	118
	119	static void __iomem *clkevt_base;
23828a7a	120	static unsigned long clkevt_reload;
e3887714 RK	121
	122	/*
	123	* IRQ handler for the timer
	124	*/
	125	static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
	126	{
	127	struct clock_event_device *evt = dev_id;
	128
	129	/* clear the interrupt */
	130	writel(1, clkevt_base + TIMER_INTCLR);
	131
	132	evt->event_handler(evt);
	133
	134	return IRQ_HANDLED;
	135	}
	136
daea7283	137	static inline void timer_shutdown(struct clock_event_device *evt)
e3887714	138	{
daea7283 VK	139	writel(0, clkevt_base + TIMER_CTRL);
daea7283 VK	140	}
e3887714	141
daea7283 VK	142	static int sp804_shutdown(struct clock_event_device *evt)
	143	{
	144	timer_shutdown(evt);
	145	return 0;
	146	}
e3887714	147
daea7283 VK	148	static int sp804_set_periodic(struct clock_event_device *evt)
	149	{
	150	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
	151	TIMER_CTRL_PERIODIC \| TIMER_CTRL_ENABLE;
e3887714	152
daea7283 VK	153	timer_shutdown(evt);
daea7283 VK	154	writel(clkevt_reload, clkevt_base + TIMER_LOAD);
e3887714	155	writel(ctrl, clkevt_base + TIMER_CTRL);
daea7283	156	return 0;
e3887714 RK	157	}
	158
	159	static int sp804_set_next_event(unsigned long next,
	160	struct clock_event_device *evt)
	161	{
daea7283 VK	162	unsigned long ctrl = TIMER_CTRL_32BIT \| TIMER_CTRL_IE \|
daea7283 VK	163	TIMER_CTRL_ONESHOT \| TIMER_CTRL_ENABLE;
e3887714 RK	164
e3887714 RK	165	writel(next, clkevt_base + TIMER_LOAD);
daea7283	166	writel(ctrl, clkevt_base + TIMER_CTRL);
e3887714 RK	167
	168	return 0;
	169	}
	170
	171	static struct clock_event_device sp804_clockevent = {
daea7283 VK	172	.features = CLOCK_EVT_FEAT_PERIODIC \|
	173	CLOCK_EVT_FEAT_ONESHOT \|
	174	CLOCK_EVT_FEAT_DYNIRQ,
	175	.set_state_shutdown = sp804_shutdown,
	176	.set_state_periodic = sp804_set_periodic,
	177	.set_state_oneshot = sp804_shutdown,
	178	.tick_resume = sp804_shutdown,
	179	.set_next_event = sp804_set_next_event,
	180	.rating = 300,
e3887714 RK	181	};
	182
	183	static struct irqaction sp804_timer_irq = {
	184	.name = "timer",
728fae6f	185	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
e3887714 RK	186	.handler = sp804_timer_interrupt,
	187	.dev_id = &sp804_clockevent,
	188	};
	189
2ef2538b	190	int __init __sp804_clockevents_init(void __iomem base, unsigned int irq, struct clk clk, const char *name)
e3887714 RK	191	{
e3887714 RK	192	struct clock_event_device *evt = &sp804_clockevent;
7a0eca71 RH	193	long rate;
	194
	195	if (!clk)
	196	clk = clk_get_sys("sp804", name);
	197	if (IS_ERR(clk)) {
	198	pr_err("sp804: %s clock not found: %d\n", name,
	199	(int)PTR_ERR(clk));
2ef2538b	200	return PTR_ERR(clk);
7a0eca71	201	}
23828a7a	202
7a0eca71	203	rate = sp804_get_clock_rate(clk);
23828a7a	204	if (rate < 0)
2ef2538b	205	return -EINVAL;
e3887714 RK	206
e3887714 RK	207	clkevt_base = base;
23828a7a	208	clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
57cc4f7d RK	209	evt->name = name;
57cc4f7d RK	210	evt->irq = irq;
ea3aacf5	211	evt->cpumask = cpu_possible_mask;
e3887714	212
7a0eca71 RH	213	writel(0, base + TIMER_CTRL);
7a0eca71 RH	214
57cc4f7d	215	setup_irq(irq, &sp804_timer_irq);
7c324d83	216	clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
2ef2538b DL	217
2ef2538b DL	218	return 0;
e3887714	219	}
7a0eca71	220
2ef2538b	221	static int __init sp804_of_init(struct device_node *np)
7a0eca71 RH	222	{
	223	static bool initialized = false;
	224	void __iomem *base;
2ef2538b	225	int irq, ret = -EINVAL;
7a0eca71 RH	226	u32 irq_num = 0;
	227	struct clk clk1, clk2;
	228	const char *name = of_get_property(np, "compatible", NULL);
	229
	230	base = of_iomap(np, 0);
2ef2538b DL	231	if (!base)
2ef2538b DL	232	return -ENXIO;
7a0eca71 RH	233
	234	/* Ensure timers are disabled */
	235	writel(0, base + TIMER_CTRL);
	236	writel(0, base + TIMER_2_BASE + TIMER_CTRL);
	237
2ef2538b DL	238	if (initialized \|\| !of_device_is_available(np)) {
2ef2538b DL	239	ret = -EINVAL;
7a0eca71	240	goto err;
2ef2538b	241	}
7a0eca71 RH	242
	243	clk1 = of_clk_get(np, 0);
	244	if (IS_ERR(clk1))
	245	clk1 = NULL;
	246
1bde9906	247	/* Get the 2nd clock if the timer has 3 timer clocks */
7a0eca71 RH	248	if (of_count_phandle_with_args(np, "clocks", "#clock-cells") == 3) {
	249	clk2 = of_clk_get(np, 1);
	250	if (IS_ERR(clk2)) {
	251	pr_err("sp804: %s clock not found: %d\n", np->name,
	252	(int)PTR_ERR(clk2));
1bde9906	253	clk2 = NULL;
7a0eca71 RH	254	}
	255	} else
	256	clk2 = clk1;
	257
	258	irq = irq_of_parse_and_map(np, 0);
	259	if (irq <= 0)
	260	goto err;
	261
	262	of_property_read_u32(np, "arm,sp804-has-irq", &irq_num);
	263	if (irq_num == 2) {
2ef2538b DL	264
	265	ret = __sp804_clockevents_init(base + TIMER_2_BASE, irq, clk2, name);
	266	if (ret)
	267	goto err;
	268
	269	ret = __sp804_clocksource_and_sched_clock_init(base, name, clk1, 1);
	270	if (ret)
	271	goto err;
7a0eca71	272	} else {
2ef2538b DL	273
	274	ret = __sp804_clockevents_init(base, irq, clk1 , name);
	275	if (ret)
	276	goto err;
	277
	278	ret =__sp804_clocksource_and_sched_clock_init(base + TIMER_2_BASE,
	279	name, clk2, 1);
	280	if (ret)
	281	goto err;
7a0eca71 RH	282	}
	283	initialized = true;
	284
2ef2538b	285	return 0;
7a0eca71 RH	286	err:
7a0eca71 RH	287	iounmap(base);
2ef2538b	288	return ret;
7a0eca71	289	}
17273395	290	TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
870e2928	291
2ef2538b	292	static int __init integrator_cp_of_init(struct device_node *np)
870e2928 RH	293	{
	294	static int init_count = 0;
	295	void __iomem *base;
2ef2538b	296	int irq, ret = -EINVAL;
870e2928	297	const char *name = of_get_property(np, "compatible", NULL);
9cf31380	298	struct clk *clk;
870e2928 RH	299
870e2928 RH	300	base = of_iomap(np, 0);
2ef2538b	301	if (!base) {
ac9ce6d1	302	pr_err("Failed to iomap\n");
2ef2538b DL	303	return -ENXIO;
	304	}
	305
9cf31380	306	clk = of_clk_get(np, 0);
2ef2538b	307	if (IS_ERR(clk)) {
ac9ce6d1	308	pr_err("Failed to get clock\n");
2ef2538b DL	309	return PTR_ERR(clk);
2ef2538b DL	310	}
870e2928 RH	311
	312	/* Ensure timer is disabled */
	313	writel(0, base + TIMER_CTRL);
	314
	315	if (init_count == 2 \|\| !of_device_is_available(np))
	316	goto err;
	317
2ef2538b DL	318	if (!init_count) {
	319	ret = __sp804_clocksource_and_sched_clock_init(base, name, clk, 0);
	320	if (ret)
	321	goto err;
	322	} else {
870e2928 RH	323	irq = irq_of_parse_and_map(np, 0);
	324	if (irq <= 0)
	325	goto err;
	326
2ef2538b DL	327	ret = __sp804_clockevents_init(base, irq, clk, name);
	328	if (ret)
	329	goto err;
870e2928 RH	330	}
	331
	332	init_count++;
2ef2538b	333	return 0;
870e2928 RH	334	err:
870e2928 RH	335	iounmap(base);
2ef2538b	336	return ret;
870e2928	337	}
17273395	338	TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);