[mirror_ubuntu-zesty-kernel.git] / drivers / clocksource / timer-sun5i.c

/*
 * Allwinner SoCs hstimer driver.
 *
 * Copyright (C) 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>

#define TIMER_IRQ_EN_REG		0x00
#define TIMER_IRQ_EN(val)			BIT(val)
#define TIMER_IRQ_ST_REG		0x04
#define TIMER_CTL_REG(val)		(0x20 * (val) + 0x10)
#define TIMER_CTL_ENABLE			BIT(0)
#define TIMER_CTL_RELOAD			BIT(1)
#define TIMER_CTL_CLK_PRES(val)			(((val) & 0x7) << 4)
#define TIMER_CTL_ONESHOT			BIT(7)
#define TIMER_INTVAL_LO_REG(val)	(0x20 * (val) + 0x14)
#define TIMER_INTVAL_HI_REG(val)	(0x20 * (val) + 0x18)
#define TIMER_CNTVAL_LO_REG(val)	(0x20 * (val) + 0x1c)
#define TIMER_CNTVAL_HI_REG(val)	(0x20 * (val) + 0x20)

#define TIMER_SYNC_TICKS	3

struct sun5i_timer {
	void __iomem		*base;
	struct clk		*clk;
	struct notifier_block	clk_rate_cb;
	u32			ticks_per_jiffy;
};

#define to_sun5i_timer(x) \
	container_of(x, struct sun5i_timer, clk_rate_cb)

struct sun5i_timer_clksrc {
	struct sun5i_timer	timer;
	struct clocksource	clksrc;
};

#define to_sun5i_timer_clksrc(x) \
	container_of(x, struct sun5i_timer_clksrc, clksrc)

struct sun5i_timer_clkevt {
	struct sun5i_timer		timer;
	struct clock_event_device	clkevt;
};

#define to_sun5i_timer_clkevt(x) \
	container_of(x, struct sun5i_timer_clkevt, clkevt)

/*
 * When we disable a timer, we need to wait at least for 2 cycles of
 * the timer source clock. We will use for that the clocksource timer
 * that is already setup and runs at the same frequency than the other
 * timers, and we never will be disabled.
 */
static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
{
	u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));

	while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
		cpu_relax();
}

static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
{
	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
	writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));

	sun5i_clkevt_sync(ce);
}

static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
{
	writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
}

static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
{
	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));

	if (periodic)
		val &= ~TIMER_CTL_ONESHOT;
	else
		val |= TIMER_CTL_ONESHOT;

	writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       ce->timer.base + TIMER_CTL_REG(timer));
}

static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
{
	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);

	sun5i_clkevt_time_stop(ce, 0);
	return 0;
}

static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
{
	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);

	sun5i_clkevt_time_stop(ce, 0);
	sun5i_clkevt_time_start(ce, 0, false);
	return 0;
}

static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
{
	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);

	sun5i_clkevt_time_stop(ce, 0);
	sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
	sun5i_clkevt_time_start(ce, 0, true);
	return 0;
}

static int sun5i_clkevt_next_event(unsigned long evt,
				   struct clock_event_device *clkevt)
{
	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);

	sun5i_clkevt_time_stop(ce, 0);
	sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
	sun5i_clkevt_time_start(ce, 0, false);

	return 0;
}

static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
{
	struct sun5i_timer_clkevt *ce = (struct sun5i_timer_clkevt *)dev_id;

	writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
	ce->clkevt.event_handler(&ce->clkevt);

	return IRQ_HANDLED;
}

static u64 sun5i_clksrc_read(struct clocksource *clksrc)
{
	struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);

	return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
}

static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
				unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct sun5i_timer *timer = to_sun5i_timer(nb);
	struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);

	switch (event) {
	case PRE_RATE_CHANGE:
		clocksource_unregister(&cs->clksrc);
		break;

	case POST_RATE_CHANGE:
		clocksource_register_hz(&cs->clksrc, ndata->new_rate);
		break;

	default:
		break;
	}

	return NOTIFY_DONE;
}

static int __init sun5i_setup_clocksource(struct device_node *node,
					  void __iomem *base,
					  struct clk *clk, int irq)
{
	struct sun5i_timer_clksrc *cs;
	unsigned long rate;
	int ret;

	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	if (!cs)
		return -ENOMEM;

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Couldn't enable parent clock\n");
		goto err_free;
	}

	rate = clk_get_rate(clk);

	cs->timer.base = base;
	cs->timer.clk = clk;
	cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
	cs->timer.clk_rate_cb.next = NULL;

	ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
	if (ret) {
		pr_err("Unable to register clock notifier.\n");
		goto err_disable_clk;
	}

	writel(~0, base + TIMER_INTVAL_LO_REG(1));
	writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD,
	       base + TIMER_CTL_REG(1));

	cs->clksrc.name = node->name;
	cs->clksrc.rating = 340;
	cs->clksrc.read = sun5i_clksrc_read;
	cs->clksrc.mask = CLOCKSOURCE_MASK(32);
	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	ret = clocksource_register_hz(&cs->clksrc, rate);
	if (ret) {
		pr_err("Couldn't register clock source.\n");
		goto err_remove_notifier;
	}

	return 0;

err_remove_notifier:
	clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
err_disable_clk:
	clk_disable_unprepare(clk);
err_free:
	kfree(cs);
	return ret;
}

static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
				unsigned long event, void *data)
{
	struct clk_notifier_data *ndata = data;
	struct sun5i_timer *timer = to_sun5i_timer(nb);
	struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);

	if (event == POST_RATE_CHANGE) {
		clockevents_update_freq(&ce->clkevt, ndata->new_rate);
		ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
	}

	return NOTIFY_DONE;
}

static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem *base,
					 struct clk *clk, int irq)
{
	struct sun5i_timer_clkevt *ce;
	unsigned long rate;
	int ret;
	u32 val;

	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	if (!ce)
		return -ENOMEM;

	ret = clk_prepare_enable(clk);
	if (ret) {
		pr_err("Couldn't enable parent clock\n");
		goto err_free;
	}

	rate = clk_get_rate(clk);

	ce->timer.base = base;
	ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
	ce->timer.clk = clk;
	ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
	ce->timer.clk_rate_cb.next = NULL;

	ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
	if (ret) {
		pr_err("Unable to register clock notifier.\n");
		goto err_disable_clk;
	}

	ce->clkevt.name = node->name;
	ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ce->clkevt.set_next_event = sun5i_clkevt_next_event;
	ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
	ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
	ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
	ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
	ce->clkevt.rating = 340;
	ce->clkevt.irq = irq;
	ce->clkevt.cpumask = cpu_possible_mask;

	/* Enable timer0 interrupt */
	val = readl(base + TIMER_IRQ_EN_REG);
	writel(val | TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);

	clockevents_config_and_register(&ce->clkevt, rate,
					TIMER_SYNC_TICKS, 0xffffffff);

	ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
			  "sun5i_timer0", ce);
	if (ret) {
		pr_err("Unable to register interrupt\n");
		goto err_remove_notifier;
	}

	return 0;

err_remove_notifier:
	clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
err_disable_clk:
	clk_disable_unprepare(clk);
err_free:
	kfree(ce);
	return ret;
}

static int __init sun5i_timer_init(struct device_node *node)
{
	struct reset_control *rstc;
	void __iomem *timer_base;
	struct clk *clk;
	int irq, ret;

	timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
	if (IS_ERR(timer_base)) {
		pr_err("Can't map registers");
		return PTR_ERR(timer_base);;
	}

	irq = irq_of_parse_and_map(node, 0);
	if (irq <= 0) {
		pr_err("Can't parse IRQ");
		return -EINVAL;
	}

	clk = of_clk_get(node, 0);
	if (IS_ERR(clk)) {
		pr_err("Can't get timer clock");
		return PTR_ERR(clk);
	}

	rstc = of_reset_control_get(node, NULL);
	if (!IS_ERR(rstc))
		reset_control_deassert(rstc);

	ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
	if (ret)
		return ret;

	return sun5i_setup_clockevent(node, timer_base, clk, irq);
}
CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
			   sun5i_timer_init);
CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
			   sun5i_timer_init);
Commit	Line	Data
67905540 MR	1	/*
	2	* Allwinner SoCs hstimer driver.
	3	*
	4	* Copyright (C) 2013 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/clk.h>
	14	#include <linux/clockchips.h>
	15	#include <linux/delay.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/irqreturn.h>
e50a00be	19	#include <linux/reset.h>
4a59058f	20	#include <linux/slab.h>
67905540 MR	21	#include <linux/of.h>
	22	#include <linux/of_address.h>
	23	#include <linux/of_irq.h>
	24
	25	#define TIMER_IRQ_EN_REG 0x00
	26	#define TIMER_IRQ_EN(val) BIT(val)
	27	#define TIMER_IRQ_ST_REG 0x04
	28	#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10)
	29	#define TIMER_CTL_ENABLE BIT(0)
	30	#define TIMER_CTL_RELOAD BIT(1)
	31	#define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4)
	32	#define TIMER_CTL_ONESHOT BIT(7)
	33	#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14)
	34	#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18)
	35	#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c)
	36	#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20)
	37
	38	#define TIMER_SYNC_TICKS 3
	39
4a59058f MR	40	struct sun5i_timer {
	41	void __iomem *base;
	42	struct clk *clk;
3071efa4	43	struct notifier_block clk_rate_cb;
4a59058f MR	44	u32 ticks_per_jiffy;
	45	};
	46
3071efa4 MR	47	#define to_sun5i_timer(x) \
	48	container_of(x, struct sun5i_timer, clk_rate_cb)
	49
4a59058f MR	50	struct sun5i_timer_clksrc {
	51	struct sun5i_timer timer;
	52	struct clocksource clksrc;
	53	};
	54
	55	#define to_sun5i_timer_clksrc(x) \
	56	container_of(x, struct sun5i_timer_clksrc, clksrc)
	57
	58	struct sun5i_timer_clkevt {
	59	struct sun5i_timer timer;
	60	struct clock_event_device clkevt;
	61	};
	62
	63	#define to_sun5i_timer_clkevt(x) \
	64	container_of(x, struct sun5i_timer_clkevt, clkevt)
67905540 MR	65
	66	/*
	67	* When we disable a timer, we need to wait at least for 2 cycles of
	68	* the timer source clock. We will use for that the clocksource timer
	69	* that is already setup and runs at the same frequency than the other
	70	* timers, and we never will be disabled.
	71	*/
4a59058f	72	static void sun5i_clkevt_sync(struct sun5i_timer_clkevt *ce)
67905540	73	{
4a59058f	74	u32 old = readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1));
67905540	75
4a59058f	76	while ((old - readl(ce->timer.base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICKS)
67905540 MR	77	cpu_relax();
	78	}
	79
4a59058f	80	static void sun5i_clkevt_time_stop(struct sun5i_timer_clkevt *ce, u8 timer)
67905540	81	{
4a59058f MR	82	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
4a59058f MR	83	writel(val & ~TIMER_CTL_ENABLE, ce->timer.base + TIMER_CTL_REG(timer));
67905540	84
4a59058f	85	sun5i_clkevt_sync(ce);
67905540 MR	86	}
67905540 MR	87
4a59058f	88	static void sun5i_clkevt_time_setup(struct sun5i_timer_clkevt *ce, u8 timer, u32 delay)
67905540	89	{
4a59058f	90	writel(delay, ce->timer.base + TIMER_INTVAL_LO_REG(timer));
67905540 MR	91	}
67905540 MR	92
4a59058f	93	static void sun5i_clkevt_time_start(struct sun5i_timer_clkevt *ce, u8 timer, bool periodic)
67905540	94	{
4a59058f	95	u32 val = readl(ce->timer.base + TIMER_CTL_REG(timer));
67905540 MR	96
	97	if (periodic)
	98	val &= ~TIMER_CTL_ONESHOT;
	99	else
	100	val \|= TIMER_CTL_ONESHOT;
	101
	102	writel(val \| TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
4a59058f	103	ce->timer.base + TIMER_CTL_REG(timer));
67905540 MR	104	}
67905540 MR	105
7486f5ad	106	static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt)
67905540	107	{
4a59058f MR	108	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
4a59058f MR	109
7486f5ad VK	110	sun5i_clkevt_time_stop(ce, 0);
	111	return 0;
	112	}
	113
	114	static int sun5i_clkevt_set_oneshot(struct clock_event_device *clkevt)
	115	{
	116	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
	117
	118	sun5i_clkevt_time_stop(ce, 0);
	119	sun5i_clkevt_time_start(ce, 0, false);
	120	return 0;
	121	}
	122
	123	static int sun5i_clkevt_set_periodic(struct clock_event_device *clkevt)
	124	{
	125	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
	126
	127	sun5i_clkevt_time_stop(ce, 0);
	128	sun5i_clkevt_time_setup(ce, 0, ce->timer.ticks_per_jiffy);
	129	sun5i_clkevt_time_start(ce, 0, true);
	130	return 0;
67905540 MR	131	}
	132
	133	static int sun5i_clkevt_next_event(unsigned long evt,
4a59058f	134	struct clock_event_device *clkevt)
67905540	135	{
4a59058f MR	136	struct sun5i_timer_clkevt *ce = to_sun5i_timer_clkevt(clkevt);
	137
	138	sun5i_clkevt_time_stop(ce, 0);
	139	sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
	140	sun5i_clkevt_time_start(ce, 0, false);
67905540 MR	141
	142	return 0;
	143	}
	144
67905540 MR	145	static irqreturn_t sun5i_timer_interrupt(int irq, void *dev_id)
67905540 MR	146	{
4a59058f	147	struct sun5i_timer_clkevt ce = (struct sun5i_timer_clkevt )dev_id;
67905540	148
4a59058f MR	149	writel(0x1, ce->timer.base + TIMER_IRQ_ST_REG);
4a59058f MR	150	ce->clkevt.event_handler(&ce->clkevt);
67905540 MR	151
	152	return IRQ_HANDLED;
	153	}
	154
a5a1d1c2	155	static u64 sun5i_clksrc_read(struct clocksource *clksrc)
59387683 CYT	156	{
	157	struct sun5i_timer_clksrc *cs = to_sun5i_timer_clksrc(clksrc);
	158
	159	return ~readl(cs->timer.base + TIMER_CNTVAL_LO_REG(1));
	160	}
	161
3071efa4 MR	162	static int sun5i_rate_cb_clksrc(struct notifier_block *nb,
	163	unsigned long event, void *data)
	164	{
	165	struct clk_notifier_data *ndata = data;
	166	struct sun5i_timer *timer = to_sun5i_timer(nb);
	167	struct sun5i_timer_clksrc *cs = container_of(timer, struct sun5i_timer_clksrc, timer);
	168
	169	switch (event) {
	170	case PRE_RATE_CHANGE:
	171	clocksource_unregister(&cs->clksrc);
	172	break;
	173
	174	case POST_RATE_CHANGE:
	175	clocksource_register_hz(&cs->clksrc, ndata->new_rate);
	176	break;
	177
	178	default:
	179	break;
	180	}
	181
	182	return NOTIFY_DONE;
	183	}
	184
4a59058f MR	185	static int __init sun5i_setup_clocksource(struct device_node *node,
	186	void __iomem *base,
	187	struct clk *clk, int irq)
	188	{
	189	struct sun5i_timer_clksrc *cs;
	190	unsigned long rate;
	191	int ret;
	192
	193	cs = kzalloc(sizeof(*cs), GFP_KERNEL);
	194	if (!cs)
	195	return -ENOMEM;
	196
	197	ret = clk_prepare_enable(clk);
	198	if (ret) {
	199	pr_err("Couldn't enable parent clock\n");
	200	goto err_free;
	201	}
	202
	203	rate = clk_get_rate(clk);
	204
	205	cs->timer.base = base;
	206	cs->timer.clk = clk;
3071efa4 MR	207	cs->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clksrc;
	208	cs->timer.clk_rate_cb.next = NULL;
	209
	210	ret = clk_notifier_register(clk, &cs->timer.clk_rate_cb);
	211	if (ret) {
	212	pr_err("Unable to register clock notifier.\n");
	213	goto err_disable_clk;
	214	}
4a59058f MR	215
	216	writel(~0, base + TIMER_INTVAL_LO_REG(1));
	217	writel(TIMER_CTL_ENABLE \| TIMER_CTL_RELOAD,
	218	base + TIMER_CTL_REG(1));
	219
59387683 CYT	220	cs->clksrc.name = node->name;
	221	cs->clksrc.rating = 340;
	222	cs->clksrc.read = sun5i_clksrc_read;
	223	cs->clksrc.mask = CLOCKSOURCE_MASK(32);
	224	cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	225
	226	ret = clocksource_register_hz(&cs->clksrc, rate);
4a59058f MR	227	if (ret) {
4a59058f MR	228	pr_err("Couldn't register clock source.\n");
3071efa4	229	goto err_remove_notifier;
4a59058f MR	230	}
	231
	232	return 0;
	233
3071efa4 MR	234	err_remove_notifier:
3071efa4 MR	235	clk_notifier_unregister(clk, &cs->timer.clk_rate_cb);
4a59058f MR	236	err_disable_clk:
	237	clk_disable_unprepare(clk);
	238	err_free:
	239	kfree(cs);
	240	return ret;
	241	}
	242
3071efa4 MR	243	static int sun5i_rate_cb_clkevt(struct notifier_block *nb,
	244	unsigned long event, void *data)
	245	{
	246	struct clk_notifier_data *ndata = data;
	247	struct sun5i_timer *timer = to_sun5i_timer(nb);
	248	struct sun5i_timer_clkevt *ce = container_of(timer, struct sun5i_timer_clkevt, timer);
	249
	250	if (event == POST_RATE_CHANGE) {
	251	clockevents_update_freq(&ce->clkevt, ndata->new_rate);
	252	ce->timer.ticks_per_jiffy = DIV_ROUND_UP(ndata->new_rate, HZ);
	253	}
	254
	255	return NOTIFY_DONE;
	256	}
	257
4a59058f MR	258	static int __init sun5i_setup_clockevent(struct device_node node, void __iomem base,
	259	struct clk *clk, int irq)
	260	{
	261	struct sun5i_timer_clkevt *ce;
	262	unsigned long rate;
	263	int ret;
	264	u32 val;
	265
	266	ce = kzalloc(sizeof(*ce), GFP_KERNEL);
	267	if (!ce)
	268	return -ENOMEM;
	269
	270	ret = clk_prepare_enable(clk);
	271	if (ret) {
	272	pr_err("Couldn't enable parent clock\n");
	273	goto err_free;
	274	}
	275
	276	rate = clk_get_rate(clk);
	277
	278	ce->timer.base = base;
	279	ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
	280	ce->timer.clk = clk;
3071efa4 MR	281	ce->timer.clk_rate_cb.notifier_call = sun5i_rate_cb_clkevt;
	282	ce->timer.clk_rate_cb.next = NULL;
	283
	284	ret = clk_notifier_register(clk, &ce->timer.clk_rate_cb);
	285	if (ret) {
	286	pr_err("Unable to register clock notifier.\n");
	287	goto err_disable_clk;
	288	}
4a59058f MR	289
	290	ce->clkevt.name = node->name;
	291	ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
	292	ce->clkevt.set_next_event = sun5i_clkevt_next_event;
7486f5ad VK	293	ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
	294	ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
	295	ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
	296	ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
4a59058f MR	297	ce->clkevt.rating = 340;
	298	ce->clkevt.irq = irq;
	299	ce->clkevt.cpumask = cpu_possible_mask;
	300
	301	/* Enable timer0 interrupt */
	302	val = readl(base + TIMER_IRQ_EN_REG);
	303	writel(val \| TIMER_IRQ_EN(0), base + TIMER_IRQ_EN_REG);
	304
	305	clockevents_config_and_register(&ce->clkevt, rate,
	306	TIMER_SYNC_TICKS, 0xffffffff);
	307
	308	ret = request_irq(irq, sun5i_timer_interrupt, IRQF_TIMER \| IRQF_IRQPOLL,
	309	"sun5i_timer0", ce);
	310	if (ret) {
	311	pr_err("Unable to register interrupt\n");
3071efa4	312	goto err_remove_notifier;
4a59058f MR	313	}
	314
	315	return 0;
	316
3071efa4 MR	317	err_remove_notifier:
3071efa4 MR	318	clk_notifier_unregister(clk, &ce->timer.clk_rate_cb);
4a59058f MR	319	err_disable_clk:
	320	clk_disable_unprepare(clk);
	321	err_free:
	322	kfree(ce);
	323	return ret;
	324	}
	325
e4d9f2ee	326	static int __init sun5i_timer_init(struct device_node *node)
67905540	327	{
e50a00be	328	struct reset_control *rstc;
4a59058f	329	void __iomem *timer_base;
67905540	330	struct clk *clk;
e4d9f2ee	331	int irq, ret;
67905540	332
a45860d0	333	timer_base = of_io_request_and_map(node, 0, of_node_full_name(node));
e4d9f2ee DL	334	if (IS_ERR(timer_base)) {
	335	pr_err("Can't map registers");
	336	return PTR_ERR(timer_base);;
	337	}
67905540 MR	338
67905540 MR	339	irq = irq_of_parse_and_map(node, 0);
e4d9f2ee DL	340	if (irq <= 0) {
	341	pr_err("Can't parse IRQ");
	342	return -EINVAL;
	343	}
67905540 MR	344
67905540 MR	345	clk = of_clk_get(node, 0);
e4d9f2ee DL	346	if (IS_ERR(clk)) {
	347	pr_err("Can't get timer clock");
	348	return PTR_ERR(clk);
	349	}
67905540	350
e50a00be MR	351	rstc = of_reset_control_get(node, NULL);
	352	if (!IS_ERR(rstc))
	353	reset_control_deassert(rstc);
	354
e4d9f2ee DL	355	ret = sun5i_setup_clocksource(node, timer_base, clk, irq);
	356	if (ret)
	357	return ret;
	358
	359	return sun5i_setup_clockevent(node, timer_base, clk, irq);
67905540	360	}
177cf6e5	361	CLOCKSOURCE_OF_DECLARE(sun5i_a13, "allwinner,sun5i-a13-hstimer",
e4d9f2ee	362	sun5i_timer_init);
177cf6e5	363	CLOCKSOURCE_OF_DECLARE(sun7i_a20, "allwinner,sun7i-a20-hstimer",
e4d9f2ee	364	sun5i_timer_init);