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Commit | Line | Data |
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92105bb7 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/dmtimer.c | |
3 | * | |
4 | * OMAP Dual-Mode Timers | |
5 | * | |
97933d6c TKD |
6 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ |
7 | * Tarun Kanti DebBarma <tarun.kanti@ti.com> | |
8 | * Thara Gopinath <thara@ti.com> | |
9 | * | |
10 | * dmtimer adaptation to platform_driver. | |
11 | * | |
92105bb7 | 12 | * Copyright (C) 2005 Nokia Corporation |
77900a2f TT |
13 | * OMAP2 support by Juha Yrjola |
14 | * API improvements and OMAP2 clock framework support by Timo Teras | |
92105bb7 | 15 | * |
44169075 SS |
16 | * Copyright (C) 2009 Texas Instruments |
17 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
18 | * | |
92105bb7 TL |
19 | * This program is free software; you can redistribute it and/or modify it |
20 | * under the terms of the GNU General Public License as published by the | |
21 | * Free Software Foundation; either version 2 of the License, or (at your | |
22 | * option) any later version. | |
23 | * | |
24 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
25 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
26 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
27 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
28 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
29 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
30 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
31 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 | * | |
33 | * You should have received a copy of the GNU General Public License along | |
34 | * with this program; if not, write to the Free Software Foundation, Inc., | |
35 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
36 | */ | |
37 | ||
b1538832 | 38 | #include <linux/clk.h> |
ea05d2ea | 39 | #include <linux/clk-provider.h> |
869dec15 | 40 | #include <linux/module.h> |
fced80c7 | 41 | #include <linux/io.h> |
74dd9ec6 | 42 | #include <linux/device.h> |
3392cdd3 | 43 | #include <linux/err.h> |
ffe07cea | 44 | #include <linux/pm_runtime.h> |
9725f445 JH |
45 | #include <linux/of.h> |
46 | #include <linux/of_device.h> | |
40fc3bb5 JH |
47 | #include <linux/platform_device.h> |
48 | #include <linux/platform_data/dmtimer-omap.h> | |
44169075 | 49 | |
5ca467c4 | 50 | #include <clocksource/timer-ti-dm.h> |
2c799cef | 51 | |
b7b4ff76 | 52 | static u32 omap_reserved_systimers; |
df28472a | 53 | static LIST_HEAD(omap_timer_list); |
3392cdd3 | 54 | static DEFINE_SPINLOCK(dm_timer_lock); |
92105bb7 | 55 | |
8fc7fcb5 JH |
56 | enum { |
57 | REQUEST_ANY = 0, | |
58 | REQUEST_BY_ID, | |
59 | REQUEST_BY_CAP, | |
60 | REQUEST_BY_NODE, | |
61 | }; | |
62 | ||
3392cdd3 TKD |
63 | /** |
64 | * omap_dm_timer_read_reg - read timer registers in posted and non-posted mode | |
65 | * @timer: timer pointer over which read operation to perform | |
66 | * @reg: lowest byte holds the register offset | |
67 | * | |
68 | * The posted mode bit is encoded in reg. Note that in posted mode write | |
69 | * pending bit must be checked. Otherwise a read of a non completed write | |
70 | * will produce an error. | |
0f0d0807 RW |
71 | */ |
72 | static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg) | |
77900a2f | 73 | { |
ee17f114 TL |
74 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
75 | return __omap_dm_timer_read(timer, reg, timer->posted); | |
77900a2f | 76 | } |
92105bb7 | 77 | |
3392cdd3 TKD |
78 | /** |
79 | * omap_dm_timer_write_reg - write timer registers in posted and non-posted mode | |
80 | * @timer: timer pointer over which write operation is to perform | |
81 | * @reg: lowest byte holds the register offset | |
82 | * @value: data to write into the register | |
83 | * | |
84 | * The posted mode bit is encoded in reg. Note that in posted mode the write | |
85 | * pending bit must be checked. Otherwise a write on a register which has a | |
86 | * pending write will be lost. | |
0f0d0807 RW |
87 | */ |
88 | static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg, | |
89 | u32 value) | |
92105bb7 | 90 | { |
ee17f114 TL |
91 | WARN_ON((reg & 0xff) < _OMAP_TIMER_WAKEUP_EN_OFFSET); |
92 | __omap_dm_timer_write(timer, reg, value, timer->posted); | |
92105bb7 TL |
93 | } |
94 | ||
b481113a TKD |
95 | static void omap_timer_restore_context(struct omap_dm_timer *timer) |
96 | { | |
b481113a TKD |
97 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, |
98 | timer->context.twer); | |
99 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, | |
100 | timer->context.tcrr); | |
101 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, | |
102 | timer->context.tldr); | |
103 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, | |
104 | timer->context.tmar); | |
105 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, | |
106 | timer->context.tsicr); | |
834cacfb | 107 | writel_relaxed(timer->context.tier, timer->irq_ena); |
b481113a TKD |
108 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, |
109 | timer->context.tclr); | |
110 | } | |
111 | ||
ae6672cb | 112 | static int omap_dm_timer_reset(struct omap_dm_timer *timer) |
92105bb7 | 113 | { |
ae6672cb | 114 | u32 l, timeout = 100000; |
77900a2f | 115 | |
ae6672cb JH |
116 | if (timer->revision != 1) |
117 | return -EINVAL; | |
ee17f114 | 118 | |
ae6672cb JH |
119 | omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); |
120 | ||
121 | do { | |
122 | l = __omap_dm_timer_read(timer, | |
123 | OMAP_TIMER_V1_SYS_STAT_OFFSET, 0); | |
124 | } while (!l && timeout--); | |
125 | ||
126 | if (!timeout) { | |
127 | dev_err(&timer->pdev->dev, "Timer failed to reset\n"); | |
128 | return -ETIMEDOUT; | |
77900a2f | 129 | } |
92105bb7 | 130 | |
ae6672cb JH |
131 | /* Configure timer for smart-idle mode */ |
132 | l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0); | |
133 | l |= 0x2 << 0x3; | |
134 | __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0); | |
135 | ||
136 | timer->posted = 0; | |
137 | ||
138 | return 0; | |
77900a2f TT |
139 | } |
140 | ||
31a7448f NA |
141 | static int omap_dm_timer_of_set_source(struct omap_dm_timer *timer) |
142 | { | |
143 | int ret; | |
144 | struct clk *parent; | |
145 | ||
146 | /* | |
147 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
148 | * do not call clk_get() for these devices. | |
149 | */ | |
150 | if (!timer->fclk) | |
151 | return -ENODEV; | |
152 | ||
153 | parent = clk_get(&timer->pdev->dev, NULL); | |
154 | if (IS_ERR(parent)) | |
155 | return -ENODEV; | |
156 | ||
157 | ret = clk_set_parent(timer->fclk, parent); | |
158 | if (ret < 0) | |
159 | pr_err("%s: failed to set parent\n", __func__); | |
160 | ||
161 | clk_put(parent); | |
162 | ||
163 | return ret; | |
164 | } | |
165 | ||
592ea6bd LM |
166 | static int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) |
167 | { | |
168 | int ret; | |
ad6e4b6f | 169 | const char *parent_name; |
592ea6bd LM |
170 | struct clk *parent; |
171 | struct dmtimer_platform_data *pdata; | |
172 | ||
ad6e4b6f | 173 | if (unlikely(!timer) || IS_ERR(timer->fclk)) |
592ea6bd LM |
174 | return -EINVAL; |
175 | ||
ad6e4b6f LM |
176 | switch (source) { |
177 | case OMAP_TIMER_SRC_SYS_CLK: | |
178 | parent_name = "timer_sys_ck"; | |
179 | break; | |
180 | case OMAP_TIMER_SRC_32_KHZ: | |
181 | parent_name = "timer_32k_ck"; | |
182 | break; | |
183 | case OMAP_TIMER_SRC_EXT_CLK: | |
184 | parent_name = "timer_ext_ck"; | |
185 | break; | |
186 | default: | |
592ea6bd | 187 | return -EINVAL; |
ad6e4b6f LM |
188 | } |
189 | ||
190 | pdata = timer->pdev->dev.platform_data; | |
592ea6bd LM |
191 | |
192 | /* | |
193 | * FIXME: Used for OMAP1 devices only because they do not currently | |
194 | * use the clock framework to set the parent clock. To be removed | |
195 | * once OMAP1 migrated to using clock framework for dmtimers | |
196 | */ | |
197 | if (pdata && pdata->set_timer_src) | |
198 | return pdata->set_timer_src(timer->pdev, source); | |
199 | ||
592ea6bd LM |
200 | #if defined(CONFIG_COMMON_CLK) |
201 | /* Check if the clock has configurable parents */ | |
202 | if (clk_hw_get_num_parents(__clk_get_hw(timer->fclk)) < 2) | |
203 | return 0; | |
204 | #endif | |
205 | ||
592ea6bd LM |
206 | parent = clk_get(&timer->pdev->dev, parent_name); |
207 | if (IS_ERR(parent)) { | |
208 | pr_err("%s: %s not found\n", __func__, parent_name); | |
209 | return -EINVAL; | |
210 | } | |
211 | ||
212 | ret = clk_set_parent(timer->fclk, parent); | |
213 | if (ret < 0) | |
214 | pr_err("%s: failed to set %s as parent\n", __func__, | |
215 | parent_name); | |
216 | ||
217 | clk_put(parent); | |
218 | ||
219 | return ret; | |
220 | } | |
221 | ||
222 | static void omap_dm_timer_enable(struct omap_dm_timer *timer) | |
223 | { | |
224 | int c; | |
225 | ||
226 | pm_runtime_get_sync(&timer->pdev->dev); | |
227 | ||
228 | if (!(timer->capability & OMAP_TIMER_ALWON)) { | |
229 | if (timer->get_context_loss_count) { | |
230 | c = timer->get_context_loss_count(&timer->pdev->dev); | |
231 | if (c != timer->ctx_loss_count) { | |
232 | omap_timer_restore_context(timer); | |
233 | timer->ctx_loss_count = c; | |
234 | } | |
235 | } else { | |
236 | omap_timer_restore_context(timer); | |
237 | } | |
238 | } | |
239 | } | |
240 | ||
241 | static void omap_dm_timer_disable(struct omap_dm_timer *timer) | |
242 | { | |
243 | pm_runtime_put_sync(&timer->pdev->dev); | |
244 | } | |
245 | ||
b0cadb3c | 246 | static int omap_dm_timer_prepare(struct omap_dm_timer *timer) |
77900a2f | 247 | { |
ae6672cb JH |
248 | int rc; |
249 | ||
bca45808 JH |
250 | /* |
251 | * FIXME: OMAP1 devices do not use the clock framework for dmtimers so | |
252 | * do not call clk_get() for these devices. | |
253 | */ | |
254 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { | |
255 | timer->fclk = clk_get(&timer->pdev->dev, "fck"); | |
86287958 | 256 | if (WARN_ON_ONCE(IS_ERR(timer->fclk))) { |
bca45808 JH |
257 | dev_err(&timer->pdev->dev, ": No fclk handle.\n"); |
258 | return -EINVAL; | |
259 | } | |
3392cdd3 TKD |
260 | } |
261 | ||
7b44cf2c JH |
262 | omap_dm_timer_enable(timer); |
263 | ||
ae6672cb JH |
264 | if (timer->capability & OMAP_TIMER_NEEDS_RESET) { |
265 | rc = omap_dm_timer_reset(timer); | |
266 | if (rc) { | |
267 | omap_dm_timer_disable(timer); | |
268 | return rc; | |
269 | } | |
270 | } | |
3392cdd3 | 271 | |
7b44cf2c JH |
272 | __omap_dm_timer_enable_posted(timer); |
273 | omap_dm_timer_disable(timer); | |
3392cdd3 | 274 | |
31a7448f NA |
275 | rc = omap_dm_timer_of_set_source(timer); |
276 | if (rc == -ENODEV) | |
277 | return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); | |
278 | ||
279 | return rc; | |
77900a2f TT |
280 | } |
281 | ||
b7b4ff76 JH |
282 | static inline u32 omap_dm_timer_reserved_systimer(int id) |
283 | { | |
284 | return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0; | |
285 | } | |
286 | ||
287 | int omap_dm_timer_reserve_systimer(int id) | |
288 | { | |
289 | if (omap_dm_timer_reserved_systimer(id)) | |
290 | return -ENODEV; | |
291 | ||
292 | omap_reserved_systimers |= (1 << (id - 1)); | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
8fc7fcb5 | 297 | static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data) |
77900a2f | 298 | { |
3392cdd3 | 299 | struct omap_dm_timer *timer = NULL, *t; |
8fc7fcb5 | 300 | struct device_node *np = NULL; |
77900a2f | 301 | unsigned long flags; |
8fc7fcb5 JH |
302 | u32 cap = 0; |
303 | int id = 0; | |
304 | ||
305 | switch (req_type) { | |
306 | case REQUEST_BY_ID: | |
307 | id = *(int *)data; | |
308 | break; | |
309 | case REQUEST_BY_CAP: | |
310 | cap = *(u32 *)data; | |
311 | break; | |
312 | case REQUEST_BY_NODE: | |
313 | np = (struct device_node *)data; | |
314 | break; | |
315 | default: | |
316 | /* REQUEST_ANY */ | |
317 | break; | |
318 | } | |
77900a2f TT |
319 | |
320 | spin_lock_irqsave(&dm_timer_lock, flags); | |
3392cdd3 TKD |
321 | list_for_each_entry(t, &omap_timer_list, node) { |
322 | if (t->reserved) | |
77900a2f TT |
323 | continue; |
324 | ||
8fc7fcb5 JH |
325 | switch (req_type) { |
326 | case REQUEST_BY_ID: | |
327 | if (id == t->pdev->id) { | |
328 | timer = t; | |
329 | timer->reserved = 1; | |
330 | goto found; | |
331 | } | |
332 | break; | |
333 | case REQUEST_BY_CAP: | |
334 | if (cap == (t->capability & cap)) { | |
335 | /* | |
336 | * If timer is not NULL, we have already found | |
28fd7e99 ME |
337 | * one timer. But it was not an exact match |
338 | * because it had more capabilities than what | |
8fc7fcb5 JH |
339 | * was required. Therefore, unreserve the last |
340 | * timer found and see if this one is a better | |
341 | * match. | |
342 | */ | |
343 | if (timer) | |
344 | timer->reserved = 0; | |
345 | timer = t; | |
346 | timer->reserved = 1; | |
347 | ||
348 | /* Exit loop early if we find an exact match */ | |
349 | if (t->capability == cap) | |
350 | goto found; | |
351 | } | |
352 | break; | |
353 | case REQUEST_BY_NODE: | |
354 | if (np == t->pdev->dev.of_node) { | |
355 | timer = t; | |
356 | timer->reserved = 1; | |
357 | goto found; | |
358 | } | |
359 | break; | |
360 | default: | |
361 | /* REQUEST_ANY */ | |
362 | timer = t; | |
363 | timer->reserved = 1; | |
364 | goto found; | |
365 | } | |
77900a2f | 366 | } |
8fc7fcb5 | 367 | found: |
c5491d1a | 368 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
3392cdd3 | 369 | |
8fc7fcb5 JH |
370 | if (timer && omap_dm_timer_prepare(timer)) { |
371 | timer->reserved = 0; | |
372 | timer = NULL; | |
3392cdd3 | 373 | } |
77900a2f | 374 | |
3392cdd3 TKD |
375 | if (!timer) |
376 | pr_debug("%s: timer request failed!\n", __func__); | |
83379c81 | 377 | |
77900a2f TT |
378 | return timer; |
379 | } | |
8fc7fcb5 | 380 | |
592ea6bd | 381 | static struct omap_dm_timer *omap_dm_timer_request(void) |
8fc7fcb5 JH |
382 | { |
383 | return _omap_dm_timer_request(REQUEST_ANY, NULL); | |
384 | } | |
77900a2f | 385 | |
592ea6bd | 386 | static struct omap_dm_timer *omap_dm_timer_request_specific(int id) |
92105bb7 | 387 | { |
9725f445 JH |
388 | /* Requesting timer by ID is not supported when device tree is used */ |
389 | if (of_have_populated_dt()) { | |
592ea6bd | 390 | pr_warn("%s: Please use omap_dm_timer_request_by_node()\n", |
9725f445 JH |
391 | __func__); |
392 | return NULL; | |
393 | } | |
394 | ||
8fc7fcb5 | 395 | return _omap_dm_timer_request(REQUEST_BY_ID, &id); |
92105bb7 TL |
396 | } |
397 | ||
373fe0bd JH |
398 | /** |
399 | * omap_dm_timer_request_by_cap - Request a timer by capability | |
400 | * @cap: Bit mask of capabilities to match | |
401 | * | |
402 | * Find a timer based upon capabilities bit mask. Callers of this function | |
403 | * should use the definitions found in the plat/dmtimer.h file under the | |
404 | * comment "timer capabilities used in hwmod database". Returns pointer to | |
405 | * timer handle on success and a NULL pointer on failure. | |
406 | */ | |
407 | struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap) | |
408 | { | |
8fc7fcb5 JH |
409 | return _omap_dm_timer_request(REQUEST_BY_CAP, &cap); |
410 | } | |
373fe0bd | 411 | |
8fc7fcb5 JH |
412 | /** |
413 | * omap_dm_timer_request_by_node - Request a timer by device-tree node | |
414 | * @np: Pointer to device-tree timer node | |
415 | * | |
416 | * Request a timer based upon a device node pointer. Returns pointer to | |
417 | * timer handle on success and a NULL pointer on failure. | |
418 | */ | |
592ea6bd | 419 | static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np) |
8fc7fcb5 JH |
420 | { |
421 | if (!np) | |
373fe0bd JH |
422 | return NULL; |
423 | ||
8fc7fcb5 | 424 | return _omap_dm_timer_request(REQUEST_BY_NODE, np); |
373fe0bd | 425 | } |
373fe0bd | 426 | |
592ea6bd | 427 | static int omap_dm_timer_free(struct omap_dm_timer *timer) |
77900a2f | 428 | { |
ab4eb8b0 TKD |
429 | if (unlikely(!timer)) |
430 | return -EINVAL; | |
431 | ||
3392cdd3 | 432 | clk_put(timer->fclk); |
fa4bb626 | 433 | |
77900a2f TT |
434 | WARN_ON(!timer->reserved); |
435 | timer->reserved = 0; | |
ab4eb8b0 | 436 | return 0; |
77900a2f TT |
437 | } |
438 | ||
439 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) | |
440 | { | |
ab4eb8b0 TKD |
441 | if (timer) |
442 | return timer->irq; | |
443 | return -EINVAL; | |
77900a2f TT |
444 | } |
445 | ||
446 | #if defined(CONFIG_ARCH_OMAP1) | |
7136f8d8 | 447 | #include <mach/hardware.h> |
592ea6bd LM |
448 | |
449 | static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | |
450 | { | |
451 | return NULL; | |
452 | } | |
453 | ||
a569c6ec TL |
454 | /** |
455 | * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR | |
456 | * @inputmask: current value of idlect mask | |
457 | */ | |
458 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |
459 | { | |
3392cdd3 TKD |
460 | int i = 0; |
461 | struct omap_dm_timer *timer = NULL; | |
462 | unsigned long flags; | |
a569c6ec TL |
463 | |
464 | /* If ARMXOR cannot be idled this function call is unnecessary */ | |
465 | if (!(inputmask & (1 << 1))) | |
466 | return inputmask; | |
467 | ||
468 | /* If any active timer is using ARMXOR return modified mask */ | |
3392cdd3 TKD |
469 | spin_lock_irqsave(&dm_timer_lock, flags); |
470 | list_for_each_entry(timer, &omap_timer_list, node) { | |
77900a2f TT |
471 | u32 l; |
472 | ||
3392cdd3 | 473 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
474 | if (l & OMAP_TIMER_CTRL_ST) { |
475 | if (((omap_readl(MOD_CONF_CTRL_1) >> (i * 2)) & 0x03) == 0) | |
a569c6ec TL |
476 | inputmask &= ~(1 << 1); |
477 | else | |
478 | inputmask &= ~(1 << 2); | |
479 | } | |
3392cdd3 | 480 | i++; |
77900a2f | 481 | } |
3392cdd3 | 482 | spin_unlock_irqrestore(&dm_timer_lock, flags); |
a569c6ec TL |
483 | |
484 | return inputmask; | |
485 | } | |
486 | ||
140455fa | 487 | #else |
a569c6ec | 488 | |
592ea6bd | 489 | static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) |
92105bb7 | 490 | { |
86287958 | 491 | if (timer && !IS_ERR(timer->fclk)) |
ab4eb8b0 TKD |
492 | return timer->fclk; |
493 | return NULL; | |
77900a2f | 494 | } |
92105bb7 | 495 | |
77900a2f TT |
496 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
497 | { | |
498 | BUG(); | |
2121880e DB |
499 | |
500 | return 0; | |
92105bb7 TL |
501 | } |
502 | ||
77900a2f | 503 | #endif |
92105bb7 | 504 | |
ab4eb8b0 | 505 | int omap_dm_timer_trigger(struct omap_dm_timer *timer) |
92105bb7 | 506 | { |
ab4eb8b0 TKD |
507 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
508 | pr_err("%s: timer not available or enabled.\n", __func__); | |
509 | return -EINVAL; | |
b481113a TKD |
510 | } |
511 | ||
77900a2f | 512 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
ab4eb8b0 | 513 | return 0; |
92105bb7 TL |
514 | } |
515 | ||
592ea6bd | 516 | static int omap_dm_timer_start(struct omap_dm_timer *timer) |
77900a2f TT |
517 | { |
518 | u32 l; | |
92105bb7 | 519 | |
ab4eb8b0 TKD |
520 | if (unlikely(!timer)) |
521 | return -EINVAL; | |
522 | ||
b481113a TKD |
523 | omap_dm_timer_enable(timer); |
524 | ||
77900a2f TT |
525 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
526 | if (!(l & OMAP_TIMER_CTRL_ST)) { | |
527 | l |= OMAP_TIMER_CTRL_ST; | |
528 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | |
529 | } | |
b481113a TKD |
530 | |
531 | /* Save the context */ | |
532 | timer->context.tclr = l; | |
ab4eb8b0 | 533 | return 0; |
77900a2f | 534 | } |
92105bb7 | 535 | |
592ea6bd | 536 | static int omap_dm_timer_stop(struct omap_dm_timer *timer) |
92105bb7 | 537 | { |
caf64f2f | 538 | unsigned long rate = 0; |
92105bb7 | 539 | |
ab4eb8b0 TKD |
540 | if (unlikely(!timer)) |
541 | return -EINVAL; | |
542 | ||
6615975b | 543 | if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) |
3392cdd3 | 544 | rate = clk_get_rate(timer->fclk); |
caf64f2f | 545 | |
ee17f114 | 546 | __omap_dm_timer_stop(timer, timer->posted, rate); |
ab4eb8b0 | 547 | |
dffc9dae TKD |
548 | /* |
549 | * Since the register values are computed and written within | |
550 | * __omap_dm_timer_stop, we need to use read to retrieve the | |
551 | * context. | |
552 | */ | |
553 | timer->context.tclr = | |
554 | omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); | |
dffc9dae | 555 | omap_dm_timer_disable(timer); |
ab4eb8b0 | 556 | return 0; |
92105bb7 TL |
557 | } |
558 | ||
592ea6bd LM |
559 | static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, |
560 | unsigned int load) | |
92105bb7 TL |
561 | { |
562 | u32 l; | |
77900a2f | 563 | |
ab4eb8b0 TKD |
564 | if (unlikely(!timer)) |
565 | return -EINVAL; | |
566 | ||
b481113a | 567 | omap_dm_timer_enable(timer); |
92105bb7 | 568 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
569 | if (autoreload) |
570 | l |= OMAP_TIMER_CTRL_AR; | |
571 | else | |
572 | l &= ~OMAP_TIMER_CTRL_AR; | |
92105bb7 | 573 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
77900a2f | 574 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
0f0d0807 | 575 | |
77900a2f | 576 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
b481113a TKD |
577 | /* Save the context */ |
578 | timer->context.tclr = l; | |
579 | timer->context.tldr = load; | |
580 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 581 | return 0; |
92105bb7 TL |
582 | } |
583 | ||
3fddd09e | 584 | /* Optimized set_load which removes costly spin wait in timer_start */ |
ab4eb8b0 | 585 | int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
3fddd09e RW |
586 | unsigned int load) |
587 | { | |
588 | u32 l; | |
589 | ||
ab4eb8b0 TKD |
590 | if (unlikely(!timer)) |
591 | return -EINVAL; | |
592 | ||
b481113a TKD |
593 | omap_dm_timer_enable(timer); |
594 | ||
3fddd09e | 595 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
64ce2907 | 596 | if (autoreload) { |
3fddd09e | 597 | l |= OMAP_TIMER_CTRL_AR; |
64ce2907 PW |
598 | omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); |
599 | } else { | |
3fddd09e | 600 | l &= ~OMAP_TIMER_CTRL_AR; |
64ce2907 | 601 | } |
3fddd09e RW |
602 | l |= OMAP_TIMER_CTRL_ST; |
603 | ||
ee17f114 | 604 | __omap_dm_timer_load_start(timer, l, load, timer->posted); |
b481113a TKD |
605 | |
606 | /* Save the context */ | |
607 | timer->context.tclr = l; | |
608 | timer->context.tldr = load; | |
609 | timer->context.tcrr = load; | |
ab4eb8b0 | 610 | return 0; |
3fddd09e | 611 | } |
592ea6bd LM |
612 | static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
613 | unsigned int match) | |
92105bb7 TL |
614 | { |
615 | u32 l; | |
616 | ||
ab4eb8b0 TKD |
617 | if (unlikely(!timer)) |
618 | return -EINVAL; | |
619 | ||
b481113a | 620 | omap_dm_timer_enable(timer); |
92105bb7 | 621 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
83379c81 | 622 | if (enable) |
77900a2f TT |
623 | l |= OMAP_TIMER_CTRL_CE; |
624 | else | |
625 | l &= ~OMAP_TIMER_CTRL_CE; | |
77900a2f | 626 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
991ad16a | 627 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
628 | |
629 | /* Save the context */ | |
630 | timer->context.tclr = l; | |
631 | timer->context.tmar = match; | |
632 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 633 | return 0; |
92105bb7 TL |
634 | } |
635 | ||
592ea6bd LM |
636 | static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
637 | int toggle, int trigger) | |
92105bb7 TL |
638 | { |
639 | u32 l; | |
640 | ||
ab4eb8b0 TKD |
641 | if (unlikely(!timer)) |
642 | return -EINVAL; | |
643 | ||
b481113a | 644 | omap_dm_timer_enable(timer); |
92105bb7 | 645 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f TT |
646 | l &= ~(OMAP_TIMER_CTRL_GPOCFG | OMAP_TIMER_CTRL_SCPWM | |
647 | OMAP_TIMER_CTRL_PT | (0x03 << 10)); | |
648 | if (def_on) | |
649 | l |= OMAP_TIMER_CTRL_SCPWM; | |
650 | if (toggle) | |
651 | l |= OMAP_TIMER_CTRL_PT; | |
652 | l |= trigger << 10; | |
92105bb7 | 653 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
654 | |
655 | /* Save the context */ | |
656 | timer->context.tclr = l; | |
657 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 658 | return 0; |
92105bb7 TL |
659 | } |
660 | ||
592ea6bd LM |
661 | static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, |
662 | int prescaler) | |
92105bb7 TL |
663 | { |
664 | u32 l; | |
665 | ||
58a54f03 | 666 | if (unlikely(!timer) || prescaler < -1 || prescaler > 7) |
ab4eb8b0 TKD |
667 | return -EINVAL; |
668 | ||
b481113a | 669 | omap_dm_timer_enable(timer); |
92105bb7 | 670 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); |
77900a2f | 671 | l &= ~(OMAP_TIMER_CTRL_PRE | (0x07 << 2)); |
58a54f03 | 672 | if (prescaler >= 0) { |
77900a2f TT |
673 | l |= OMAP_TIMER_CTRL_PRE; |
674 | l |= prescaler << 2; | |
675 | } | |
92105bb7 | 676 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
b481113a TKD |
677 | |
678 | /* Save the context */ | |
679 | timer->context.tclr = l; | |
680 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 681 | return 0; |
92105bb7 TL |
682 | } |
683 | ||
592ea6bd LM |
684 | static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
685 | unsigned int value) | |
92105bb7 | 686 | { |
ab4eb8b0 TKD |
687 | if (unlikely(!timer)) |
688 | return -EINVAL; | |
689 | ||
b481113a | 690 | omap_dm_timer_enable(timer); |
ee17f114 | 691 | __omap_dm_timer_int_enable(timer, value); |
b481113a TKD |
692 | |
693 | /* Save the context */ | |
694 | timer->context.tier = value; | |
695 | timer->context.twer = value; | |
696 | omap_dm_timer_disable(timer); | |
ab4eb8b0 | 697 | return 0; |
92105bb7 TL |
698 | } |
699 | ||
4249d96c JH |
700 | /** |
701 | * omap_dm_timer_set_int_disable - disable timer interrupts | |
702 | * @timer: pointer to timer handle | |
703 | * @mask: bit mask of interrupts to be disabled | |
704 | * | |
705 | * Disables the specified timer interrupts for a timer. | |
706 | */ | |
592ea6bd | 707 | static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask) |
4249d96c JH |
708 | { |
709 | u32 l = mask; | |
710 | ||
711 | if (unlikely(!timer)) | |
712 | return -EINVAL; | |
713 | ||
714 | omap_dm_timer_enable(timer); | |
715 | ||
716 | if (timer->revision == 1) | |
834cacfb | 717 | l = readl_relaxed(timer->irq_ena) & ~mask; |
4249d96c | 718 | |
834cacfb | 719 | writel_relaxed(l, timer->irq_dis); |
4249d96c JH |
720 | l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask; |
721 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l); | |
722 | ||
723 | /* Save the context */ | |
724 | timer->context.tier &= ~mask; | |
725 | timer->context.twer &= ~mask; | |
726 | omap_dm_timer_disable(timer); | |
727 | return 0; | |
728 | } | |
4249d96c | 729 | |
592ea6bd | 730 | static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
92105bb7 | 731 | { |
fa4bb626 TT |
732 | unsigned int l; |
733 | ||
ab4eb8b0 TKD |
734 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
735 | pr_err("%s: timer not available or enabled.\n", __func__); | |
b481113a TKD |
736 | return 0; |
737 | } | |
738 | ||
834cacfb | 739 | l = readl_relaxed(timer->irq_stat); |
fa4bb626 TT |
740 | |
741 | return l; | |
92105bb7 TL |
742 | } |
743 | ||
592ea6bd | 744 | static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
92105bb7 | 745 | { |
ab4eb8b0 TKD |
746 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) |
747 | return -EINVAL; | |
748 | ||
ee17f114 | 749 | __omap_dm_timer_write_status(timer, value); |
1eaff710 | 750 | |
ab4eb8b0 | 751 | return 0; |
92105bb7 TL |
752 | } |
753 | ||
592ea6bd | 754 | static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
92105bb7 | 755 | { |
ab4eb8b0 TKD |
756 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
757 | pr_err("%s: timer not iavailable or enabled.\n", __func__); | |
b481113a TKD |
758 | return 0; |
759 | } | |
760 | ||
ee17f114 | 761 | return __omap_dm_timer_read_counter(timer, timer->posted); |
92105bb7 TL |
762 | } |
763 | ||
592ea6bd | 764 | static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
83379c81 | 765 | { |
ab4eb8b0 TKD |
766 | if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) { |
767 | pr_err("%s: timer not available or enabled.\n", __func__); | |
768 | return -EINVAL; | |
b481113a TKD |
769 | } |
770 | ||
fa4bb626 | 771 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
b481113a TKD |
772 | |
773 | /* Save the context */ | |
774 | timer->context.tcrr = value; | |
ab4eb8b0 | 775 | return 0; |
83379c81 TT |
776 | } |
777 | ||
77900a2f | 778 | int omap_dm_timers_active(void) |
92105bb7 | 779 | { |
3392cdd3 | 780 | struct omap_dm_timer *timer; |
12583a70 | 781 | |
3392cdd3 | 782 | list_for_each_entry(timer, &omap_timer_list, node) { |
ffe07cea | 783 | if (!timer->reserved) |
12583a70 TT |
784 | continue; |
785 | ||
77900a2f | 786 | if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & |
fa4bb626 | 787 | OMAP_TIMER_CTRL_ST) { |
77900a2f | 788 | return 1; |
fa4bb626 | 789 | } |
77900a2f TT |
790 | } |
791 | return 0; | |
792 | } | |
92105bb7 | 793 | |
d1c6ccfe JH |
794 | static const struct of_device_id omap_timer_match[]; |
795 | ||
df28472a TKD |
796 | /** |
797 | * omap_dm_timer_probe - probe function called for every registered device | |
798 | * @pdev: pointer to current timer platform device | |
799 | * | |
800 | * Called by driver framework at the end of device registration for all | |
801 | * timer devices. | |
802 | */ | |
351a102d | 803 | static int omap_dm_timer_probe(struct platform_device *pdev) |
df28472a | 804 | { |
df28472a TKD |
805 | unsigned long flags; |
806 | struct omap_dm_timer *timer; | |
74dd9ec6 TKD |
807 | struct resource *mem, *irq; |
808 | struct device *dev = &pdev->dev; | |
d1c6ccfe | 809 | const struct dmtimer_platform_data *pdata; |
a76fc9dd | 810 | int ret; |
d1c6ccfe | 811 | |
1a3acad2 LM |
812 | pdata = of_device_get_match_data(dev); |
813 | if (!pdata) | |
814 | pdata = dev_get_platdata(dev); | |
815 | else | |
816 | dev->platform_data = (void *)pdata; | |
df28472a | 817 | |
1a3acad2 | 818 | if (!pdata) { |
74dd9ec6 | 819 | dev_err(dev, "%s: no platform data.\n", __func__); |
df28472a TKD |
820 | return -ENODEV; |
821 | } | |
822 | ||
823 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
824 | if (unlikely(!irq)) { | |
74dd9ec6 | 825 | dev_err(dev, "%s: no IRQ resource.\n", __func__); |
df28472a TKD |
826 | return -ENODEV; |
827 | } | |
828 | ||
829 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
830 | if (unlikely(!mem)) { | |
74dd9ec6 | 831 | dev_err(dev, "%s: no memory resource.\n", __func__); |
df28472a TKD |
832 | return -ENODEV; |
833 | } | |
834 | ||
16e7ea53 | 835 | timer = devm_kzalloc(dev, sizeof(*timer), GFP_KERNEL); |
d679950c | 836 | if (!timer) |
74dd9ec6 | 837 | return -ENOMEM; |
df28472a | 838 | |
86287958 | 839 | timer->fclk = ERR_PTR(-ENODEV); |
5857bd98 TR |
840 | timer->io_base = devm_ioremap_resource(dev, mem); |
841 | if (IS_ERR(timer->io_base)) | |
842 | return PTR_ERR(timer->io_base); | |
df28472a | 843 | |
9725f445 JH |
844 | if (dev->of_node) { |
845 | if (of_find_property(dev->of_node, "ti,timer-alwon", NULL)) | |
846 | timer->capability |= OMAP_TIMER_ALWON; | |
847 | if (of_find_property(dev->of_node, "ti,timer-dsp", NULL)) | |
848 | timer->capability |= OMAP_TIMER_HAS_DSP_IRQ; | |
849 | if (of_find_property(dev->of_node, "ti,timer-pwm", NULL)) | |
850 | timer->capability |= OMAP_TIMER_HAS_PWM; | |
851 | if (of_find_property(dev->of_node, "ti,timer-secure", NULL)) | |
852 | timer->capability |= OMAP_TIMER_SECURE; | |
853 | } else { | |
854 | timer->id = pdev->id; | |
855 | timer->capability = pdata->timer_capability; | |
856 | timer->reserved = omap_dm_timer_reserved_systimer(timer->id); | |
f56f52e0 | 857 | timer->get_context_loss_count = pdata->get_context_loss_count; |
9725f445 JH |
858 | } |
859 | ||
d1c6ccfe JH |
860 | if (pdata) |
861 | timer->errata = pdata->timer_errata; | |
862 | ||
df28472a TKD |
863 | timer->irq = irq->start; |
864 | timer->pdev = pdev; | |
df28472a | 865 | |
ba688783 TL |
866 | pm_runtime_enable(dev); |
867 | pm_runtime_irq_safe(dev); | |
ffe07cea | 868 | |
0dad9fae | 869 | if (!timer->reserved) { |
a76fc9dd SA |
870 | ret = pm_runtime_get_sync(dev); |
871 | if (ret < 0) { | |
872 | dev_err(dev, "%s: pm_runtime_get_sync failed!\n", | |
873 | __func__); | |
874 | goto err_get_sync; | |
875 | } | |
0dad9fae | 876 | __omap_dm_timer_init_regs(timer); |
74dd9ec6 | 877 | pm_runtime_put(dev); |
0dad9fae TL |
878 | } |
879 | ||
df28472a TKD |
880 | /* add the timer element to the list */ |
881 | spin_lock_irqsave(&dm_timer_lock, flags); | |
882 | list_add_tail(&timer->node, &omap_timer_list); | |
883 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
884 | ||
74dd9ec6 | 885 | dev_dbg(dev, "Device Probed.\n"); |
df28472a TKD |
886 | |
887 | return 0; | |
a76fc9dd SA |
888 | |
889 | err_get_sync: | |
890 | pm_runtime_put_noidle(dev); | |
891 | pm_runtime_disable(dev); | |
892 | return ret; | |
df28472a TKD |
893 | } |
894 | ||
895 | /** | |
896 | * omap_dm_timer_remove - cleanup a registered timer device | |
897 | * @pdev: pointer to current timer platform device | |
898 | * | |
899 | * Called by driver framework whenever a timer device is unregistered. | |
900 | * In addition to freeing platform resources it also deletes the timer | |
901 | * entry from the local list. | |
902 | */ | |
351a102d | 903 | static int omap_dm_timer_remove(struct platform_device *pdev) |
df28472a TKD |
904 | { |
905 | struct omap_dm_timer *timer; | |
906 | unsigned long flags; | |
907 | int ret = -EINVAL; | |
908 | ||
909 | spin_lock_irqsave(&dm_timer_lock, flags); | |
910 | list_for_each_entry(timer, &omap_timer_list, node) | |
9725f445 JH |
911 | if (!strcmp(dev_name(&timer->pdev->dev), |
912 | dev_name(&pdev->dev))) { | |
df28472a | 913 | list_del(&timer->node); |
df28472a TKD |
914 | ret = 0; |
915 | break; | |
916 | } | |
917 | spin_unlock_irqrestore(&dm_timer_lock, flags); | |
918 | ||
51b7e572 SA |
919 | pm_runtime_disable(&pdev->dev); |
920 | ||
df28472a TKD |
921 | return ret; |
922 | } | |
923 | ||
76234f7c K |
924 | const static struct omap_dm_timer_ops dmtimer_ops = { |
925 | .request_by_node = omap_dm_timer_request_by_node, | |
926 | .request_specific = omap_dm_timer_request_specific, | |
927 | .request = omap_dm_timer_request, | |
928 | .set_source = omap_dm_timer_set_source, | |
929 | .get_irq = omap_dm_timer_get_irq, | |
930 | .set_int_enable = omap_dm_timer_set_int_enable, | |
931 | .set_int_disable = omap_dm_timer_set_int_disable, | |
932 | .free = omap_dm_timer_free, | |
933 | .enable = omap_dm_timer_enable, | |
934 | .disable = omap_dm_timer_disable, | |
935 | .get_fclk = omap_dm_timer_get_fclk, | |
936 | .start = omap_dm_timer_start, | |
937 | .stop = omap_dm_timer_stop, | |
938 | .set_load = omap_dm_timer_set_load, | |
939 | .set_match = omap_dm_timer_set_match, | |
940 | .set_pwm = omap_dm_timer_set_pwm, | |
941 | .set_prescaler = omap_dm_timer_set_prescaler, | |
942 | .read_counter = omap_dm_timer_read_counter, | |
943 | .write_counter = omap_dm_timer_write_counter, | |
944 | .read_status = omap_dm_timer_read_status, | |
945 | .write_status = omap_dm_timer_write_status, | |
946 | }; | |
947 | ||
d1c6ccfe JH |
948 | static const struct dmtimer_platform_data omap3plus_pdata = { |
949 | .timer_errata = OMAP_TIMER_ERRATA_I103_I767, | |
76234f7c | 950 | .timer_ops = &dmtimer_ops, |
d1c6ccfe JH |
951 | }; |
952 | ||
9725f445 | 953 | static const struct of_device_id omap_timer_match[] = { |
d1c6ccfe JH |
954 | { |
955 | .compatible = "ti,omap2420-timer", | |
956 | }, | |
957 | { | |
958 | .compatible = "ti,omap3430-timer", | |
959 | .data = &omap3plus_pdata, | |
960 | }, | |
961 | { | |
962 | .compatible = "ti,omap4430-timer", | |
963 | .data = &omap3plus_pdata, | |
964 | }, | |
965 | { | |
966 | .compatible = "ti,omap5430-timer", | |
967 | .data = &omap3plus_pdata, | |
968 | }, | |
969 | { | |
970 | .compatible = "ti,am335x-timer", | |
971 | .data = &omap3plus_pdata, | |
972 | }, | |
973 | { | |
974 | .compatible = "ti,am335x-timer-1ms", | |
975 | .data = &omap3plus_pdata, | |
976 | }, | |
8c0cabd7 NA |
977 | { |
978 | .compatible = "ti,dm816-timer", | |
979 | .data = &omap3plus_pdata, | |
980 | }, | |
9725f445 JH |
981 | {}, |
982 | }; | |
983 | MODULE_DEVICE_TABLE(of, omap_timer_match); | |
984 | ||
df28472a TKD |
985 | static struct platform_driver omap_dm_timer_driver = { |
986 | .probe = omap_dm_timer_probe, | |
351a102d | 987 | .remove = omap_dm_timer_remove, |
df28472a TKD |
988 | .driver = { |
989 | .name = "omap_timer", | |
9725f445 | 990 | .of_match_table = of_match_ptr(omap_timer_match), |
df28472a TKD |
991 | }, |
992 | }; | |
993 | ||
df28472a | 994 | early_platform_init("earlytimer", &omap_dm_timer_driver); |
e4e9f7ea | 995 | module_platform_driver(omap_dm_timer_driver); |
df28472a TKD |
996 | |
997 | MODULE_DESCRIPTION("OMAP Dual-Mode Timer Driver"); | |
998 | MODULE_LICENSE("GPL"); | |
999 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
1000 | MODULE_AUTHOR("Texas Instruments Inc"); |