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Commit | Line | Data |
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1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1da177e4 LT |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
fe27cb35 VP |
31 | #include <linux/smp.h> |
32 | #include <linux/sched.h> | |
1da177e4 | 33 | #include <linux/cpufreq.h> |
d395bf12 | 34 | #include <linux/compiler.h> |
8adcc0c6 | 35 | #include <linux/dmi.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
1da177e4 LT |
37 | |
38 | #include <linux/acpi.h> | |
3a58df35 DJ |
39 | #include <linux/io.h> |
40 | #include <linux/delay.h> | |
41 | #include <linux/uaccess.h> | |
42 | ||
1da177e4 LT |
43 | #include <acpi/processor.h> |
44 | ||
dde9f7ba | 45 | #include <asm/msr.h> |
fe27cb35 VP |
46 | #include <asm/processor.h> |
47 | #include <asm/cpufeature.h> | |
fe27cb35 | 48 | |
1da177e4 LT |
49 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
50 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
51 | MODULE_LICENSE("GPL"); | |
52 | ||
acd31624 AP |
53 | #define PFX "acpi-cpufreq: " |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | struct acpi_processor_performance *acpi_data; |
69 | struct cpufreq_frequency_table *freq_table; | |
70 | unsigned int resume; | |
71 | unsigned int cpu_feature; | |
8cfcfd39 | 72 | unsigned int acpi_perf_cpu; |
f4fd3797 | 73 | cpumask_var_t freqdomain_cpus; |
1da177e4 LT |
74 | }; |
75 | ||
50109292 | 76 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 77 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 LT |
78 | |
79 | static struct cpufreq_driver acpi_cpufreq_driver; | |
80 | ||
d395bf12 | 81 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
82 | static struct msr __percpu *msrs; |
83 | ||
84 | static bool boost_state(unsigned int cpu) | |
85 | { | |
86 | u32 lo, hi; | |
87 | u64 msr; | |
88 | ||
89 | switch (boot_cpu_data.x86_vendor) { | |
90 | case X86_VENDOR_INTEL: | |
91 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
92 | msr = lo | ((u64)hi << 32); | |
93 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
94 | case X86_VENDOR_AMD: | |
95 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
96 | msr = lo | ((u64)hi << 32); | |
97 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
98 | } | |
99 | return false; | |
100 | } | |
101 | ||
102 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
103 | { | |
104 | u32 cpu; | |
105 | u32 msr_addr; | |
106 | u64 msr_mask; | |
107 | ||
108 | switch (boot_cpu_data.x86_vendor) { | |
109 | case X86_VENDOR_INTEL: | |
110 | msr_addr = MSR_IA32_MISC_ENABLE; | |
111 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
112 | break; | |
113 | case X86_VENDOR_AMD: | |
114 | msr_addr = MSR_K7_HWCR; | |
115 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
116 | break; | |
117 | default: | |
118 | return; | |
119 | } | |
120 | ||
121 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
122 | ||
123 | for_each_cpu(cpu, cpumask) { | |
124 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
125 | if (enable) | |
126 | reg->q &= ~msr_mask; | |
127 | else | |
128 | reg->q |= msr_mask; | |
129 | } | |
130 | ||
131 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
132 | } | |
133 | ||
cfc9c8ed | 134 | static int _store_boost(int val) |
615b7300 | 135 | { |
615b7300 | 136 | get_online_cpus(); |
615b7300 | 137 | boost_set_msrs(val, cpu_online_mask); |
615b7300 | 138 | put_online_cpus(); |
615b7300 AP |
139 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
140 | ||
cfc9c8ed | 141 | return 0; |
615b7300 AP |
142 | } |
143 | ||
f4fd3797 LT |
144 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
145 | { | |
eb0b3e78 | 146 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 LT |
147 | |
148 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); | |
149 | } | |
150 | ||
151 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
152 | ||
11269ff5 | 153 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
cfc9c8ed LM |
154 | static ssize_t store_boost(const char *buf, size_t count) |
155 | { | |
156 | int ret; | |
157 | unsigned long val = 0; | |
158 | ||
159 | if (!acpi_cpufreq_driver.boost_supported) | |
160 | return -EINVAL; | |
161 | ||
162 | ret = kstrtoul(buf, 10, &val); | |
163 | if (ret || (val > 1)) | |
164 | return -EINVAL; | |
165 | ||
166 | _store_boost((int) val); | |
167 | ||
168 | return count; | |
169 | } | |
170 | ||
11269ff5 AP |
171 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
172 | size_t count) | |
173 | { | |
cfc9c8ed | 174 | return store_boost(buf, count); |
11269ff5 AP |
175 | } |
176 | ||
177 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) | |
178 | { | |
cfc9c8ed | 179 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
180 | } |
181 | ||
59027d35 | 182 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
183 | #endif |
184 | ||
dde9f7ba VP |
185 | static int check_est_cpu(unsigned int cpuid) |
186 | { | |
92cb7612 | 187 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 188 | |
0de51088 | 189 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
190 | } |
191 | ||
3dc9a633 MG |
192 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
193 | { | |
194 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
195 | ||
196 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
197 | } | |
198 | ||
dde9f7ba | 199 | static unsigned extract_io(u32 value, struct acpi_cpufreq_data *data) |
fe27cb35 | 200 | { |
64be7eed VP |
201 | struct acpi_processor_performance *perf; |
202 | int i; | |
fe27cb35 VP |
203 | |
204 | perf = data->acpi_data; | |
205 | ||
3a58df35 | 206 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 VP |
207 | if (value == perf->states[i].status) |
208 | return data->freq_table[i].frequency; | |
209 | } | |
210 | return 0; | |
211 | } | |
212 | ||
dde9f7ba VP |
213 | static unsigned extract_msr(u32 msr, struct acpi_cpufreq_data *data) |
214 | { | |
041526f9 | 215 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 216 | struct acpi_processor_performance *perf; |
dde9f7ba | 217 | |
3dc9a633 MG |
218 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
219 | msr &= AMD_MSR_RANGE; | |
220 | else | |
221 | msr &= INTEL_MSR_RANGE; | |
222 | ||
a6f6e6e6 VP |
223 | perf = data->acpi_data; |
224 | ||
041526f9 SK |
225 | cpufreq_for_each_entry(pos, data->freq_table) |
226 | if (msr == perf->states[pos->driver_data].status) | |
227 | return pos->frequency; | |
dde9f7ba VP |
228 | return data->freq_table[0].frequency; |
229 | } | |
230 | ||
dde9f7ba VP |
231 | static unsigned extract_freq(u32 val, struct acpi_cpufreq_data *data) |
232 | { | |
233 | switch (data->cpu_feature) { | |
64be7eed | 234 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 235 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba | 236 | return extract_msr(val, data); |
64be7eed | 237 | case SYSTEM_IO_CAPABLE: |
dde9f7ba | 238 | return extract_io(val, data); |
64be7eed | 239 | default: |
dde9f7ba VP |
240 | return 0; |
241 | } | |
242 | } | |
243 | ||
dde9f7ba VP |
244 | struct msr_addr { |
245 | u32 reg; | |
246 | }; | |
247 | ||
fe27cb35 VP |
248 | struct io_addr { |
249 | u16 port; | |
250 | u8 bit_width; | |
251 | }; | |
252 | ||
253 | struct drv_cmd { | |
dde9f7ba | 254 | unsigned int type; |
bfa318ad | 255 | const struct cpumask *mask; |
3a58df35 DJ |
256 | union { |
257 | struct msr_addr msr; | |
258 | struct io_addr io; | |
259 | } addr; | |
fe27cb35 VP |
260 | u32 val; |
261 | }; | |
262 | ||
01599fca AM |
263 | /* Called via smp_call_function_single(), on the target CPU */ |
264 | static void do_drv_read(void *_cmd) | |
1da177e4 | 265 | { |
72859081 | 266 | struct drv_cmd *cmd = _cmd; |
dde9f7ba VP |
267 | u32 h; |
268 | ||
269 | switch (cmd->type) { | |
64be7eed | 270 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 271 | case SYSTEM_AMD_MSR_CAPABLE: |
dde9f7ba VP |
272 | rdmsr(cmd->addr.msr.reg, cmd->val, h); |
273 | break; | |
64be7eed | 274 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
275 | acpi_os_read_port((acpi_io_address)cmd->addr.io.port, |
276 | &cmd->val, | |
277 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 278 | break; |
64be7eed | 279 | default: |
dde9f7ba VP |
280 | break; |
281 | } | |
fe27cb35 | 282 | } |
1da177e4 | 283 | |
01599fca AM |
284 | /* Called via smp_call_function_many(), on the target CPUs */ |
285 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 286 | { |
72859081 | 287 | struct drv_cmd *cmd = _cmd; |
13424f65 | 288 | u32 lo, hi; |
dde9f7ba VP |
289 | |
290 | switch (cmd->type) { | |
64be7eed | 291 | case SYSTEM_INTEL_MSR_CAPABLE: |
13424f65 VP |
292 | rdmsr(cmd->addr.msr.reg, lo, hi); |
293 | lo = (lo & ~INTEL_MSR_RANGE) | (cmd->val & INTEL_MSR_RANGE); | |
294 | wrmsr(cmd->addr.msr.reg, lo, hi); | |
dde9f7ba | 295 | break; |
3dc9a633 MG |
296 | case SYSTEM_AMD_MSR_CAPABLE: |
297 | wrmsr(cmd->addr.msr.reg, cmd->val, 0); | |
298 | break; | |
64be7eed | 299 | case SYSTEM_IO_CAPABLE: |
4e581ff1 VP |
300 | acpi_os_write_port((acpi_io_address)cmd->addr.io.port, |
301 | cmd->val, | |
302 | (u32)cmd->addr.io.bit_width); | |
dde9f7ba | 303 | break; |
64be7eed | 304 | default: |
dde9f7ba VP |
305 | break; |
306 | } | |
fe27cb35 | 307 | } |
1da177e4 | 308 | |
95dd7227 | 309 | static void drv_read(struct drv_cmd *cmd) |
fe27cb35 | 310 | { |
4a28395d | 311 | int err; |
fe27cb35 VP |
312 | cmd->val = 0; |
313 | ||
4a28395d AM |
314 | err = smp_call_function_any(cmd->mask, do_drv_read, cmd, 1); |
315 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
fe27cb35 VP |
316 | } |
317 | ||
318 | static void drv_write(struct drv_cmd *cmd) | |
319 | { | |
ea34f43a LT |
320 | int this_cpu; |
321 | ||
322 | this_cpu = get_cpu(); | |
323 | if (cpumask_test_cpu(this_cpu, cmd->mask)) | |
324 | do_drv_write(cmd); | |
01599fca | 325 | smp_call_function_many(cmd->mask, do_drv_write, cmd, 1); |
ea34f43a | 326 | put_cpu(); |
fe27cb35 | 327 | } |
1da177e4 | 328 | |
eb0b3e78 PX |
329 | static u32 |
330 | get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) | |
fe27cb35 | 331 | { |
64be7eed VP |
332 | struct acpi_processor_performance *perf; |
333 | struct drv_cmd cmd; | |
1da177e4 | 334 | |
4d8bb537 | 335 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 336 | return 0; |
1da177e4 | 337 | |
eb0b3e78 | 338 | switch (data->cpu_feature) { |
dde9f7ba VP |
339 | case SYSTEM_INTEL_MSR_CAPABLE: |
340 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
8673b83b | 341 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; |
dde9f7ba | 342 | break; |
3dc9a633 MG |
343 | case SYSTEM_AMD_MSR_CAPABLE: |
344 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
8673b83b | 345 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; |
3dc9a633 | 346 | break; |
dde9f7ba VP |
347 | case SYSTEM_IO_CAPABLE: |
348 | cmd.type = SYSTEM_IO_CAPABLE; | |
eb0b3e78 | 349 | perf = data->acpi_data; |
dde9f7ba VP |
350 | cmd.addr.io.port = perf->control_register.address; |
351 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
352 | break; | |
353 | default: | |
354 | return 0; | |
355 | } | |
356 | ||
bfa318ad | 357 | cmd.mask = mask; |
fe27cb35 | 358 | drv_read(&cmd); |
1da177e4 | 359 | |
2d06d8c4 | 360 | pr_debug("get_cur_val = %u\n", cmd.val); |
fe27cb35 VP |
361 | |
362 | return cmd.val; | |
363 | } | |
1da177e4 | 364 | |
fe27cb35 VP |
365 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
366 | { | |
eb0b3e78 PX |
367 | struct acpi_cpufreq_data *data; |
368 | struct cpufreq_policy *policy; | |
64be7eed | 369 | unsigned int freq; |
e56a727b | 370 | unsigned int cached_freq; |
fe27cb35 | 371 | |
2d06d8c4 | 372 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 373 | |
eb0b3e78 PX |
374 | policy = cpufreq_cpu_get(cpu); |
375 | if (unlikely(!policy)) | |
376 | return 0; | |
377 | ||
378 | data = policy->driver_data; | |
379 | cpufreq_cpu_put(policy); | |
380 | if (unlikely(!data || !data->acpi_data || !data->freq_table)) | |
fe27cb35 | 381 | return 0; |
1da177e4 | 382 | |
e56a727b | 383 | cached_freq = data->freq_table[data->acpi_data->state].frequency; |
eb0b3e78 | 384 | freq = extract_freq(get_cur_val(cpumask_of(cpu), data), data); |
e56a727b VP |
385 | if (freq != cached_freq) { |
386 | /* | |
387 | * The dreaded BIOS frequency change behind our back. | |
388 | * Force set the frequency on next target call. | |
389 | */ | |
390 | data->resume = 1; | |
391 | } | |
392 | ||
2d06d8c4 | 393 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 394 | |
fe27cb35 | 395 | return freq; |
1da177e4 LT |
396 | } |
397 | ||
72859081 | 398 | static unsigned int check_freqs(const struct cpumask *mask, unsigned int freq, |
64be7eed | 399 | struct acpi_cpufreq_data *data) |
fe27cb35 | 400 | { |
64be7eed VP |
401 | unsigned int cur_freq; |
402 | unsigned int i; | |
1da177e4 | 403 | |
3a58df35 | 404 | for (i = 0; i < 100; i++) { |
eb0b3e78 | 405 | cur_freq = extract_freq(get_cur_val(mask, data), data); |
fe27cb35 VP |
406 | if (cur_freq == freq) |
407 | return 1; | |
408 | udelay(10); | |
409 | } | |
410 | return 0; | |
411 | } | |
412 | ||
413 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 414 | unsigned int index) |
1da177e4 | 415 | { |
eb0b3e78 | 416 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 417 | struct acpi_processor_performance *perf; |
64be7eed | 418 | struct drv_cmd cmd; |
8edc59d9 | 419 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 420 | int result = 0; |
fe27cb35 | 421 | |
fe27cb35 | 422 | if (unlikely(data == NULL || |
95dd7227 | 423 | data->acpi_data == NULL || data->freq_table == NULL)) { |
fe27cb35 VP |
424 | return -ENODEV; |
425 | } | |
1da177e4 | 426 | |
fe27cb35 | 427 | perf = data->acpi_data; |
9c0ebcf7 | 428 | next_perf_state = data->freq_table[index].driver_data; |
7650b281 | 429 | if (perf->state == next_perf_state) { |
fe27cb35 | 430 | if (unlikely(data->resume)) { |
2d06d8c4 | 431 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 432 | next_perf_state); |
fe27cb35 VP |
433 | data->resume = 0; |
434 | } else { | |
2d06d8c4 | 435 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 436 | next_perf_state); |
4d8bb537 | 437 | goto out; |
fe27cb35 | 438 | } |
09b4d1ee VP |
439 | } |
440 | ||
64be7eed VP |
441 | switch (data->cpu_feature) { |
442 | case SYSTEM_INTEL_MSR_CAPABLE: | |
443 | cmd.type = SYSTEM_INTEL_MSR_CAPABLE; | |
444 | cmd.addr.msr.reg = MSR_IA32_PERF_CTL; | |
13424f65 | 445 | cmd.val = (u32) perf->states[next_perf_state].control; |
64be7eed | 446 | break; |
3dc9a633 MG |
447 | case SYSTEM_AMD_MSR_CAPABLE: |
448 | cmd.type = SYSTEM_AMD_MSR_CAPABLE; | |
449 | cmd.addr.msr.reg = MSR_AMD_PERF_CTL; | |
450 | cmd.val = (u32) perf->states[next_perf_state].control; | |
451 | break; | |
64be7eed VP |
452 | case SYSTEM_IO_CAPABLE: |
453 | cmd.type = SYSTEM_IO_CAPABLE; | |
454 | cmd.addr.io.port = perf->control_register.address; | |
455 | cmd.addr.io.bit_width = perf->control_register.bit_width; | |
456 | cmd.val = (u32) perf->states[next_perf_state].control; | |
457 | break; | |
458 | default: | |
4d8bb537 MT |
459 | result = -ENODEV; |
460 | goto out; | |
64be7eed | 461 | } |
09b4d1ee | 462 | |
4d8bb537 | 463 | /* cpufreq holds the hotplug lock, so we are safe from here on */ |
fe27cb35 | 464 | if (policy->shared_type != CPUFREQ_SHARED_TYPE_ANY) |
bfa318ad | 465 | cmd.mask = policy->cpus; |
fe27cb35 | 466 | else |
bfa318ad | 467 | cmd.mask = cpumask_of(policy->cpu); |
09b4d1ee | 468 | |
fe27cb35 | 469 | drv_write(&cmd); |
09b4d1ee | 470 | |
fe27cb35 | 471 | if (acpi_pstate_strict) { |
d4019f0a VK |
472 | if (!check_freqs(cmd.mask, data->freq_table[index].frequency, |
473 | data)) { | |
2d06d8c4 | 474 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 475 | policy->cpu); |
4d8bb537 | 476 | result = -EAGAIN; |
09b4d1ee VP |
477 | } |
478 | } | |
479 | ||
e15d8309 VK |
480 | if (!result) |
481 | perf->state = next_perf_state; | |
fe27cb35 | 482 | |
4d8bb537 | 483 | out: |
fe27cb35 | 484 | return result; |
1da177e4 LT |
485 | } |
486 | ||
1da177e4 | 487 | static unsigned long |
64be7eed | 488 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 489 | { |
64be7eed | 490 | struct acpi_processor_performance *perf = data->acpi_data; |
09b4d1ee | 491 | |
1da177e4 LT |
492 | if (cpu_khz) { |
493 | /* search the closest match to cpu_khz */ | |
494 | unsigned int i; | |
495 | unsigned long freq; | |
09b4d1ee | 496 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 497 | |
3a58df35 | 498 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 499 | freq = freqn; |
95dd7227 | 500 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 501 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 502 | perf->state = i; |
64be7eed | 503 | return freq; |
1da177e4 LT |
504 | } |
505 | } | |
95dd7227 | 506 | perf->state = perf->state_count-1; |
64be7eed | 507 | return freqn; |
09b4d1ee | 508 | } else { |
1da177e4 | 509 | /* assume CPU is at P0... */ |
09b4d1ee VP |
510 | perf->state = 0; |
511 | return perf->states[0].core_frequency * 1000; | |
512 | } | |
1da177e4 LT |
513 | } |
514 | ||
2fdf66b4 RR |
515 | static void free_acpi_perf_data(void) |
516 | { | |
517 | unsigned int i; | |
518 | ||
519 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
520 | for_each_possible_cpu(i) | |
521 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
522 | ->shared_cpu_map); | |
523 | free_percpu(acpi_perf_data); | |
524 | } | |
525 | ||
615b7300 AP |
526 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
527 | void *hcpu) | |
528 | { | |
529 | unsigned cpu = (long)hcpu; | |
530 | const struct cpumask *cpumask; | |
531 | ||
532 | cpumask = get_cpu_mask(cpu); | |
533 | ||
534 | /* | |
535 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
536 | * this cpu cannot block the remaining ones from boosting. On | |
537 | * the CPU_UP path we simply keep the boost-disable flag in | |
538 | * sync with the current global state. | |
539 | */ | |
540 | ||
541 | switch (action) { | |
542 | case CPU_UP_PREPARE: | |
543 | case CPU_UP_PREPARE_FROZEN: | |
cfc9c8ed | 544 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); |
615b7300 AP |
545 | break; |
546 | ||
547 | case CPU_DOWN_PREPARE: | |
548 | case CPU_DOWN_PREPARE_FROZEN: | |
549 | boost_set_msrs(1, cpumask); | |
550 | break; | |
551 | ||
552 | default: | |
553 | break; | |
554 | } | |
555 | ||
556 | return NOTIFY_OK; | |
557 | } | |
558 | ||
559 | ||
560 | static struct notifier_block boost_nb = { | |
561 | .notifier_call = boost_notify, | |
562 | }; | |
563 | ||
09b4d1ee VP |
564 | /* |
565 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
566 | * | |
567 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
568 | * in order to determine correct frequency and voltage pairings. We can | |
569 | * do _PDC and _PSD and find out the processor dependency for the | |
570 | * actual init that will happen later... | |
571 | */ | |
50109292 | 572 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 573 | { |
2fdf66b4 | 574 | unsigned int i; |
2d06d8c4 | 575 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 576 | |
50109292 FY |
577 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
578 | if (!acpi_perf_data) { | |
2d06d8c4 | 579 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 580 | return -ENOMEM; |
09b4d1ee | 581 | } |
2fdf66b4 | 582 | for_each_possible_cpu(i) { |
eaa95840 | 583 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
584 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
585 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
586 | |
587 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
588 | free_acpi_perf_data(); | |
589 | return -ENOMEM; | |
590 | } | |
591 | } | |
09b4d1ee VP |
592 | |
593 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
594 | acpi_processor_preregister_performance(acpi_perf_data); |
595 | return 0; | |
09b4d1ee VP |
596 | } |
597 | ||
95625b8f | 598 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
599 | /* |
600 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
601 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
602 | * detected, this has a side effect of making CPU run at a different speed | |
603 | * than OS intended it to run at. Detect it and handle it cleanly. | |
604 | */ | |
605 | static int bios_with_sw_any_bug; | |
606 | ||
1855256c | 607 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
608 | { |
609 | bios_with_sw_any_bug = 1; | |
610 | return 0; | |
611 | } | |
612 | ||
1855256c | 613 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
614 | { |
615 | .callback = sw_any_bug_found, | |
616 | .ident = "Supermicro Server X6DLP", | |
617 | .matches = { | |
618 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
619 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
620 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
621 | }, | |
622 | }, | |
623 | { } | |
624 | }; | |
1a8e42fa PB |
625 | |
626 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
627 | { | |
293afe44 JV |
628 | /* Intel Xeon Processor 7100 Series Specification Update |
629 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
630 | * AL30: A Machine Check Exception (MCE) Occurring during an |
631 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 632 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
633 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
634 | if ((c->x86 == 15) && | |
635 | (c->x86_model == 6) && | |
293afe44 JV |
636 | (c->x86_mask == 8)) { |
637 | printk(KERN_INFO "acpi-cpufreq: Intel(R) " | |
638 | "Xeon(R) 7100 Errata AL30, processors may " | |
639 | "lock up on frequency changes: disabling " | |
640 | "acpi-cpufreq.\n"); | |
1a8e42fa | 641 | return -ENODEV; |
293afe44 | 642 | } |
1a8e42fa PB |
643 | } |
644 | return 0; | |
645 | } | |
95625b8f | 646 | #endif |
8adcc0c6 | 647 | |
64be7eed | 648 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 649 | { |
64be7eed VP |
650 | unsigned int i; |
651 | unsigned int valid_states = 0; | |
652 | unsigned int cpu = policy->cpu; | |
653 | struct acpi_cpufreq_data *data; | |
64be7eed | 654 | unsigned int result = 0; |
92cb7612 | 655 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 656 | struct acpi_processor_performance *perf; |
293afe44 JV |
657 | #ifdef CONFIG_SMP |
658 | static int blacklisted; | |
659 | #endif | |
1da177e4 | 660 | |
2d06d8c4 | 661 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 662 | |
1a8e42fa | 663 | #ifdef CONFIG_SMP |
293afe44 JV |
664 | if (blacklisted) |
665 | return blacklisted; | |
666 | blacklisted = acpi_cpufreq_blacklist(c); | |
667 | if (blacklisted) | |
668 | return blacklisted; | |
1a8e42fa PB |
669 | #endif |
670 | ||
d5b73cd8 | 671 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 672 | if (!data) |
64be7eed | 673 | return -ENOMEM; |
1da177e4 | 674 | |
f4fd3797 LT |
675 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
676 | result = -ENOMEM; | |
677 | goto err_free; | |
678 | } | |
679 | ||
b36128c8 | 680 | data->acpi_data = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 681 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 682 | policy->driver_data = data; |
1da177e4 | 683 | |
95dd7227 | 684 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 685 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 686 | |
fe27cb35 | 687 | result = acpi_processor_register_performance(data->acpi_data, cpu); |
1da177e4 | 688 | if (result) |
f4fd3797 | 689 | goto err_free_mask; |
1da177e4 | 690 | |
09b4d1ee | 691 | perf = data->acpi_data; |
09b4d1ee | 692 | policy->shared_type = perf->shared_type; |
95dd7227 | 693 | |
46f18e3a | 694 | /* |
95dd7227 | 695 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
696 | * coordination is required. |
697 | */ | |
698 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 699 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 700 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 701 | } |
f4fd3797 | 702 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
703 | |
704 | #ifdef CONFIG_SMP | |
705 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 706 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 707 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 708 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 709 | } |
acd31624 AP |
710 | |
711 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
712 | cpumask_clear(policy->cpus); | |
713 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
714 | cpumask_copy(data->freqdomain_cpus, |
715 | topology_sibling_cpumask(cpu)); | |
acd31624 AP |
716 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
717 | pr_info_once(PFX "overriding BIOS provided _PSD data\n"); | |
718 | } | |
8adcc0c6 | 719 | #endif |
09b4d1ee | 720 | |
1da177e4 | 721 | /* capability check */ |
09b4d1ee | 722 | if (perf->state_count <= 1) { |
2d06d8c4 | 723 | pr_debug("No P-States\n"); |
1da177e4 LT |
724 | result = -ENODEV; |
725 | goto err_unreg; | |
726 | } | |
09b4d1ee | 727 | |
fe27cb35 VP |
728 | if (perf->control_register.space_id != perf->status_register.space_id) { |
729 | result = -ENODEV; | |
730 | goto err_unreg; | |
731 | } | |
732 | ||
733 | switch (perf->control_register.space_id) { | |
64be7eed | 734 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
735 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
736 | boot_cpu_data.x86 == 0xf) { | |
737 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
738 | result = -ENODEV; | |
739 | goto err_unreg; | |
740 | } | |
2d06d8c4 | 741 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba VP |
742 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
743 | break; | |
64be7eed | 744 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 745 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
746 | if (check_est_cpu(cpu)) { |
747 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
748 | break; | |
dde9f7ba | 749 | } |
3dc9a633 MG |
750 | if (check_amd_hwpstate_cpu(cpu)) { |
751 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
752 | break; | |
753 | } | |
754 | result = -ENODEV; | |
755 | goto err_unreg; | |
64be7eed | 756 | default: |
2d06d8c4 | 757 | pr_debug("Unknown addr space %d\n", |
64be7eed | 758 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
759 | result = -ENODEV; |
760 | goto err_unreg; | |
761 | } | |
762 | ||
71508a1f | 763 | data->freq_table = kzalloc(sizeof(*data->freq_table) * |
95dd7227 | 764 | (perf->state_count+1), GFP_KERNEL); |
1da177e4 LT |
765 | if (!data->freq_table) { |
766 | result = -ENOMEM; | |
767 | goto err_unreg; | |
768 | } | |
769 | ||
770 | /* detect transition latency */ | |
771 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 772 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
773 | if ((perf->states[i].transition_latency * 1000) > |
774 | policy->cpuinfo.transition_latency) | |
775 | policy->cpuinfo.transition_latency = | |
776 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 777 | } |
1da177e4 | 778 | |
a59d1637 PV |
779 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
780 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
781 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 782 | policy->cpuinfo.transition_latency = 20 * 1000; |
61c8c67e JP |
783 | printk_once(KERN_INFO |
784 | "P-state transition latency capped at 20 uS\n"); | |
a59d1637 PV |
785 | } |
786 | ||
1da177e4 | 787 | /* table init */ |
3a58df35 DJ |
788 | for (i = 0; i < perf->state_count; i++) { |
789 | if (i > 0 && perf->states[i].core_frequency >= | |
3cdf552b | 790 | data->freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
791 | continue; |
792 | ||
50701588 | 793 | data->freq_table[valid_states].driver_data = i; |
fe27cb35 | 794 | data->freq_table[valid_states].frequency = |
64be7eed | 795 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 796 | valid_states++; |
1da177e4 | 797 | } |
3d4a7ef3 | 798 | data->freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 799 | perf->state = 0; |
1da177e4 | 800 | |
776b57be | 801 | result = cpufreq_table_validate_and_show(policy, data->freq_table); |
95dd7227 | 802 | if (result) |
1da177e4 | 803 | goto err_freqfree; |
1da177e4 | 804 | |
d876dfbb TR |
805 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
806 | printk(KERN_WARNING FW_WARN "P-state 0 is not max freq\n"); | |
807 | ||
a507ac4b | 808 | switch (perf->control_register.space_id) { |
64be7eed | 809 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
810 | /* |
811 | * The core will not set policy->cur, because | |
812 | * cpufreq_driver->get is NULL, so we need to set it here. | |
813 | * However, we have to guess it, because the current speed is | |
814 | * unknown and not detectable via IO ports. | |
815 | */ | |
dde9f7ba VP |
816 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
817 | break; | |
64be7eed | 818 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 819 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 820 | break; |
64be7eed | 821 | default: |
dde9f7ba VP |
822 | break; |
823 | } | |
824 | ||
1da177e4 LT |
825 | /* notify BIOS that we exist */ |
826 | acpi_processor_notify_smm(THIS_MODULE); | |
827 | ||
2d06d8c4 | 828 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 829 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 830 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 831 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
832 | (u32) perf->states[i].core_frequency, |
833 | (u32) perf->states[i].power, | |
834 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 835 | |
4b31e774 DB |
836 | /* |
837 | * the first call to ->target() should result in us actually | |
838 | * writing something to the appropriate registers. | |
839 | */ | |
840 | data->resume = 1; | |
64be7eed | 841 | |
fe27cb35 | 842 | return result; |
1da177e4 | 843 | |
95dd7227 | 844 | err_freqfree: |
1da177e4 | 845 | kfree(data->freq_table); |
95dd7227 | 846 | err_unreg: |
b2f8dc4c | 847 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
848 | err_free_mask: |
849 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 850 | err_free: |
1da177e4 | 851 | kfree(data); |
eb0b3e78 | 852 | policy->driver_data = NULL; |
1da177e4 | 853 | |
64be7eed | 854 | return result; |
1da177e4 LT |
855 | } |
856 | ||
64be7eed | 857 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 858 | { |
eb0b3e78 | 859 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 860 | |
2d06d8c4 | 861 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 LT |
862 | |
863 | if (data) { | |
eb0b3e78 | 864 | policy->driver_data = NULL; |
b2f8dc4c | 865 | acpi_processor_unregister_performance(data->acpi_perf_cpu); |
f4fd3797 | 866 | free_cpumask_var(data->freqdomain_cpus); |
dab5fff1 | 867 | kfree(data->freq_table); |
1da177e4 LT |
868 | kfree(data); |
869 | } | |
870 | ||
64be7eed | 871 | return 0; |
1da177e4 LT |
872 | } |
873 | ||
64be7eed | 874 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 875 | { |
eb0b3e78 | 876 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 877 | |
2d06d8c4 | 878 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
879 | |
880 | data->resume = 1; | |
881 | ||
64be7eed | 882 | return 0; |
1da177e4 LT |
883 | } |
884 | ||
64be7eed | 885 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 886 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 887 | &freqdomain_cpus, |
11269ff5 | 888 | NULL, /* this is a placeholder for cpb, do not remove */ |
1da177e4 LT |
889 | NULL, |
890 | }; | |
891 | ||
892 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 893 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 894 | .target_index = acpi_cpufreq_target, |
e2f74f35 TR |
895 | .bios_limit = acpi_processor_get_bios_limit, |
896 | .init = acpi_cpufreq_cpu_init, | |
897 | .exit = acpi_cpufreq_cpu_exit, | |
898 | .resume = acpi_cpufreq_resume, | |
899 | .name = "acpi-cpufreq", | |
e2f74f35 | 900 | .attr = acpi_cpufreq_attr, |
cfc9c8ed | 901 | .set_boost = _store_boost, |
1da177e4 LT |
902 | }; |
903 | ||
615b7300 AP |
904 | static void __init acpi_cpufreq_boost_init(void) |
905 | { | |
906 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
907 | msrs = msrs_alloc(); | |
908 | ||
909 | if (!msrs) | |
910 | return; | |
911 | ||
cfc9c8ed LM |
912 | acpi_cpufreq_driver.boost_supported = true; |
913 | acpi_cpufreq_driver.boost_enabled = boost_state(0); | |
0197fbd2 SB |
914 | |
915 | cpu_notifier_register_begin(); | |
615b7300 AP |
916 | |
917 | /* Force all MSRs to the same value */ | |
cfc9c8ed LM |
918 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, |
919 | cpu_online_mask); | |
615b7300 | 920 | |
0197fbd2 | 921 | __register_cpu_notifier(&boost_nb); |
615b7300 | 922 | |
0197fbd2 | 923 | cpu_notifier_register_done(); |
cfc9c8ed | 924 | } |
615b7300 AP |
925 | } |
926 | ||
eb8c68ef | 927 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 928 | { |
615b7300 AP |
929 | if (msrs) { |
930 | unregister_cpu_notifier(&boost_nb); | |
931 | ||
932 | msrs_free(msrs); | |
933 | msrs = NULL; | |
934 | } | |
935 | } | |
936 | ||
64be7eed | 937 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 938 | { |
50109292 FY |
939 | int ret; |
940 | ||
75c07581 RW |
941 | if (acpi_disabled) |
942 | return -ENODEV; | |
943 | ||
8a61e12e YL |
944 | /* don't keep reloading if cpufreq_driver exists */ |
945 | if (cpufreq_get_current_driver()) | |
75c07581 | 946 | return -EEXIST; |
ee297533 | 947 | |
2d06d8c4 | 948 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 949 | |
50109292 FY |
950 | ret = acpi_cpufreq_early_init(); |
951 | if (ret) | |
952 | return ret; | |
09b4d1ee | 953 | |
11269ff5 AP |
954 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
955 | /* this is a sysfs file with a strange name and an even stranger | |
956 | * semantic - per CPU instantiation, but system global effect. | |
957 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
958 | * only if configured. This is considered legacy code, which | |
959 | * will probably be removed at some point in the future. | |
960 | */ | |
961 | if (check_amd_hwpstate_cpu(0)) { | |
962 | struct freq_attr **iter; | |
963 | ||
964 | pr_debug("adding sysfs entry for cpb\n"); | |
965 | ||
966 | for (iter = acpi_cpufreq_attr; *iter != NULL; iter++) | |
967 | ; | |
968 | ||
969 | /* make sure there is a terminator behind it */ | |
970 | if (iter[1] == NULL) | |
971 | *iter = &cpb; | |
972 | } | |
973 | #endif | |
cfc9c8ed | 974 | acpi_cpufreq_boost_init(); |
11269ff5 | 975 | |
847aef6f | 976 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 977 | if (ret) { |
2fdf66b4 | 978 | free_acpi_perf_data(); |
eb8c68ef KRW |
979 | acpi_cpufreq_boost_exit(); |
980 | } | |
847aef6f | 981 | return ret; |
1da177e4 LT |
982 | } |
983 | ||
64be7eed | 984 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 985 | { |
2d06d8c4 | 986 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 987 | |
615b7300 AP |
988 | acpi_cpufreq_boost_exit(); |
989 | ||
1da177e4 LT |
990 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
991 | ||
50f4ddd4 | 992 | free_acpi_perf_data(); |
1da177e4 LT |
993 | } |
994 | ||
d395bf12 | 995 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 996 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
997 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
998 | "performed during frequency changes."); | |
1da177e4 LT |
999 | |
1000 | late_initcall(acpi_cpufreq_init); | |
1001 | module_exit(acpi_cpufreq_exit); | |
1002 | ||
efa17194 MG |
1003 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1004 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1005 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1006 | {} | |
1007 | }; | |
1008 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1009 | ||
c655affb RW |
1010 | static const struct acpi_device_id processor_device_ids[] = { |
1011 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1012 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1013 | {}, | |
1014 | }; | |
1015 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1016 | ||
1da177e4 | 1017 | MODULE_ALIAS("acpi"); |