]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a58df35 | 2 | * acpi-cpufreq.c - ACPI Processor P-States Driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com> | |
5 | * Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> | |
6 | * Copyright (C) 2002 - 2004 Dominik Brodowski <linux@brodo.de> | |
fe27cb35 | 7 | * Copyright (C) 2006 Denis Sadykov <denis.m.sadykov@intel.com> |
1da177e4 LT |
8 | * |
9 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or (at | |
14 | * your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, but | |
17 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License along | |
22 | * with this program; if not, write to the Free Software Foundation, Inc., | |
23 | * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. | |
24 | * | |
25 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
26 | */ | |
27 | ||
1c5864e2 JP |
28 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
29 | ||
1da177e4 LT |
30 | #include <linux/kernel.h> |
31 | #include <linux/module.h> | |
32 | #include <linux/init.h> | |
fe27cb35 VP |
33 | #include <linux/smp.h> |
34 | #include <linux/sched.h> | |
1da177e4 | 35 | #include <linux/cpufreq.h> |
d395bf12 | 36 | #include <linux/compiler.h> |
8adcc0c6 | 37 | #include <linux/dmi.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
1da177e4 LT |
39 | |
40 | #include <linux/acpi.h> | |
3a58df35 DJ |
41 | #include <linux/io.h> |
42 | #include <linux/delay.h> | |
43 | #include <linux/uaccess.h> | |
44 | ||
1da177e4 LT |
45 | #include <acpi/processor.h> |
46 | ||
dde9f7ba | 47 | #include <asm/msr.h> |
fe27cb35 VP |
48 | #include <asm/processor.h> |
49 | #include <asm/cpufeature.h> | |
fe27cb35 | 50 | |
1da177e4 LT |
51 | MODULE_AUTHOR("Paul Diefenbaugh, Dominik Brodowski"); |
52 | MODULE_DESCRIPTION("ACPI Processor P-States Driver"); | |
53 | MODULE_LICENSE("GPL"); | |
54 | ||
dde9f7ba VP |
55 | enum { |
56 | UNDEFINED_CAPABLE = 0, | |
57 | SYSTEM_INTEL_MSR_CAPABLE, | |
3dc9a633 | 58 | SYSTEM_AMD_MSR_CAPABLE, |
dde9f7ba VP |
59 | SYSTEM_IO_CAPABLE, |
60 | }; | |
61 | ||
62 | #define INTEL_MSR_RANGE (0xffff) | |
3dc9a633 | 63 | #define AMD_MSR_RANGE (0x7) |
dde9f7ba | 64 | |
615b7300 AP |
65 | #define MSR_K7_HWCR_CPB_DIS (1ULL << 25) |
66 | ||
fe27cb35 | 67 | struct acpi_cpufreq_data { |
64be7eed VP |
68 | unsigned int resume; |
69 | unsigned int cpu_feature; | |
8cfcfd39 | 70 | unsigned int acpi_perf_cpu; |
f4fd3797 | 71 | cpumask_var_t freqdomain_cpus; |
ed757a2c RW |
72 | void (*cpu_freq_write)(struct acpi_pct_register *reg, u32 val); |
73 | u32 (*cpu_freq_read)(struct acpi_pct_register *reg); | |
1da177e4 LT |
74 | }; |
75 | ||
50109292 | 76 | /* acpi_perf_data is a pointer to percpu data. */ |
3f6c4df7 | 77 | static struct acpi_processor_performance __percpu *acpi_perf_data; |
1da177e4 | 78 | |
3427616b RW |
79 | static inline struct acpi_processor_performance *to_perf_data(struct acpi_cpufreq_data *data) |
80 | { | |
81 | return per_cpu_ptr(acpi_perf_data, data->acpi_perf_cpu); | |
82 | } | |
83 | ||
1da177e4 LT |
84 | static struct cpufreq_driver acpi_cpufreq_driver; |
85 | ||
d395bf12 | 86 | static unsigned int acpi_pstate_strict; |
615b7300 AP |
87 | static struct msr __percpu *msrs; |
88 | ||
89 | static bool boost_state(unsigned int cpu) | |
90 | { | |
91 | u32 lo, hi; | |
92 | u64 msr; | |
93 | ||
94 | switch (boot_cpu_data.x86_vendor) { | |
95 | case X86_VENDOR_INTEL: | |
96 | rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi); | |
97 | msr = lo | ((u64)hi << 32); | |
98 | return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
99 | case X86_VENDOR_AMD: | |
100 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
101 | msr = lo | ((u64)hi << 32); | |
102 | return !(msr & MSR_K7_HWCR_CPB_DIS); | |
103 | } | |
104 | return false; | |
105 | } | |
106 | ||
107 | static void boost_set_msrs(bool enable, const struct cpumask *cpumask) | |
108 | { | |
109 | u32 cpu; | |
110 | u32 msr_addr; | |
111 | u64 msr_mask; | |
112 | ||
113 | switch (boot_cpu_data.x86_vendor) { | |
114 | case X86_VENDOR_INTEL: | |
115 | msr_addr = MSR_IA32_MISC_ENABLE; | |
116 | msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE; | |
117 | break; | |
118 | case X86_VENDOR_AMD: | |
119 | msr_addr = MSR_K7_HWCR; | |
120 | msr_mask = MSR_K7_HWCR_CPB_DIS; | |
121 | break; | |
122 | default: | |
123 | return; | |
124 | } | |
125 | ||
126 | rdmsr_on_cpus(cpumask, msr_addr, msrs); | |
127 | ||
128 | for_each_cpu(cpu, cpumask) { | |
129 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
130 | if (enable) | |
131 | reg->q &= ~msr_mask; | |
132 | else | |
133 | reg->q |= msr_mask; | |
134 | } | |
135 | ||
136 | wrmsr_on_cpus(cpumask, msr_addr, msrs); | |
137 | } | |
138 | ||
17135782 | 139 | static int set_boost(int val) |
615b7300 | 140 | { |
615b7300 | 141 | get_online_cpus(); |
615b7300 | 142 | boost_set_msrs(val, cpu_online_mask); |
615b7300 | 143 | put_online_cpus(); |
615b7300 AP |
144 | pr_debug("Core Boosting %sabled.\n", val ? "en" : "dis"); |
145 | ||
cfc9c8ed | 146 | return 0; |
615b7300 AP |
147 | } |
148 | ||
f4fd3797 LT |
149 | static ssize_t show_freqdomain_cpus(struct cpufreq_policy *policy, char *buf) |
150 | { | |
eb0b3e78 | 151 | struct acpi_cpufreq_data *data = policy->driver_data; |
f4fd3797 | 152 | |
e2530367 SP |
153 | if (unlikely(!data)) |
154 | return -ENODEV; | |
155 | ||
f4fd3797 LT |
156 | return cpufreq_show_cpus(data->freqdomain_cpus, buf); |
157 | } | |
158 | ||
159 | cpufreq_freq_attr_ro(freqdomain_cpus); | |
160 | ||
11269ff5 | 161 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
17135782 RW |
162 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, |
163 | size_t count) | |
cfc9c8ed LM |
164 | { |
165 | int ret; | |
17135782 | 166 | unsigned int val = 0; |
cfc9c8ed | 167 | |
7a6c79f2 | 168 | if (!acpi_cpufreq_driver.set_boost) |
cfc9c8ed LM |
169 | return -EINVAL; |
170 | ||
17135782 RW |
171 | ret = kstrtouint(buf, 10, &val); |
172 | if (ret || val > 1) | |
cfc9c8ed LM |
173 | return -EINVAL; |
174 | ||
17135782 | 175 | set_boost(val); |
cfc9c8ed LM |
176 | |
177 | return count; | |
178 | } | |
179 | ||
11269ff5 AP |
180 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) |
181 | { | |
cfc9c8ed | 182 | return sprintf(buf, "%u\n", acpi_cpufreq_driver.boost_enabled); |
11269ff5 AP |
183 | } |
184 | ||
59027d35 | 185 | cpufreq_freq_attr_rw(cpb); |
11269ff5 AP |
186 | #endif |
187 | ||
dde9f7ba VP |
188 | static int check_est_cpu(unsigned int cpuid) |
189 | { | |
92cb7612 | 190 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); |
dde9f7ba | 191 | |
0de51088 | 192 | return cpu_has(cpu, X86_FEATURE_EST); |
dde9f7ba VP |
193 | } |
194 | ||
3dc9a633 MG |
195 | static int check_amd_hwpstate_cpu(unsigned int cpuid) |
196 | { | |
197 | struct cpuinfo_x86 *cpu = &cpu_data(cpuid); | |
198 | ||
199 | return cpu_has(cpu, X86_FEATURE_HW_PSTATE); | |
200 | } | |
201 | ||
8cee1eed | 202 | static unsigned extract_io(struct cpufreq_policy *policy, u32 value) |
fe27cb35 | 203 | { |
8cee1eed | 204 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
205 | struct acpi_processor_performance *perf; |
206 | int i; | |
fe27cb35 | 207 | |
3427616b | 208 | perf = to_perf_data(data); |
fe27cb35 | 209 | |
3a58df35 | 210 | for (i = 0; i < perf->state_count; i++) { |
fe27cb35 | 211 | if (value == perf->states[i].status) |
8cee1eed | 212 | return policy->freq_table[i].frequency; |
fe27cb35 VP |
213 | } |
214 | return 0; | |
215 | } | |
216 | ||
8cee1eed | 217 | static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr) |
dde9f7ba | 218 | { |
8cee1eed | 219 | struct acpi_cpufreq_data *data = policy->driver_data; |
041526f9 | 220 | struct cpufreq_frequency_table *pos; |
a6f6e6e6 | 221 | struct acpi_processor_performance *perf; |
dde9f7ba | 222 | |
3dc9a633 MG |
223 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) |
224 | msr &= AMD_MSR_RANGE; | |
225 | else | |
226 | msr &= INTEL_MSR_RANGE; | |
227 | ||
3427616b | 228 | perf = to_perf_data(data); |
a6f6e6e6 | 229 | |
8cee1eed | 230 | cpufreq_for_each_entry(pos, policy->freq_table) |
041526f9 SK |
231 | if (msr == perf->states[pos->driver_data].status) |
232 | return pos->frequency; | |
8cee1eed | 233 | return policy->freq_table[0].frequency; |
dde9f7ba VP |
234 | } |
235 | ||
8cee1eed | 236 | static unsigned extract_freq(struct cpufreq_policy *policy, u32 val) |
dde9f7ba | 237 | { |
8cee1eed VK |
238 | struct acpi_cpufreq_data *data = policy->driver_data; |
239 | ||
dde9f7ba | 240 | switch (data->cpu_feature) { |
64be7eed | 241 | case SYSTEM_INTEL_MSR_CAPABLE: |
3dc9a633 | 242 | case SYSTEM_AMD_MSR_CAPABLE: |
8cee1eed | 243 | return extract_msr(policy, val); |
64be7eed | 244 | case SYSTEM_IO_CAPABLE: |
8cee1eed | 245 | return extract_io(policy, val); |
64be7eed | 246 | default: |
dde9f7ba VP |
247 | return 0; |
248 | } | |
249 | } | |
250 | ||
ac13b996 | 251 | static u32 cpu_freq_read_intel(struct acpi_pct_register *not_used) |
ed757a2c RW |
252 | { |
253 | u32 val, dummy; | |
dde9f7ba | 254 | |
ed757a2c RW |
255 | rdmsr(MSR_IA32_PERF_CTL, val, dummy); |
256 | return val; | |
257 | } | |
258 | ||
ac13b996 | 259 | static void cpu_freq_write_intel(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
260 | { |
261 | u32 lo, hi; | |
262 | ||
263 | rdmsr(MSR_IA32_PERF_CTL, lo, hi); | |
264 | lo = (lo & ~INTEL_MSR_RANGE) | (val & INTEL_MSR_RANGE); | |
265 | wrmsr(MSR_IA32_PERF_CTL, lo, hi); | |
266 | } | |
267 | ||
ac13b996 | 268 | static u32 cpu_freq_read_amd(struct acpi_pct_register *not_used) |
ed757a2c RW |
269 | { |
270 | u32 val, dummy; | |
271 | ||
272 | rdmsr(MSR_AMD_PERF_CTL, val, dummy); | |
273 | return val; | |
274 | } | |
275 | ||
ac13b996 | 276 | static void cpu_freq_write_amd(struct acpi_pct_register *not_used, u32 val) |
ed757a2c RW |
277 | { |
278 | wrmsr(MSR_AMD_PERF_CTL, val, 0); | |
279 | } | |
280 | ||
ac13b996 | 281 | static u32 cpu_freq_read_io(struct acpi_pct_register *reg) |
ed757a2c RW |
282 | { |
283 | u32 val; | |
284 | ||
285 | acpi_os_read_port(reg->address, &val, reg->bit_width); | |
286 | return val; | |
287 | } | |
288 | ||
ac13b996 | 289 | static void cpu_freq_write_io(struct acpi_pct_register *reg, u32 val) |
ed757a2c RW |
290 | { |
291 | acpi_os_write_port(reg->address, val, reg->bit_width); | |
292 | } | |
fe27cb35 VP |
293 | |
294 | struct drv_cmd { | |
ed757a2c | 295 | struct acpi_pct_register *reg; |
fe27cb35 | 296 | u32 val; |
ed757a2c RW |
297 | union { |
298 | void (*write)(struct acpi_pct_register *reg, u32 val); | |
299 | u32 (*read)(struct acpi_pct_register *reg); | |
300 | } func; | |
fe27cb35 VP |
301 | }; |
302 | ||
01599fca AM |
303 | /* Called via smp_call_function_single(), on the target CPU */ |
304 | static void do_drv_read(void *_cmd) | |
1da177e4 | 305 | { |
72859081 | 306 | struct drv_cmd *cmd = _cmd; |
dde9f7ba | 307 | |
ed757a2c | 308 | cmd->val = cmd->func.read(cmd->reg); |
fe27cb35 | 309 | } |
1da177e4 | 310 | |
ed757a2c | 311 | static u32 drv_read(struct acpi_cpufreq_data *data, const struct cpumask *mask) |
fe27cb35 | 312 | { |
ed757a2c RW |
313 | struct acpi_processor_performance *perf = to_perf_data(data); |
314 | struct drv_cmd cmd = { | |
315 | .reg = &perf->control_register, | |
316 | .func.read = data->cpu_freq_read, | |
317 | }; | |
318 | int err; | |
dde9f7ba | 319 | |
ed757a2c RW |
320 | err = smp_call_function_any(mask, do_drv_read, &cmd, 1); |
321 | WARN_ON_ONCE(err); /* smp_call_function_any() was buggy? */ | |
322 | return cmd.val; | |
fe27cb35 | 323 | } |
1da177e4 | 324 | |
ed757a2c RW |
325 | /* Called via smp_call_function_many(), on the target CPUs */ |
326 | static void do_drv_write(void *_cmd) | |
fe27cb35 | 327 | { |
ed757a2c | 328 | struct drv_cmd *cmd = _cmd; |
fe27cb35 | 329 | |
ed757a2c | 330 | cmd->func.write(cmd->reg, cmd->val); |
fe27cb35 VP |
331 | } |
332 | ||
ed757a2c RW |
333 | static void drv_write(struct acpi_cpufreq_data *data, |
334 | const struct cpumask *mask, u32 val) | |
fe27cb35 | 335 | { |
ed757a2c RW |
336 | struct acpi_processor_performance *perf = to_perf_data(data); |
337 | struct drv_cmd cmd = { | |
338 | .reg = &perf->control_register, | |
339 | .val = val, | |
340 | .func.write = data->cpu_freq_write, | |
341 | }; | |
ea34f43a LT |
342 | int this_cpu; |
343 | ||
344 | this_cpu = get_cpu(); | |
ed757a2c RW |
345 | if (cpumask_test_cpu(this_cpu, mask)) |
346 | do_drv_write(&cmd); | |
347 | ||
348 | smp_call_function_many(mask, do_drv_write, &cmd, 1); | |
ea34f43a | 349 | put_cpu(); |
fe27cb35 | 350 | } |
1da177e4 | 351 | |
ed757a2c | 352 | static u32 get_cur_val(const struct cpumask *mask, struct acpi_cpufreq_data *data) |
fe27cb35 | 353 | { |
ed757a2c | 354 | u32 val; |
1da177e4 | 355 | |
4d8bb537 | 356 | if (unlikely(cpumask_empty(mask))) |
fe27cb35 | 357 | return 0; |
1da177e4 | 358 | |
ed757a2c | 359 | val = drv_read(data, mask); |
1da177e4 | 360 | |
ed757a2c | 361 | pr_debug("get_cur_val = %u\n", val); |
fe27cb35 | 362 | |
ed757a2c | 363 | return val; |
fe27cb35 | 364 | } |
1da177e4 | 365 | |
fe27cb35 VP |
366 | static unsigned int get_cur_freq_on_cpu(unsigned int cpu) |
367 | { | |
eb0b3e78 PX |
368 | struct acpi_cpufreq_data *data; |
369 | struct cpufreq_policy *policy; | |
64be7eed | 370 | unsigned int freq; |
e56a727b | 371 | unsigned int cached_freq; |
fe27cb35 | 372 | |
2d06d8c4 | 373 | pr_debug("get_cur_freq_on_cpu (%d)\n", cpu); |
fe27cb35 | 374 | |
1f0bd44e | 375 | policy = cpufreq_cpu_get_raw(cpu); |
eb0b3e78 PX |
376 | if (unlikely(!policy)) |
377 | return 0; | |
378 | ||
379 | data = policy->driver_data; | |
8cee1eed | 380 | if (unlikely(!data || !policy->freq_table)) |
fe27cb35 | 381 | return 0; |
1da177e4 | 382 | |
8cee1eed VK |
383 | cached_freq = policy->freq_table[to_perf_data(data)->state].frequency; |
384 | freq = extract_freq(policy, get_cur_val(cpumask_of(cpu), data)); | |
e56a727b VP |
385 | if (freq != cached_freq) { |
386 | /* | |
387 | * The dreaded BIOS frequency change behind our back. | |
388 | * Force set the frequency on next target call. | |
389 | */ | |
390 | data->resume = 1; | |
391 | } | |
392 | ||
2d06d8c4 | 393 | pr_debug("cur freq = %u\n", freq); |
1da177e4 | 394 | |
fe27cb35 | 395 | return freq; |
1da177e4 LT |
396 | } |
397 | ||
8cee1eed VK |
398 | static unsigned int check_freqs(struct cpufreq_policy *policy, |
399 | const struct cpumask *mask, unsigned int freq) | |
fe27cb35 | 400 | { |
8cee1eed | 401 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed VP |
402 | unsigned int cur_freq; |
403 | unsigned int i; | |
1da177e4 | 404 | |
3a58df35 | 405 | for (i = 0; i < 100; i++) { |
8cee1eed | 406 | cur_freq = extract_freq(policy, get_cur_val(mask, data)); |
fe27cb35 VP |
407 | if (cur_freq == freq) |
408 | return 1; | |
409 | udelay(10); | |
410 | } | |
411 | return 0; | |
412 | } | |
413 | ||
414 | static int acpi_cpufreq_target(struct cpufreq_policy *policy, | |
9c0ebcf7 | 415 | unsigned int index) |
1da177e4 | 416 | { |
eb0b3e78 | 417 | struct acpi_cpufreq_data *data = policy->driver_data; |
64be7eed | 418 | struct acpi_processor_performance *perf; |
ed757a2c | 419 | const struct cpumask *mask; |
8edc59d9 | 420 | unsigned int next_perf_state = 0; /* Index into perf table */ |
64be7eed | 421 | int result = 0; |
fe27cb35 | 422 | |
8cee1eed | 423 | if (unlikely(!data)) { |
fe27cb35 VP |
424 | return -ENODEV; |
425 | } | |
1da177e4 | 426 | |
3427616b | 427 | perf = to_perf_data(data); |
8cee1eed | 428 | next_perf_state = policy->freq_table[index].driver_data; |
7650b281 | 429 | if (perf->state == next_perf_state) { |
fe27cb35 | 430 | if (unlikely(data->resume)) { |
2d06d8c4 | 431 | pr_debug("Called after resume, resetting to P%d\n", |
64be7eed | 432 | next_perf_state); |
fe27cb35 VP |
433 | data->resume = 0; |
434 | } else { | |
2d06d8c4 | 435 | pr_debug("Already at target state (P%d)\n", |
64be7eed | 436 | next_perf_state); |
9a909a14 | 437 | return 0; |
fe27cb35 | 438 | } |
09b4d1ee VP |
439 | } |
440 | ||
ed757a2c RW |
441 | /* |
442 | * The core won't allow CPUs to go away until the governor has been | |
443 | * stopped, so we can rely on the stability of policy->cpus. | |
444 | */ | |
445 | mask = policy->shared_type == CPUFREQ_SHARED_TYPE_ANY ? | |
446 | cpumask_of(policy->cpu) : policy->cpus; | |
09b4d1ee | 447 | |
ed757a2c | 448 | drv_write(data, mask, perf->states[next_perf_state].control); |
09b4d1ee | 449 | |
fe27cb35 | 450 | if (acpi_pstate_strict) { |
8cee1eed VK |
451 | if (!check_freqs(policy, mask, |
452 | policy->freq_table[index].frequency)) { | |
2d06d8c4 | 453 | pr_debug("acpi_cpufreq_target failed (%d)\n", |
64be7eed | 454 | policy->cpu); |
4d8bb537 | 455 | result = -EAGAIN; |
09b4d1ee VP |
456 | } |
457 | } | |
458 | ||
e15d8309 VK |
459 | if (!result) |
460 | perf->state = next_perf_state; | |
fe27cb35 VP |
461 | |
462 | return result; | |
1da177e4 LT |
463 | } |
464 | ||
b7898fda RW |
465 | unsigned int acpi_cpufreq_fast_switch(struct cpufreq_policy *policy, |
466 | unsigned int target_freq) | |
467 | { | |
468 | struct acpi_cpufreq_data *data = policy->driver_data; | |
469 | struct acpi_processor_performance *perf; | |
470 | struct cpufreq_frequency_table *entry; | |
82577360 | 471 | unsigned int next_perf_state, next_freq, index; |
b7898fda RW |
472 | |
473 | /* | |
474 | * Find the closest frequency above target_freq. | |
b7898fda | 475 | */ |
5b6667c7 SM |
476 | if (policy->cached_target_freq == target_freq) |
477 | index = policy->cached_resolved_idx; | |
478 | else | |
479 | index = cpufreq_table_find_index_dl(policy, target_freq); | |
82577360 VK |
480 | |
481 | entry = &policy->freq_table[index]; | |
b7898fda RW |
482 | next_freq = entry->frequency; |
483 | next_perf_state = entry->driver_data; | |
484 | ||
485 | perf = to_perf_data(data); | |
486 | if (perf->state == next_perf_state) { | |
487 | if (unlikely(data->resume)) | |
488 | data->resume = 0; | |
489 | else | |
490 | return next_freq; | |
491 | } | |
492 | ||
493 | data->cpu_freq_write(&perf->control_register, | |
494 | perf->states[next_perf_state].control); | |
495 | perf->state = next_perf_state; | |
496 | return next_freq; | |
497 | } | |
498 | ||
1da177e4 | 499 | static unsigned long |
64be7eed | 500 | acpi_cpufreq_guess_freq(struct acpi_cpufreq_data *data, unsigned int cpu) |
1da177e4 | 501 | { |
3427616b | 502 | struct acpi_processor_performance *perf; |
09b4d1ee | 503 | |
3427616b | 504 | perf = to_perf_data(data); |
1da177e4 LT |
505 | if (cpu_khz) { |
506 | /* search the closest match to cpu_khz */ | |
507 | unsigned int i; | |
508 | unsigned long freq; | |
09b4d1ee | 509 | unsigned long freqn = perf->states[0].core_frequency * 1000; |
1da177e4 | 510 | |
3a58df35 | 511 | for (i = 0; i < (perf->state_count-1); i++) { |
1da177e4 | 512 | freq = freqn; |
95dd7227 | 513 | freqn = perf->states[i+1].core_frequency * 1000; |
1da177e4 | 514 | if ((2 * cpu_khz) > (freqn + freq)) { |
09b4d1ee | 515 | perf->state = i; |
64be7eed | 516 | return freq; |
1da177e4 LT |
517 | } |
518 | } | |
95dd7227 | 519 | perf->state = perf->state_count-1; |
64be7eed | 520 | return freqn; |
09b4d1ee | 521 | } else { |
1da177e4 | 522 | /* assume CPU is at P0... */ |
09b4d1ee VP |
523 | perf->state = 0; |
524 | return perf->states[0].core_frequency * 1000; | |
525 | } | |
1da177e4 LT |
526 | } |
527 | ||
2fdf66b4 RR |
528 | static void free_acpi_perf_data(void) |
529 | { | |
530 | unsigned int i; | |
531 | ||
532 | /* Freeing a NULL pointer is OK, and alloc_percpu zeroes. */ | |
533 | for_each_possible_cpu(i) | |
534 | free_cpumask_var(per_cpu_ptr(acpi_perf_data, i) | |
535 | ->shared_cpu_map); | |
536 | free_percpu(acpi_perf_data); | |
537 | } | |
538 | ||
615b7300 AP |
539 | static int boost_notify(struct notifier_block *nb, unsigned long action, |
540 | void *hcpu) | |
541 | { | |
542 | unsigned cpu = (long)hcpu; | |
543 | const struct cpumask *cpumask; | |
544 | ||
545 | cpumask = get_cpu_mask(cpu); | |
546 | ||
547 | /* | |
548 | * Clear the boost-disable bit on the CPU_DOWN path so that | |
549 | * this cpu cannot block the remaining ones from boosting. On | |
550 | * the CPU_UP path we simply keep the boost-disable flag in | |
551 | * sync with the current global state. | |
552 | */ | |
553 | ||
554 | switch (action) { | |
ed72662a RC |
555 | case CPU_DOWN_FAILED: |
556 | case CPU_DOWN_FAILED_FROZEN: | |
557 | case CPU_ONLINE: | |
558 | case CPU_ONLINE_FROZEN: | |
cfc9c8ed | 559 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, cpumask); |
615b7300 AP |
560 | break; |
561 | ||
562 | case CPU_DOWN_PREPARE: | |
563 | case CPU_DOWN_PREPARE_FROZEN: | |
564 | boost_set_msrs(1, cpumask); | |
565 | break; | |
566 | ||
567 | default: | |
568 | break; | |
569 | } | |
570 | ||
571 | return NOTIFY_OK; | |
572 | } | |
573 | ||
574 | ||
575 | static struct notifier_block boost_nb = { | |
576 | .notifier_call = boost_notify, | |
577 | }; | |
578 | ||
09b4d1ee VP |
579 | /* |
580 | * acpi_cpufreq_early_init - initialize ACPI P-States library | |
581 | * | |
582 | * Initialize the ACPI P-States library (drivers/acpi/processor_perflib.c) | |
583 | * in order to determine correct frequency and voltage pairings. We can | |
584 | * do _PDC and _PSD and find out the processor dependency for the | |
585 | * actual init that will happen later... | |
586 | */ | |
50109292 | 587 | static int __init acpi_cpufreq_early_init(void) |
09b4d1ee | 588 | { |
2fdf66b4 | 589 | unsigned int i; |
2d06d8c4 | 590 | pr_debug("acpi_cpufreq_early_init\n"); |
09b4d1ee | 591 | |
50109292 FY |
592 | acpi_perf_data = alloc_percpu(struct acpi_processor_performance); |
593 | if (!acpi_perf_data) { | |
2d06d8c4 | 594 | pr_debug("Memory allocation error for acpi_perf_data.\n"); |
50109292 | 595 | return -ENOMEM; |
09b4d1ee | 596 | } |
2fdf66b4 | 597 | for_each_possible_cpu(i) { |
eaa95840 | 598 | if (!zalloc_cpumask_var_node( |
80855f73 MT |
599 | &per_cpu_ptr(acpi_perf_data, i)->shared_cpu_map, |
600 | GFP_KERNEL, cpu_to_node(i))) { | |
2fdf66b4 RR |
601 | |
602 | /* Freeing a NULL pointer is OK: alloc_percpu zeroes. */ | |
603 | free_acpi_perf_data(); | |
604 | return -ENOMEM; | |
605 | } | |
606 | } | |
09b4d1ee VP |
607 | |
608 | /* Do initialization in ACPI core */ | |
fe27cb35 VP |
609 | acpi_processor_preregister_performance(acpi_perf_data); |
610 | return 0; | |
09b4d1ee VP |
611 | } |
612 | ||
95625b8f | 613 | #ifdef CONFIG_SMP |
8adcc0c6 VP |
614 | /* |
615 | * Some BIOSes do SW_ANY coordination internally, either set it up in hw | |
616 | * or do it in BIOS firmware and won't inform about it to OS. If not | |
617 | * detected, this has a side effect of making CPU run at a different speed | |
618 | * than OS intended it to run at. Detect it and handle it cleanly. | |
619 | */ | |
620 | static int bios_with_sw_any_bug; | |
621 | ||
1855256c | 622 | static int sw_any_bug_found(const struct dmi_system_id *d) |
8adcc0c6 VP |
623 | { |
624 | bios_with_sw_any_bug = 1; | |
625 | return 0; | |
626 | } | |
627 | ||
1855256c | 628 | static const struct dmi_system_id sw_any_bug_dmi_table[] = { |
8adcc0c6 VP |
629 | { |
630 | .callback = sw_any_bug_found, | |
631 | .ident = "Supermicro Server X6DLP", | |
632 | .matches = { | |
633 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
634 | DMI_MATCH(DMI_BIOS_VERSION, "080010"), | |
635 | DMI_MATCH(DMI_PRODUCT_NAME, "X6DLP"), | |
636 | }, | |
637 | }, | |
638 | { } | |
639 | }; | |
1a8e42fa PB |
640 | |
641 | static int acpi_cpufreq_blacklist(struct cpuinfo_x86 *c) | |
642 | { | |
293afe44 JV |
643 | /* Intel Xeon Processor 7100 Series Specification Update |
644 | * http://www.intel.com/Assets/PDF/specupdate/314554.pdf | |
1a8e42fa PB |
645 | * AL30: A Machine Check Exception (MCE) Occurring during an |
646 | * Enhanced Intel SpeedStep Technology Ratio Change May Cause | |
293afe44 | 647 | * Both Processor Cores to Lock Up. */ |
1a8e42fa PB |
648 | if (c->x86_vendor == X86_VENDOR_INTEL) { |
649 | if ((c->x86 == 15) && | |
650 | (c->x86_model == 6) && | |
293afe44 | 651 | (c->x86_mask == 8)) { |
1c5864e2 | 652 | pr_info("Intel(R) Xeon(R) 7100 Errata AL30, processors may lock up on frequency changes: disabling acpi-cpufreq\n"); |
1a8e42fa | 653 | return -ENODEV; |
293afe44 | 654 | } |
1a8e42fa PB |
655 | } |
656 | return 0; | |
657 | } | |
95625b8f | 658 | #endif |
8adcc0c6 | 659 | |
64be7eed | 660 | static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy) |
1da177e4 | 661 | { |
64be7eed VP |
662 | unsigned int i; |
663 | unsigned int valid_states = 0; | |
664 | unsigned int cpu = policy->cpu; | |
665 | struct acpi_cpufreq_data *data; | |
64be7eed | 666 | unsigned int result = 0; |
92cb7612 | 667 | struct cpuinfo_x86 *c = &cpu_data(policy->cpu); |
64be7eed | 668 | struct acpi_processor_performance *perf; |
8cee1eed | 669 | struct cpufreq_frequency_table *freq_table; |
293afe44 JV |
670 | #ifdef CONFIG_SMP |
671 | static int blacklisted; | |
672 | #endif | |
1da177e4 | 673 | |
2d06d8c4 | 674 | pr_debug("acpi_cpufreq_cpu_init\n"); |
1da177e4 | 675 | |
1a8e42fa | 676 | #ifdef CONFIG_SMP |
293afe44 JV |
677 | if (blacklisted) |
678 | return blacklisted; | |
679 | blacklisted = acpi_cpufreq_blacklist(c); | |
680 | if (blacklisted) | |
681 | return blacklisted; | |
1a8e42fa PB |
682 | #endif |
683 | ||
d5b73cd8 | 684 | data = kzalloc(sizeof(*data), GFP_KERNEL); |
1da177e4 | 685 | if (!data) |
64be7eed | 686 | return -ENOMEM; |
1da177e4 | 687 | |
f4fd3797 LT |
688 | if (!zalloc_cpumask_var(&data->freqdomain_cpus, GFP_KERNEL)) { |
689 | result = -ENOMEM; | |
690 | goto err_free; | |
691 | } | |
692 | ||
3427616b | 693 | perf = per_cpu_ptr(acpi_perf_data, cpu); |
8cfcfd39 | 694 | data->acpi_perf_cpu = cpu; |
eb0b3e78 | 695 | policy->driver_data = data; |
1da177e4 | 696 | |
95dd7227 | 697 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) |
fe27cb35 | 698 | acpi_cpufreq_driver.flags |= CPUFREQ_CONST_LOOPS; |
1da177e4 | 699 | |
3427616b | 700 | result = acpi_processor_register_performance(perf, cpu); |
1da177e4 | 701 | if (result) |
f4fd3797 | 702 | goto err_free_mask; |
1da177e4 | 703 | |
09b4d1ee | 704 | policy->shared_type = perf->shared_type; |
95dd7227 | 705 | |
46f18e3a | 706 | /* |
95dd7227 | 707 | * Will let policy->cpus know about dependency only when software |
46f18e3a VP |
708 | * coordination is required. |
709 | */ | |
710 | if (policy->shared_type == CPUFREQ_SHARED_TYPE_ALL || | |
8adcc0c6 | 711 | policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { |
835481d9 | 712 | cpumask_copy(policy->cpus, perf->shared_cpu_map); |
8adcc0c6 | 713 | } |
f4fd3797 | 714 | cpumask_copy(data->freqdomain_cpus, perf->shared_cpu_map); |
8adcc0c6 VP |
715 | |
716 | #ifdef CONFIG_SMP | |
717 | dmi_check_system(sw_any_bug_dmi_table); | |
2624f90c | 718 | if (bios_with_sw_any_bug && !policy_is_shared(policy)) { |
8adcc0c6 | 719 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; |
3280c3c8 | 720 | cpumask_copy(policy->cpus, topology_core_cpumask(cpu)); |
8adcc0c6 | 721 | } |
acd31624 AP |
722 | |
723 | if (check_amd_hwpstate_cpu(cpu) && !acpi_pstate_strict) { | |
724 | cpumask_clear(policy->cpus); | |
725 | cpumask_set_cpu(cpu, policy->cpus); | |
3280c3c8 BG |
726 | cpumask_copy(data->freqdomain_cpus, |
727 | topology_sibling_cpumask(cpu)); | |
acd31624 | 728 | policy->shared_type = CPUFREQ_SHARED_TYPE_HW; |
1c5864e2 | 729 | pr_info_once("overriding BIOS provided _PSD data\n"); |
acd31624 | 730 | } |
8adcc0c6 | 731 | #endif |
09b4d1ee | 732 | |
1da177e4 | 733 | /* capability check */ |
09b4d1ee | 734 | if (perf->state_count <= 1) { |
2d06d8c4 | 735 | pr_debug("No P-States\n"); |
1da177e4 LT |
736 | result = -ENODEV; |
737 | goto err_unreg; | |
738 | } | |
09b4d1ee | 739 | |
fe27cb35 VP |
740 | if (perf->control_register.space_id != perf->status_register.space_id) { |
741 | result = -ENODEV; | |
742 | goto err_unreg; | |
743 | } | |
744 | ||
745 | switch (perf->control_register.space_id) { | |
64be7eed | 746 | case ACPI_ADR_SPACE_SYSTEM_IO: |
c40a4518 MG |
747 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && |
748 | boot_cpu_data.x86 == 0xf) { | |
749 | pr_debug("AMD K8 systems must use native drivers.\n"); | |
750 | result = -ENODEV; | |
751 | goto err_unreg; | |
752 | } | |
2d06d8c4 | 753 | pr_debug("SYSTEM IO addr space\n"); |
dde9f7ba | 754 | data->cpu_feature = SYSTEM_IO_CAPABLE; |
ed757a2c RW |
755 | data->cpu_freq_read = cpu_freq_read_io; |
756 | data->cpu_freq_write = cpu_freq_write_io; | |
dde9f7ba | 757 | break; |
64be7eed | 758 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
2d06d8c4 | 759 | pr_debug("HARDWARE addr space\n"); |
3dc9a633 MG |
760 | if (check_est_cpu(cpu)) { |
761 | data->cpu_feature = SYSTEM_INTEL_MSR_CAPABLE; | |
ed757a2c RW |
762 | data->cpu_freq_read = cpu_freq_read_intel; |
763 | data->cpu_freq_write = cpu_freq_write_intel; | |
3dc9a633 | 764 | break; |
dde9f7ba | 765 | } |
3dc9a633 MG |
766 | if (check_amd_hwpstate_cpu(cpu)) { |
767 | data->cpu_feature = SYSTEM_AMD_MSR_CAPABLE; | |
ed757a2c RW |
768 | data->cpu_freq_read = cpu_freq_read_amd; |
769 | data->cpu_freq_write = cpu_freq_write_amd; | |
3dc9a633 MG |
770 | break; |
771 | } | |
772 | result = -ENODEV; | |
773 | goto err_unreg; | |
64be7eed | 774 | default: |
2d06d8c4 | 775 | pr_debug("Unknown addr space %d\n", |
64be7eed | 776 | (u32) (perf->control_register.space_id)); |
1da177e4 LT |
777 | result = -ENODEV; |
778 | goto err_unreg; | |
779 | } | |
780 | ||
8cee1eed | 781 | freq_table = kzalloc(sizeof(*freq_table) * |
95dd7227 | 782 | (perf->state_count+1), GFP_KERNEL); |
8cee1eed | 783 | if (!freq_table) { |
1da177e4 LT |
784 | result = -ENOMEM; |
785 | goto err_unreg; | |
786 | } | |
787 | ||
788 | /* detect transition latency */ | |
789 | policy->cpuinfo.transition_latency = 0; | |
3a58df35 | 790 | for (i = 0; i < perf->state_count; i++) { |
64be7eed VP |
791 | if ((perf->states[i].transition_latency * 1000) > |
792 | policy->cpuinfo.transition_latency) | |
793 | policy->cpuinfo.transition_latency = | |
794 | perf->states[i].transition_latency * 1000; | |
1da177e4 | 795 | } |
1da177e4 | 796 | |
a59d1637 PV |
797 | /* Check for high latency (>20uS) from buggy BIOSes, like on T42 */ |
798 | if (perf->control_register.space_id == ACPI_ADR_SPACE_FIXED_HARDWARE && | |
799 | policy->cpuinfo.transition_latency > 20 * 1000) { | |
a59d1637 | 800 | policy->cpuinfo.transition_latency = 20 * 1000; |
b49c22a6 | 801 | pr_info_once("P-state transition latency capped at 20 uS\n"); |
a59d1637 PV |
802 | } |
803 | ||
1da177e4 | 804 | /* table init */ |
3a58df35 DJ |
805 | for (i = 0; i < perf->state_count; i++) { |
806 | if (i > 0 && perf->states[i].core_frequency >= | |
8cee1eed | 807 | freq_table[valid_states-1].frequency / 1000) |
fe27cb35 VP |
808 | continue; |
809 | ||
8cee1eed VK |
810 | freq_table[valid_states].driver_data = i; |
811 | freq_table[valid_states].frequency = | |
64be7eed | 812 | perf->states[i].core_frequency * 1000; |
fe27cb35 | 813 | valid_states++; |
1da177e4 | 814 | } |
8cee1eed | 815 | freq_table[valid_states].frequency = CPUFREQ_TABLE_END; |
8edc59d9 | 816 | perf->state = 0; |
1da177e4 | 817 | |
8cee1eed | 818 | result = cpufreq_table_validate_and_show(policy, freq_table); |
95dd7227 | 819 | if (result) |
1da177e4 | 820 | goto err_freqfree; |
1da177e4 | 821 | |
d876dfbb | 822 | if (perf->states[0].core_frequency * 1000 != policy->cpuinfo.max_freq) |
b49c22a6 | 823 | pr_warn(FW_WARN "P-state 0 is not max freq\n"); |
d876dfbb | 824 | |
a507ac4b | 825 | switch (perf->control_register.space_id) { |
64be7eed | 826 | case ACPI_ADR_SPACE_SYSTEM_IO: |
1bab64d5 VK |
827 | /* |
828 | * The core will not set policy->cur, because | |
829 | * cpufreq_driver->get is NULL, so we need to set it here. | |
830 | * However, we have to guess it, because the current speed is | |
831 | * unknown and not detectable via IO ports. | |
832 | */ | |
dde9f7ba VP |
833 | policy->cur = acpi_cpufreq_guess_freq(data, policy->cpu); |
834 | break; | |
64be7eed | 835 | case ACPI_ADR_SPACE_FIXED_HARDWARE: |
7650b281 | 836 | acpi_cpufreq_driver.get = get_cur_freq_on_cpu; |
dde9f7ba | 837 | break; |
64be7eed | 838 | default: |
dde9f7ba VP |
839 | break; |
840 | } | |
841 | ||
1da177e4 LT |
842 | /* notify BIOS that we exist */ |
843 | acpi_processor_notify_smm(THIS_MODULE); | |
844 | ||
2d06d8c4 | 845 | pr_debug("CPU%u - ACPI performance management activated.\n", cpu); |
09b4d1ee | 846 | for (i = 0; i < perf->state_count; i++) |
2d06d8c4 | 847 | pr_debug(" %cP%d: %d MHz, %d mW, %d uS\n", |
64be7eed | 848 | (i == perf->state ? '*' : ' '), i, |
09b4d1ee VP |
849 | (u32) perf->states[i].core_frequency, |
850 | (u32) perf->states[i].power, | |
851 | (u32) perf->states[i].transition_latency); | |
1da177e4 | 852 | |
4b31e774 DB |
853 | /* |
854 | * the first call to ->target() should result in us actually | |
855 | * writing something to the appropriate registers. | |
856 | */ | |
857 | data->resume = 1; | |
64be7eed | 858 | |
b7898fda RW |
859 | policy->fast_switch_possible = !acpi_pstate_strict && |
860 | !(policy_is_shared(policy) && policy->shared_type != CPUFREQ_SHARED_TYPE_ANY); | |
861 | ||
fe27cb35 | 862 | return result; |
1da177e4 | 863 | |
95dd7227 | 864 | err_freqfree: |
8cee1eed | 865 | kfree(freq_table); |
95dd7227 | 866 | err_unreg: |
b2f8dc4c | 867 | acpi_processor_unregister_performance(cpu); |
f4fd3797 LT |
868 | err_free_mask: |
869 | free_cpumask_var(data->freqdomain_cpus); | |
95dd7227 | 870 | err_free: |
1da177e4 | 871 | kfree(data); |
eb0b3e78 | 872 | policy->driver_data = NULL; |
1da177e4 | 873 | |
64be7eed | 874 | return result; |
1da177e4 LT |
875 | } |
876 | ||
64be7eed | 877 | static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy) |
1da177e4 | 878 | { |
eb0b3e78 | 879 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 880 | |
2d06d8c4 | 881 | pr_debug("acpi_cpufreq_cpu_exit\n"); |
1da177e4 | 882 | |
9b55f55a VK |
883 | policy->fast_switch_possible = false; |
884 | policy->driver_data = NULL; | |
885 | acpi_processor_unregister_performance(data->acpi_perf_cpu); | |
886 | free_cpumask_var(data->freqdomain_cpus); | |
8cee1eed | 887 | kfree(policy->freq_table); |
9b55f55a | 888 | kfree(data); |
1da177e4 | 889 | |
64be7eed | 890 | return 0; |
1da177e4 LT |
891 | } |
892 | ||
64be7eed | 893 | static int acpi_cpufreq_resume(struct cpufreq_policy *policy) |
1da177e4 | 894 | { |
eb0b3e78 | 895 | struct acpi_cpufreq_data *data = policy->driver_data; |
1da177e4 | 896 | |
2d06d8c4 | 897 | pr_debug("acpi_cpufreq_resume\n"); |
1da177e4 LT |
898 | |
899 | data->resume = 1; | |
900 | ||
64be7eed | 901 | return 0; |
1da177e4 LT |
902 | } |
903 | ||
64be7eed | 904 | static struct freq_attr *acpi_cpufreq_attr[] = { |
1da177e4 | 905 | &cpufreq_freq_attr_scaling_available_freqs, |
f4fd3797 | 906 | &freqdomain_cpus, |
f56c50e3 RW |
907 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
908 | &cpb, | |
909 | #endif | |
1da177e4 LT |
910 | NULL, |
911 | }; | |
912 | ||
913 | static struct cpufreq_driver acpi_cpufreq_driver = { | |
db9be219 | 914 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 915 | .target_index = acpi_cpufreq_target, |
b7898fda | 916 | .fast_switch = acpi_cpufreq_fast_switch, |
e2f74f35 TR |
917 | .bios_limit = acpi_processor_get_bios_limit, |
918 | .init = acpi_cpufreq_cpu_init, | |
919 | .exit = acpi_cpufreq_cpu_exit, | |
920 | .resume = acpi_cpufreq_resume, | |
921 | .name = "acpi-cpufreq", | |
e2f74f35 | 922 | .attr = acpi_cpufreq_attr, |
1da177e4 LT |
923 | }; |
924 | ||
615b7300 AP |
925 | static void __init acpi_cpufreq_boost_init(void) |
926 | { | |
927 | if (boot_cpu_has(X86_FEATURE_CPB) || boot_cpu_has(X86_FEATURE_IDA)) { | |
928 | msrs = msrs_alloc(); | |
929 | ||
930 | if (!msrs) | |
931 | return; | |
932 | ||
7a6c79f2 | 933 | acpi_cpufreq_driver.set_boost = set_boost; |
cfc9c8ed | 934 | acpi_cpufreq_driver.boost_enabled = boost_state(0); |
0197fbd2 SB |
935 | |
936 | cpu_notifier_register_begin(); | |
615b7300 AP |
937 | |
938 | /* Force all MSRs to the same value */ | |
cfc9c8ed LM |
939 | boost_set_msrs(acpi_cpufreq_driver.boost_enabled, |
940 | cpu_online_mask); | |
615b7300 | 941 | |
0197fbd2 | 942 | __register_cpu_notifier(&boost_nb); |
615b7300 | 943 | |
0197fbd2 | 944 | cpu_notifier_register_done(); |
cfc9c8ed | 945 | } |
615b7300 AP |
946 | } |
947 | ||
eb8c68ef | 948 | static void acpi_cpufreq_boost_exit(void) |
615b7300 | 949 | { |
615b7300 AP |
950 | if (msrs) { |
951 | unregister_cpu_notifier(&boost_nb); | |
952 | ||
953 | msrs_free(msrs); | |
954 | msrs = NULL; | |
955 | } | |
956 | } | |
957 | ||
64be7eed | 958 | static int __init acpi_cpufreq_init(void) |
1da177e4 | 959 | { |
50109292 FY |
960 | int ret; |
961 | ||
75c07581 RW |
962 | if (acpi_disabled) |
963 | return -ENODEV; | |
964 | ||
8a61e12e YL |
965 | /* don't keep reloading if cpufreq_driver exists */ |
966 | if (cpufreq_get_current_driver()) | |
75c07581 | 967 | return -EEXIST; |
ee297533 | 968 | |
2d06d8c4 | 969 | pr_debug("acpi_cpufreq_init\n"); |
1da177e4 | 970 | |
50109292 FY |
971 | ret = acpi_cpufreq_early_init(); |
972 | if (ret) | |
973 | return ret; | |
09b4d1ee | 974 | |
11269ff5 AP |
975 | #ifdef CONFIG_X86_ACPI_CPUFREQ_CPB |
976 | /* this is a sysfs file with a strange name and an even stranger | |
977 | * semantic - per CPU instantiation, but system global effect. | |
978 | * Lets enable it only on AMD CPUs for compatibility reasons and | |
979 | * only if configured. This is considered legacy code, which | |
980 | * will probably be removed at some point in the future. | |
981 | */ | |
f56c50e3 RW |
982 | if (!check_amd_hwpstate_cpu(0)) { |
983 | struct freq_attr **attr; | |
11269ff5 | 984 | |
f56c50e3 | 985 | pr_debug("CPB unsupported, do not expose it\n"); |
11269ff5 | 986 | |
f56c50e3 RW |
987 | for (attr = acpi_cpufreq_attr; *attr; attr++) |
988 | if (*attr == &cpb) { | |
989 | *attr = NULL; | |
990 | break; | |
991 | } | |
11269ff5 AP |
992 | } |
993 | #endif | |
cfc9c8ed | 994 | acpi_cpufreq_boost_init(); |
11269ff5 | 995 | |
847aef6f | 996 | ret = cpufreq_register_driver(&acpi_cpufreq_driver); |
eb8c68ef | 997 | if (ret) { |
2fdf66b4 | 998 | free_acpi_perf_data(); |
eb8c68ef KRW |
999 | acpi_cpufreq_boost_exit(); |
1000 | } | |
847aef6f | 1001 | return ret; |
1da177e4 LT |
1002 | } |
1003 | ||
64be7eed | 1004 | static void __exit acpi_cpufreq_exit(void) |
1da177e4 | 1005 | { |
2d06d8c4 | 1006 | pr_debug("acpi_cpufreq_exit\n"); |
1da177e4 | 1007 | |
615b7300 AP |
1008 | acpi_cpufreq_boost_exit(); |
1009 | ||
1da177e4 LT |
1010 | cpufreq_unregister_driver(&acpi_cpufreq_driver); |
1011 | ||
50f4ddd4 | 1012 | free_acpi_perf_data(); |
1da177e4 LT |
1013 | } |
1014 | ||
d395bf12 | 1015 | module_param(acpi_pstate_strict, uint, 0644); |
64be7eed | 1016 | MODULE_PARM_DESC(acpi_pstate_strict, |
95dd7227 DJ |
1017 | "value 0 or non-zero. non-zero -> strict ACPI checks are " |
1018 | "performed during frequency changes."); | |
1da177e4 LT |
1019 | |
1020 | late_initcall(acpi_cpufreq_init); | |
1021 | module_exit(acpi_cpufreq_exit); | |
1022 | ||
efa17194 MG |
1023 | static const struct x86_cpu_id acpi_cpufreq_ids[] = { |
1024 | X86_FEATURE_MATCH(X86_FEATURE_ACPI), | |
1025 | X86_FEATURE_MATCH(X86_FEATURE_HW_PSTATE), | |
1026 | {} | |
1027 | }; | |
1028 | MODULE_DEVICE_TABLE(x86cpu, acpi_cpufreq_ids); | |
1029 | ||
c655affb RW |
1030 | static const struct acpi_device_id processor_device_ids[] = { |
1031 | {ACPI_PROCESSOR_OBJECT_HID, }, | |
1032 | {ACPI_PROCESSOR_DEVICE_HID, }, | |
1033 | {}, | |
1034 | }; | |
1035 | MODULE_DEVICE_TABLE(acpi, processor_device_ids); | |
1036 | ||
1da177e4 | 1037 | MODULE_ALIAS("acpi"); |