[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / cpufreq-cpu0.c

/*
 * Copyright (C) 2012 Freescale Semiconductor, Inc.
 *
 * Copyright (C) 2014 Linaro.
 * Viresh Kumar <viresh.kumar@linaro.org>
 *
 * The OPP code in function cpu0_set_target() is reused from
 * drivers/cpufreq/omap-cpufreq.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/cpu_cooling.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/thermal.h>

struct private_data {
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct thermal_cooling_device *cdev;
	unsigned int voltage_tolerance; /* in percentage */
};

static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
{
	struct dev_pm_opp *opp;
	struct cpufreq_frequency_table *freq_table = policy->freq_table;
	struct clk *cpu_clk = policy->clk;
	struct private_data *priv = policy->driver_data;
	struct device *cpu_dev = priv->cpu_dev;
	struct regulator *cpu_reg = priv->cpu_reg;
	unsigned long volt = 0, volt_old = 0, tol = 0;
	unsigned int old_freq, new_freq;
	long freq_Hz, freq_exact;
	int ret;

	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
	if (freq_Hz <= 0)
		freq_Hz = freq_table[index].frequency * 1000;

	freq_exact = freq_Hz;
	new_freq = freq_Hz / 1000;
	old_freq = clk_get_rate(cpu_clk) / 1000;

	if (!IS_ERR(cpu_reg)) {
		rcu_read_lock();
		opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
		if (IS_ERR(opp)) {
			rcu_read_unlock();
			dev_err(cpu_dev, "failed to find OPP for %ld\n",
				freq_Hz);
			return PTR_ERR(opp);
		}
		volt = dev_pm_opp_get_voltage(opp);
		rcu_read_unlock();
		tol = volt * priv->voltage_tolerance / 100;
		volt_old = regulator_get_voltage(cpu_reg);
	}

	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
		old_freq / 1000, volt_old ? volt_old / 1000 : -1,
		new_freq / 1000, volt ? volt / 1000 : -1);

	/* scaling up?  scale voltage before frequency */
	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			dev_err(cpu_dev, "failed to scale voltage up: %d\n",
				ret);
			return ret;
		}
	}

	ret = clk_set_rate(cpu_clk, freq_exact);
	if (ret) {
		dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
		if (!IS_ERR(cpu_reg))
			regulator_set_voltage_tol(cpu_reg, volt_old, tol);
		return ret;
	}

	/* scaling down?  scale voltage after frequency */
	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
		ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
		if (ret) {
			dev_err(cpu_dev, "failed to scale voltage down: %d\n",
				ret);
			clk_set_rate(cpu_clk, old_freq * 1000);
		}
	}

	return ret;
}

static int allocate_resources(struct device **cdev,
			      struct regulator **creg, struct clk **cclk)
{
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	int ret = 0;
	char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;

	cpu_dev = get_cpu_device(0);
	if (!cpu_dev) {
		pr_err("failed to get cpu0 device\n");
		return -ENODEV;
	}

	/* Try "cpu0" for older DTs */
	reg = reg_cpu0;

try_again:
	cpu_reg = regulator_get_optional(cpu_dev, reg);
	if (IS_ERR(cpu_reg)) {
		/*
		 * If cpu0 regulator supply node is present, but regulator is
		 * not yet registered, we should try defering probe.
		 */
		if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
			dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
			return -EPROBE_DEFER;
		}

		/* Try with "cpu-supply" */
		if (reg == reg_cpu0) {
			reg = reg_cpu;
			goto try_again;
		}

		dev_warn(cpu_dev, "failed to get cpu0 regulator: %ld\n",
			 PTR_ERR(cpu_reg));
	}

	cpu_clk = clk_get(cpu_dev, NULL);
	if (IS_ERR(cpu_clk)) {
		/* put regulator */
		if (!IS_ERR(cpu_reg))
			regulator_put(cpu_reg);

		ret = PTR_ERR(cpu_clk);

		/*
		 * If cpu's clk node is present, but clock is not yet
		 * registered, we should try defering probe.
		 */
		if (ret == -EPROBE_DEFER)
			dev_dbg(cpu_dev, "cpu0 clock not ready, retry\n");
		else
			dev_err(cpu_dev, "failed to get cpu0 clock: %d\n", ret);
	} else {
		*cdev = cpu_dev;
		*creg = cpu_reg;
		*cclk = cpu_clk;
	}

	return ret;
}

static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
{
	struct cpufreq_frequency_table *freq_table;
	struct thermal_cooling_device *cdev;
	struct device_node *np;
	struct private_data *priv;
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	unsigned int transition_latency;
	int ret;

	/* We only support cpu0 currently */
	ret = allocate_resources(&cpu_dev, &cpu_reg, &cpu_clk);
	if (ret) {
		pr_err("%s: Failed to allocate resources\n: %d", __func__, ret);
		return ret;
	}

	np = of_node_get(cpu_dev->of_node);
	if (!np) {
		dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
		ret = -ENOENT;
		goto out_put_reg_clk;
	}

	/* OPPs might be populated at runtime, don't check for error here */
	of_init_opp_table(cpu_dev);

	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
	if (ret) {
		dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
		goto out_put_node;
	}

	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv) {
		ret = -ENOMEM;
		goto out_free_table;
	}

	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);

	if (of_property_read_u32(np, "clock-latency", &transition_latency))
		transition_latency = CPUFREQ_ETERNAL;

	if (!IS_ERR(cpu_reg)) {
		struct dev_pm_opp *opp;
		unsigned long min_uV, max_uV;
		int i;

		/*
		 * OPP is maintained in order of increasing frequency, and
		 * freq_table initialised from OPP is therefore sorted in the
		 * same order.
		 */
		for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
			;
		rcu_read_lock();
		opp = dev_pm_opp_find_freq_exact(cpu_dev,
				freq_table[0].frequency * 1000, true);
		min_uV = dev_pm_opp_get_voltage(opp);
		opp = dev_pm_opp_find_freq_exact(cpu_dev,
				freq_table[i-1].frequency * 1000, true);
		max_uV = dev_pm_opp_get_voltage(opp);
		rcu_read_unlock();
		ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
		if (ret > 0)
			transition_latency += ret * 1000;
	}

	/*
	 * For now, just loading the cooling device;
	 * thermal DT code takes care of matching them.
	 */
	if (of_find_property(np, "#cooling-cells", NULL)) {
		cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
		if (IS_ERR(cdev))
			dev_err(cpu_dev,
				"running cpufreq without cooling device: %ld\n",
				PTR_ERR(cdev));
		else
			priv->cdev = cdev;
	}
	of_node_put(np);

	priv->cpu_dev = cpu_dev;
	priv->cpu_reg = cpu_reg;
	policy->driver_data = priv;

	policy->clk = cpu_clk;
	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	if (ret)
		goto out_cooling_unregister;

	return 0;

out_cooling_unregister:
	cpufreq_cooling_unregister(priv->cdev);
	kfree(priv);
out_free_table:
	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
out_put_node:
	of_node_put(np);
out_put_reg_clk:
	clk_put(cpu_clk);
	if (!IS_ERR(cpu_reg))
		regulator_put(cpu_reg);

	return ret;
}

static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
{
	struct private_data *priv = policy->driver_data;

	cpufreq_cooling_unregister(priv->cdev);
	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
	clk_put(policy->clk);
	if (!IS_ERR(priv->cpu_reg))
		regulator_put(priv->cpu_reg);
	kfree(priv);

	return 0;
}

static struct cpufreq_driver cpu0_cpufreq_driver = {
	.flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	.verify = cpufreq_generic_frequency_table_verify,
	.target_index = cpu0_set_target,
	.get = cpufreq_generic_get,
	.init = cpu0_cpufreq_init,
	.exit = cpu0_cpufreq_exit,
	.name = "generic_cpu0",
	.attr = cpufreq_generic_attr,
};

static int cpu0_cpufreq_probe(struct platform_device *pdev)
{
	struct device *cpu_dev;
	struct regulator *cpu_reg;
	struct clk *cpu_clk;
	int ret;

	/*
	 * All per-cluster (CPUs sharing clock/voltages) initialization is done
	 * from ->init(). In probe(), we just need to make sure that clk and
	 * regulators are available. Else defer probe and retry.
	 *
	 * FIXME: Is checking this only for CPU0 sufficient ?
	 */
	ret = allocate_resources(&cpu_dev, &cpu_reg, &cpu_clk);
	if (ret)
		return ret;

	clk_put(cpu_clk);
	if (!IS_ERR(cpu_reg))
		regulator_put(cpu_reg);

	ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
	if (ret)
		dev_err(cpu_dev, "failed register driver: %d\n", ret);

	return ret;
}

static int cpu0_cpufreq_remove(struct platform_device *pdev)
{
	cpufreq_unregister_driver(&cpu0_cpufreq_driver);
	return 0;
}

static struct platform_driver cpu0_cpufreq_platdrv = {
	.driver = {
		.name	= "cpufreq-cpu0",
		.owner	= THIS_MODULE,
	},
	.probe		= cpu0_cpufreq_probe,
	.remove		= cpu0_cpufreq_remove,
};
module_platform_driver(cpu0_cpufreq_platdrv);

MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
95ceafd4 SG	1	/*
	2	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	*
748c8766 VK	4	* Copyright (C) 2014 Linaro.
	5	* Viresh Kumar <viresh.kumar@linaro.org>
	6	*
95ceafd4 SG	7	* The OPP code in function cpu0_set_target() is reused from
	8	* drivers/cpufreq/omap-cpufreq.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	16
	17	#include <linux/clk.h>
e1825b25	18	#include <linux/cpu.h>
77cff592	19	#include <linux/cpu_cooling.h>
95ceafd4	20	#include <linux/cpufreq.h>
77cff592	21	#include <linux/cpumask.h>
95ceafd4 SG	22	#include <linux/err.h>
	23	#include <linux/module.h>
	24	#include <linux/of.h>
e4db1c74	25	#include <linux/pm_opp.h>
5553f9e2	26	#include <linux/platform_device.h>
95ceafd4 SG	27	#include <linux/regulator/consumer.h>
95ceafd4 SG	28	#include <linux/slab.h>
77cff592	29	#include <linux/thermal.h>
95ceafd4	30
d2f31f1d VK	31	struct private_data {
	32	struct device *cpu_dev;
	33	struct regulator *cpu_reg;
	34	struct thermal_cooling_device *cdev;
	35	unsigned int voltage_tolerance; /* in percentage */
	36	};
95ceafd4	37
9c0ebcf7	38	static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4	39	{
47d43ba7	40	struct dev_pm_opp *opp;
d2f31f1d VK	41	struct cpufreq_frequency_table *freq_table = policy->freq_table;
	42	struct clk *cpu_clk = policy->clk;
	43	struct private_data *priv = policy->driver_data;
	44	struct device *cpu_dev = priv->cpu_dev;
	45	struct regulator *cpu_reg = priv->cpu_reg;
5df60559	46	unsigned long volt = 0, volt_old = 0, tol = 0;
d4019f0a	47	unsigned int old_freq, new_freq;
0ca68436	48	long freq_Hz, freq_exact;
95ceafd4 SG	49	int ret;
95ceafd4 SG	50
95ceafd4	51	freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9	52	if (freq_Hz <= 0)
95ceafd4	53	freq_Hz = freq_table[index].frequency * 1000;
95ceafd4	54
d4019f0a VK	55	freq_exact = freq_Hz;
	56	new_freq = freq_Hz / 1000;
	57	old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4	58
4a511de9	59	if (!IS_ERR(cpu_reg)) {
78e8eb8f	60	rcu_read_lock();
5d4879cd	61	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4	62	if (IS_ERR(opp)) {
78e8eb8f	63	rcu_read_unlock();
fbd48ca5 VK	64	dev_err(cpu_dev, "failed to find OPP for %ld\n",
fbd48ca5 VK	65	freq_Hz);
d4019f0a	66	return PTR_ERR(opp);
95ceafd4	67	}
5d4879cd	68	volt = dev_pm_opp_get_voltage(opp);
78e8eb8f	69	rcu_read_unlock();
d2f31f1d	70	tol = volt * priv->voltage_tolerance / 100;
95ceafd4 SG	71	volt_old = regulator_get_voltage(cpu_reg);
	72	}
	73
fbd48ca5 VK	74	dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
	75	old_freq / 1000, volt_old ? volt_old / 1000 : -1,
	76	new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4 SG	77
95ceafd4 SG	78	/* scaling up? scale voltage before frequency */
d4019f0a	79	if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4 SG	80	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95ceafd4 SG	81	if (ret) {
fbd48ca5 VK	82	dev_err(cpu_dev, "failed to scale voltage up: %d\n",
fbd48ca5 VK	83	ret);
d4019f0a	84	return ret;
95ceafd4 SG	85	}
	86	}
	87
0ca68436	88	ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4	89	if (ret) {
fbd48ca5	90	dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
4a511de9	91	if (!IS_ERR(cpu_reg))
95ceafd4	92	regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a	93	return ret;
95ceafd4 SG	94	}
	95
	96	/* scaling down? scale voltage after frequency */
d4019f0a	97	if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
95ceafd4 SG	98	ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95ceafd4 SG	99	if (ret) {
fbd48ca5 VK	100	dev_err(cpu_dev, "failed to scale voltage down: %d\n",
fbd48ca5 VK	101	ret);
d4019f0a	102	clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4 SG	103	}
	104	}
	105
fd143b4d	106	return ret;
95ceafd4 SG	107	}
95ceafd4 SG	108
d2f31f1d VK	109	static int allocate_resources(struct device **cdev,
d2f31f1d VK	110	struct regulator creg, struct clk cclk)
95ceafd4	111	{
d2f31f1d VK	112	struct device *cpu_dev;
	113	struct regulator *cpu_reg;
	114	struct clk *cpu_clk;
	115	int ret = 0;
2d2c5e0e	116	char reg_cpu0 = "cpu0", reg_cpu = "cpu", *reg;
95ceafd4	117
e1825b25 SH	118	cpu_dev = get_cpu_device(0);
	119	if (!cpu_dev) {
	120	pr_err("failed to get cpu0 device\n");
	121	return -ENODEV;
	122	}
6754f556	123
2d2c5e0e VK	124	/* Try "cpu0" for older DTs */
	125	reg = reg_cpu0;
	126
	127	try_again:
	128	cpu_reg = regulator_get_optional(cpu_dev, reg);
fc31d6f5 NM	129	if (IS_ERR(cpu_reg)) {
	130	/*
	131	* If cpu0 regulator supply node is present, but regulator is
	132	* not yet registered, we should try defering probe.
	133	*/
	134	if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
713a3fa6	135	dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n");
d2f31f1d	136	return -EPROBE_DEFER;
fc31d6f5	137	}
2d2c5e0e VK	138
	139	/* Try with "cpu-supply" */
	140	if (reg == reg_cpu0) {
	141	reg = reg_cpu;
	142	goto try_again;
	143	}
	144
fbd48ca5 VK	145	dev_warn(cpu_dev, "failed to get cpu0 regulator: %ld\n",
fbd48ca5 VK	146	PTR_ERR(cpu_reg));
fc31d6f5 NM	147	}
fc31d6f5 NM	148
e3beb0ac	149	cpu_clk = clk_get(cpu_dev, NULL);
95ceafd4	150	if (IS_ERR(cpu_clk)) {
d2f31f1d VK	151	/* put regulator */
	152	if (!IS_ERR(cpu_reg))
	153	regulator_put(cpu_reg);
	154
95ceafd4	155	ret = PTR_ERR(cpu_clk);
48a8624b VK	156
	157	/*
	158	* If cpu's clk node is present, but clock is not yet
	159	* registered, we should try defering probe.
	160	*/
	161	if (ret == -EPROBE_DEFER)
	162	dev_dbg(cpu_dev, "cpu0 clock not ready, retry\n");
	163	else
	164	dev_err(cpu_dev, "failed to get cpu0 clock: %d\n", ret);
d2f31f1d VK	165	} else {
	166	*cdev = cpu_dev;
	167	*creg = cpu_reg;
	168	*cclk = cpu_clk;
	169	}
	170
	171	return ret;
	172	}
	173
	174	static int cpu0_cpufreq_init(struct cpufreq_policy *policy)
	175	{
	176	struct cpufreq_frequency_table *freq_table;
	177	struct thermal_cooling_device *cdev;
	178	struct device_node *np;
	179	struct private_data *priv;
	180	struct device *cpu_dev;
	181	struct regulator *cpu_reg;
	182	struct clk *cpu_clk;
	183	unsigned int transition_latency;
	184	int ret;
	185
	186	/* We only support cpu0 currently */
	187	ret = allocate_resources(&cpu_dev, &cpu_reg, &cpu_clk);
	188	if (ret) {
	189	pr_err("%s: Failed to allocate resources\n: %d", __func__, ret);
	190	return ret;
	191	}
48a8624b	192
d2f31f1d VK	193	np = of_node_get(cpu_dev->of_node);
	194	if (!np) {
	195	dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
	196	ret = -ENOENT;
	197	goto out_put_reg_clk;
95ceafd4 SG	198	}
95ceafd4 SG	199
1bf8cc3d VK	200	/* OPPs might be populated at runtime, don't check for error here */
1bf8cc3d VK	201	of_init_opp_table(cpu_dev);
95ceafd4	202
5d4879cd	203	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
95ceafd4	204	if (ret) {
fbd48ca5	205	dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
d2f31f1d VK	206	goto out_put_node;
	207	}
	208
	209	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
	210	if (!priv) {
	211	ret = -ENOMEM;
	212	goto out_free_table;
95ceafd4 SG	213	}
95ceafd4 SG	214
d2f31f1d	215	of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
95ceafd4 SG	216
	217	if (of_property_read_u32(np, "clock-latency", &transition_latency))
	218	transition_latency = CPUFREQ_ETERNAL;
	219
43c638e3	220	if (!IS_ERR(cpu_reg)) {
47d43ba7	221	struct dev_pm_opp *opp;
95ceafd4 SG	222	unsigned long min_uV, max_uV;
	223	int i;
	224
	225	/*
	226	* OPP is maintained in order of increasing frequency, and
	227	* freq_table initialised from OPP is therefore sorted in the
	228	* same order.
	229	*/
	230	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
	231	;
78e8eb8f	232	rcu_read_lock();
5d4879cd	233	opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4	234	freq_table[0].frequency * 1000, true);
5d4879cd NM	235	min_uV = dev_pm_opp_get_voltage(opp);
5d4879cd NM	236	opp = dev_pm_opp_find_freq_exact(cpu_dev,
95ceafd4	237	freq_table[i-1].frequency * 1000, true);
5d4879cd	238	max_uV = dev_pm_opp_get_voltage(opp);
78e8eb8f	239	rcu_read_unlock();
95ceafd4 SG	240	ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV);
	241	if (ret > 0)
	242	transition_latency += ret * 1000;
	243	}
	244
77cff592 EV	245	/*
	246	* For now, just loading the cooling device;
	247	* thermal DT code takes care of matching them.
	248	*/
	249	if (of_find_property(np, "#cooling-cells", NULL)) {
	250	cdev = of_cpufreq_cooling_register(np, cpu_present_mask);
	251	if (IS_ERR(cdev))
fbd48ca5 VK	252	dev_err(cpu_dev,
	253	"running cpufreq without cooling device: %ld\n",
	254	PTR_ERR(cdev));
d2f31f1d VK	255	else
d2f31f1d VK	256	priv->cdev = cdev;
77cff592	257	}
95ceafd4	258	of_node_put(np);
d2f31f1d VK	259
	260	priv->cpu_dev = cpu_dev;
	261	priv->cpu_reg = cpu_reg;
	262	policy->driver_data = priv;
	263
	264	policy->clk = cpu_clk;
	265	ret = cpufreq_generic_init(policy, freq_table, transition_latency);
	266	if (ret)
	267	goto out_cooling_unregister;
	268
95ceafd4 SG	269	return 0;
95ceafd4 SG	270
d2f31f1d VK	271	out_cooling_unregister:
	272	cpufreq_cooling_unregister(priv->cdev);
	273	kfree(priv);
95ceafd4	274	out_free_table:
5d4879cd	275	dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
d2f31f1d VK	276	out_put_node:
	277	of_node_put(np);
	278	out_put_reg_clk:
ed4b053c	279	clk_put(cpu_clk);
e3beb0ac LS	280	if (!IS_ERR(cpu_reg))
e3beb0ac LS	281	regulator_put(cpu_reg);
d2f31f1d VK	282
	283	return ret;
	284	}
	285
	286	static int cpu0_cpufreq_exit(struct cpufreq_policy *policy)
	287	{
	288	struct private_data *priv = policy->driver_data;
	289
	290	cpufreq_cooling_unregister(priv->cdev);
	291	dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
	292	clk_put(policy->clk);
	293	if (!IS_ERR(priv->cpu_reg))
	294	regulator_put(priv->cpu_reg);
	295	kfree(priv);
	296
	297	return 0;
	298	}
	299
	300	static struct cpufreq_driver cpu0_cpufreq_driver = {
	301	.flags = CPUFREQ_STICKY \| CPUFREQ_NEED_INITIAL_FREQ_CHECK,
	302	.verify = cpufreq_generic_frequency_table_verify,
	303	.target_index = cpu0_set_target,
	304	.get = cpufreq_generic_get,
	305	.init = cpu0_cpufreq_init,
	306	.exit = cpu0_cpufreq_exit,
	307	.name = "generic_cpu0",
	308	.attr = cpufreq_generic_attr,
	309	};
	310
	311	static int cpu0_cpufreq_probe(struct platform_device *pdev)
	312	{
	313	struct device *cpu_dev;
	314	struct regulator *cpu_reg;
	315	struct clk *cpu_clk;
	316	int ret;
	317
	318	/*
	319	* All per-cluster (CPUs sharing clock/voltages) initialization is done
	320	* from ->init(). In probe(), we just need to make sure that clk and
	321	* regulators are available. Else defer probe and retry.
	322	*
	323	* FIXME: Is checking this only for CPU0 sufficient ?
	324	*/
	325	ret = allocate_resources(&cpu_dev, &cpu_reg, &cpu_clk);
	326	if (ret)
	327	return ret;
	328
	329	clk_put(cpu_clk);
	330	if (!IS_ERR(cpu_reg))
	331	regulator_put(cpu_reg);
	332
	333	ret = cpufreq_register_driver(&cpu0_cpufreq_driver);
	334	if (ret)
	335	dev_err(cpu_dev, "failed register driver: %d\n", ret);
	336
95ceafd4 SG	337	return ret;
95ceafd4 SG	338	}
5553f9e2 SG	339
	340	static int cpu0_cpufreq_remove(struct platform_device *pdev)
	341	{
	342	cpufreq_unregister_driver(&cpu0_cpufreq_driver);
5553f9e2 SG	343	return 0;
	344	}
	345
	346	static struct platform_driver cpu0_cpufreq_platdrv = {
	347	.driver = {
	348	.name = "cpufreq-cpu0",
	349	.owner = THIS_MODULE,
	350	},
	351	.probe = cpu0_cpufreq_probe,
	352	.remove = cpu0_cpufreq_remove,
	353	};
	354	module_platform_driver(cpu0_cpufreq_platdrv);
95ceafd4	355
748c8766	356	MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
95ceafd4 SG	357	MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
	358	MODULE_DESCRIPTION("Generic CPU0 cpufreq driver");
	359	MODULE_LICENSE("GPL");