]>
Commit | Line | Data |
---|---|---|
95ceafd4 SG |
1 | /* |
2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
3 | * | |
748c8766 VK |
4 | * Copyright (C) 2014 Linaro. |
5 | * Viresh Kumar <viresh.kumar@linaro.org> | |
6 | * | |
95ceafd4 SG |
7 | * The OPP code in function cpu0_set_target() is reused from |
8 | * drivers/cpufreq/omap-cpufreq.c | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
16 | ||
17 | #include <linux/clk.h> | |
e1825b25 | 18 | #include <linux/cpu.h> |
77cff592 | 19 | #include <linux/cpu_cooling.h> |
95ceafd4 | 20 | #include <linux/cpufreq.h> |
77cff592 | 21 | #include <linux/cpumask.h> |
95ceafd4 SG |
22 | #include <linux/err.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/of.h> | |
e4db1c74 | 25 | #include <linux/pm_opp.h> |
5553f9e2 | 26 | #include <linux/platform_device.h> |
95ceafd4 SG |
27 | #include <linux/regulator/consumer.h> |
28 | #include <linux/slab.h> | |
77cff592 | 29 | #include <linux/thermal.h> |
95ceafd4 SG |
30 | |
31 | static unsigned int transition_latency; | |
32 | static unsigned int voltage_tolerance; /* in percentage */ | |
33 | ||
34 | static struct device *cpu_dev; | |
35 | static struct clk *cpu_clk; | |
36 | static struct regulator *cpu_reg; | |
37 | static struct cpufreq_frequency_table *freq_table; | |
77cff592 | 38 | static struct thermal_cooling_device *cdev; |
95ceafd4 | 39 | |
9c0ebcf7 | 40 | static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index) |
95ceafd4 | 41 | { |
47d43ba7 | 42 | struct dev_pm_opp *opp; |
5df60559 | 43 | unsigned long volt = 0, volt_old = 0, tol = 0; |
d4019f0a | 44 | unsigned int old_freq, new_freq; |
0ca68436 | 45 | long freq_Hz, freq_exact; |
95ceafd4 SG |
46 | int ret; |
47 | ||
95ceafd4 | 48 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); |
2209b0c9 | 49 | if (freq_Hz <= 0) |
95ceafd4 | 50 | freq_Hz = freq_table[index].frequency * 1000; |
95ceafd4 | 51 | |
d4019f0a VK |
52 | freq_exact = freq_Hz; |
53 | new_freq = freq_Hz / 1000; | |
54 | old_freq = clk_get_rate(cpu_clk) / 1000; | |
95ceafd4 | 55 | |
4a511de9 | 56 | if (!IS_ERR(cpu_reg)) { |
78e8eb8f | 57 | rcu_read_lock(); |
5d4879cd | 58 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); |
95ceafd4 | 59 | if (IS_ERR(opp)) { |
78e8eb8f | 60 | rcu_read_unlock(); |
95ceafd4 | 61 | pr_err("failed to find OPP for %ld\n", freq_Hz); |
d4019f0a | 62 | return PTR_ERR(opp); |
95ceafd4 | 63 | } |
5d4879cd | 64 | volt = dev_pm_opp_get_voltage(opp); |
78e8eb8f | 65 | rcu_read_unlock(); |
95ceafd4 SG |
66 | tol = volt * voltage_tolerance / 100; |
67 | volt_old = regulator_get_voltage(cpu_reg); | |
68 | } | |
69 | ||
70 | pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", | |
d4019f0a VK |
71 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
72 | new_freq / 1000, volt ? volt / 1000 : -1); | |
95ceafd4 SG |
73 | |
74 | /* scaling up? scale voltage before frequency */ | |
d4019f0a | 75 | if (!IS_ERR(cpu_reg) && new_freq > old_freq) { |
95ceafd4 SG |
76 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
77 | if (ret) { | |
78 | pr_err("failed to scale voltage up: %d\n", ret); | |
d4019f0a | 79 | return ret; |
95ceafd4 SG |
80 | } |
81 | } | |
82 | ||
0ca68436 | 83 | ret = clk_set_rate(cpu_clk, freq_exact); |
95ceafd4 SG |
84 | if (ret) { |
85 | pr_err("failed to set clock rate: %d\n", ret); | |
4a511de9 | 86 | if (!IS_ERR(cpu_reg)) |
95ceafd4 | 87 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); |
d4019f0a | 88 | return ret; |
95ceafd4 SG |
89 | } |
90 | ||
91 | /* scaling down? scale voltage after frequency */ | |
d4019f0a | 92 | if (!IS_ERR(cpu_reg) && new_freq < old_freq) { |
95ceafd4 SG |
93 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
94 | if (ret) { | |
95 | pr_err("failed to scale voltage down: %d\n", ret); | |
d4019f0a | 96 | clk_set_rate(cpu_clk, old_freq * 1000); |
95ceafd4 SG |
97 | } |
98 | } | |
99 | ||
fd143b4d | 100 | return ret; |
95ceafd4 SG |
101 | } |
102 | ||
103 | static int cpu0_cpufreq_init(struct cpufreq_policy *policy) | |
104 | { | |
652ed95d | 105 | policy->clk = cpu_clk; |
78b3d109 | 106 | return cpufreq_generic_init(policy, freq_table, transition_latency); |
95ceafd4 SG |
107 | } |
108 | ||
95ceafd4 | 109 | static struct cpufreq_driver cpu0_cpufreq_driver = { |
93575b75 | 110 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
f793d79f | 111 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 112 | .target_index = cpu0_set_target, |
652ed95d | 113 | .get = cpufreq_generic_get, |
95ceafd4 | 114 | .init = cpu0_cpufreq_init, |
95ceafd4 | 115 | .name = "generic_cpu0", |
f793d79f | 116 | .attr = cpufreq_generic_attr, |
95ceafd4 SG |
117 | }; |
118 | ||
5553f9e2 | 119 | static int cpu0_cpufreq_probe(struct platform_device *pdev) |
95ceafd4 | 120 | { |
f837a9b5 | 121 | struct device_node *np; |
95ceafd4 SG |
122 | int ret; |
123 | ||
e1825b25 SH |
124 | cpu_dev = get_cpu_device(0); |
125 | if (!cpu_dev) { | |
126 | pr_err("failed to get cpu0 device\n"); | |
127 | return -ENODEV; | |
128 | } | |
6754f556 | 129 | |
f837a9b5 | 130 | np = of_node_get(cpu_dev->of_node); |
95ceafd4 SG |
131 | if (!np) { |
132 | pr_err("failed to find cpu0 node\n"); | |
f837a9b5 | 133 | return -ENOENT; |
95ceafd4 SG |
134 | } |
135 | ||
e3beb0ac | 136 | cpu_reg = regulator_get_optional(cpu_dev, "cpu0"); |
fc31d6f5 NM |
137 | if (IS_ERR(cpu_reg)) { |
138 | /* | |
139 | * If cpu0 regulator supply node is present, but regulator is | |
140 | * not yet registered, we should try defering probe. | |
141 | */ | |
142 | if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) { | |
713a3fa6 | 143 | dev_dbg(cpu_dev, "cpu0 regulator not ready, retry\n"); |
fc31d6f5 NM |
144 | ret = -EPROBE_DEFER; |
145 | goto out_put_node; | |
146 | } | |
147 | pr_warn("failed to get cpu0 regulator: %ld\n", | |
148 | PTR_ERR(cpu_reg)); | |
fc31d6f5 NM |
149 | } |
150 | ||
e3beb0ac | 151 | cpu_clk = clk_get(cpu_dev, NULL); |
95ceafd4 SG |
152 | if (IS_ERR(cpu_clk)) { |
153 | ret = PTR_ERR(cpu_clk); | |
48a8624b VK |
154 | |
155 | /* | |
156 | * If cpu's clk node is present, but clock is not yet | |
157 | * registered, we should try defering probe. | |
158 | */ | |
159 | if (ret == -EPROBE_DEFER) | |
160 | dev_dbg(cpu_dev, "cpu0 clock not ready, retry\n"); | |
161 | else | |
162 | dev_err(cpu_dev, "failed to get cpu0 clock: %d\n", ret); | |
163 | ||
e3beb0ac | 164 | goto out_put_reg; |
95ceafd4 SG |
165 | } |
166 | ||
1bf8cc3d VK |
167 | /* OPPs might be populated at runtime, don't check for error here */ |
168 | of_init_opp_table(cpu_dev); | |
95ceafd4 | 169 | |
5d4879cd | 170 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
95ceafd4 SG |
171 | if (ret) { |
172 | pr_err("failed to init cpufreq table: %d\n", ret); | |
e3beb0ac | 173 | goto out_put_clk; |
95ceafd4 SG |
174 | } |
175 | ||
176 | of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); | |
177 | ||
178 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) | |
179 | transition_latency = CPUFREQ_ETERNAL; | |
180 | ||
43c638e3 | 181 | if (!IS_ERR(cpu_reg)) { |
47d43ba7 | 182 | struct dev_pm_opp *opp; |
95ceafd4 SG |
183 | unsigned long min_uV, max_uV; |
184 | int i; | |
185 | ||
186 | /* | |
187 | * OPP is maintained in order of increasing frequency, and | |
188 | * freq_table initialised from OPP is therefore sorted in the | |
189 | * same order. | |
190 | */ | |
191 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) | |
192 | ; | |
78e8eb8f | 193 | rcu_read_lock(); |
5d4879cd | 194 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
95ceafd4 | 195 | freq_table[0].frequency * 1000, true); |
5d4879cd NM |
196 | min_uV = dev_pm_opp_get_voltage(opp); |
197 | opp = dev_pm_opp_find_freq_exact(cpu_dev, | |
95ceafd4 | 198 | freq_table[i-1].frequency * 1000, true); |
5d4879cd | 199 | max_uV = dev_pm_opp_get_voltage(opp); |
78e8eb8f | 200 | rcu_read_unlock(); |
95ceafd4 SG |
201 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
202 | if (ret > 0) | |
203 | transition_latency += ret * 1000; | |
204 | } | |
205 | ||
206 | ret = cpufreq_register_driver(&cpu0_cpufreq_driver); | |
207 | if (ret) { | |
208 | pr_err("failed register driver: %d\n", ret); | |
209 | goto out_free_table; | |
210 | } | |
211 | ||
77cff592 EV |
212 | /* |
213 | * For now, just loading the cooling device; | |
214 | * thermal DT code takes care of matching them. | |
215 | */ | |
216 | if (of_find_property(np, "#cooling-cells", NULL)) { | |
217 | cdev = of_cpufreq_cooling_register(np, cpu_present_mask); | |
218 | if (IS_ERR(cdev)) | |
219 | pr_err("running cpufreq without cooling device: %ld\n", | |
220 | PTR_ERR(cdev)); | |
221 | } | |
222 | ||
95ceafd4 SG |
223 | of_node_put(np); |
224 | return 0; | |
225 | ||
226 | out_free_table: | |
5d4879cd | 227 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
e3beb0ac | 228 | out_put_clk: |
ed4b053c | 229 | clk_put(cpu_clk); |
e3beb0ac LS |
230 | out_put_reg: |
231 | if (!IS_ERR(cpu_reg)) | |
232 | regulator_put(cpu_reg); | |
95ceafd4 SG |
233 | out_put_node: |
234 | of_node_put(np); | |
235 | return ret; | |
236 | } | |
5553f9e2 SG |
237 | |
238 | static int cpu0_cpufreq_remove(struct platform_device *pdev) | |
239 | { | |
77cff592 | 240 | cpufreq_cooling_unregister(cdev); |
5553f9e2 | 241 | cpufreq_unregister_driver(&cpu0_cpufreq_driver); |
5d4879cd | 242 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
5553f9e2 SG |
243 | |
244 | return 0; | |
245 | } | |
246 | ||
247 | static struct platform_driver cpu0_cpufreq_platdrv = { | |
248 | .driver = { | |
249 | .name = "cpufreq-cpu0", | |
250 | .owner = THIS_MODULE, | |
251 | }, | |
252 | .probe = cpu0_cpufreq_probe, | |
253 | .remove = cpu0_cpufreq_remove, | |
254 | }; | |
255 | module_platform_driver(cpu0_cpufreq_platdrv); | |
95ceafd4 | 256 | |
748c8766 | 257 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>"); |
95ceafd4 SG |
258 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); |
259 | MODULE_DESCRIPTION("Generic CPU0 cpufreq driver"); | |
260 | MODULE_LICENSE("GPL"); |