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95ceafd4 SG |
1 | /* |
2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * The OPP code in function cpu0_set_target() is reused from | |
5 | * drivers/cpufreq/omap-cpufreq.c | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
13 | ||
14 | #include <linux/clk.h> | |
95ceafd4 SG |
15 | #include <linux/cpufreq.h> |
16 | #include <linux/err.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/opp.h> | |
5553f9e2 | 20 | #include <linux/platform_device.h> |
95ceafd4 SG |
21 | #include <linux/regulator/consumer.h> |
22 | #include <linux/slab.h> | |
23 | ||
24 | static unsigned int transition_latency; | |
25 | static unsigned int voltage_tolerance; /* in percentage */ | |
26 | ||
27 | static struct device *cpu_dev; | |
28 | static struct clk *cpu_clk; | |
29 | static struct regulator *cpu_reg; | |
30 | static struct cpufreq_frequency_table *freq_table; | |
31 | ||
32 | static int cpu0_verify_speed(struct cpufreq_policy *policy) | |
33 | { | |
34 | return cpufreq_frequency_table_verify(policy, freq_table); | |
35 | } | |
36 | ||
37 | static unsigned int cpu0_get_speed(unsigned int cpu) | |
38 | { | |
39 | return clk_get_rate(cpu_clk) / 1000; | |
40 | } | |
41 | ||
42 | static int cpu0_set_target(struct cpufreq_policy *policy, | |
43 | unsigned int target_freq, unsigned int relation) | |
44 | { | |
45 | struct cpufreq_freqs freqs; | |
46 | struct opp *opp; | |
5df60559 | 47 | unsigned long volt = 0, volt_old = 0, tol = 0; |
48 | long freq_Hz; | |
95ceafd4 SG |
49 | unsigned int index, cpu; |
50 | int ret; | |
51 | ||
52 | ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, | |
53 | relation, &index); | |
54 | if (ret) { | |
55 | pr_err("failed to match target freqency %d: %d\n", | |
56 | target_freq, ret); | |
57 | return ret; | |
58 | } | |
59 | ||
60 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); | |
61 | if (freq_Hz < 0) | |
62 | freq_Hz = freq_table[index].frequency * 1000; | |
63 | freqs.new = freq_Hz / 1000; | |
64 | freqs.old = clk_get_rate(cpu_clk) / 1000; | |
65 | ||
66 | if (freqs.old == freqs.new) | |
67 | return 0; | |
68 | ||
69 | for_each_online_cpu(cpu) { | |
70 | freqs.cpu = cpu; | |
71 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
72 | } | |
73 | ||
74 | if (cpu_reg) { | |
78e8eb8f | 75 | rcu_read_lock(); |
95ceafd4 SG |
76 | opp = opp_find_freq_ceil(cpu_dev, &freq_Hz); |
77 | if (IS_ERR(opp)) { | |
78e8eb8f | 78 | rcu_read_unlock(); |
95ceafd4 | 79 | pr_err("failed to find OPP for %ld\n", freq_Hz); |
fd143b4d VK |
80 | freqs.new = freqs.old; |
81 | ret = PTR_ERR(opp); | |
82 | goto post_notify; | |
95ceafd4 SG |
83 | } |
84 | volt = opp_get_voltage(opp); | |
78e8eb8f | 85 | rcu_read_unlock(); |
95ceafd4 SG |
86 | tol = volt * voltage_tolerance / 100; |
87 | volt_old = regulator_get_voltage(cpu_reg); | |
88 | } | |
89 | ||
90 | pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", | |
91 | freqs.old / 1000, volt_old ? volt_old / 1000 : -1, | |
92 | freqs.new / 1000, volt ? volt / 1000 : -1); | |
93 | ||
94 | /* scaling up? scale voltage before frequency */ | |
95 | if (cpu_reg && freqs.new > freqs.old) { | |
96 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); | |
97 | if (ret) { | |
98 | pr_err("failed to scale voltage up: %d\n", ret); | |
99 | freqs.new = freqs.old; | |
fd143b4d | 100 | goto post_notify; |
95ceafd4 SG |
101 | } |
102 | } | |
103 | ||
104 | ret = clk_set_rate(cpu_clk, freqs.new * 1000); | |
105 | if (ret) { | |
106 | pr_err("failed to set clock rate: %d\n", ret); | |
107 | if (cpu_reg) | |
108 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); | |
fd143b4d VK |
109 | freqs.new = freqs.old; |
110 | goto post_notify; | |
95ceafd4 SG |
111 | } |
112 | ||
113 | /* scaling down? scale voltage after frequency */ | |
114 | if (cpu_reg && freqs.new < freqs.old) { | |
115 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); | |
116 | if (ret) { | |
117 | pr_err("failed to scale voltage down: %d\n", ret); | |
118 | clk_set_rate(cpu_clk, freqs.old * 1000); | |
119 | freqs.new = freqs.old; | |
95ceafd4 SG |
120 | } |
121 | } | |
122 | ||
fd143b4d | 123 | post_notify: |
95ceafd4 SG |
124 | for_each_online_cpu(cpu) { |
125 | freqs.cpu = cpu; | |
126 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
127 | } | |
128 | ||
fd143b4d | 129 | return ret; |
95ceafd4 SG |
130 | } |
131 | ||
132 | static int cpu0_cpufreq_init(struct cpufreq_policy *policy) | |
133 | { | |
134 | int ret; | |
135 | ||
95ceafd4 SG |
136 | ret = cpufreq_frequency_table_cpuinfo(policy, freq_table); |
137 | if (ret) { | |
138 | pr_err("invalid frequency table: %d\n", ret); | |
139 | return ret; | |
140 | } | |
141 | ||
142 | policy->cpuinfo.transition_latency = transition_latency; | |
143 | policy->cur = clk_get_rate(cpu_clk) / 1000; | |
144 | ||
145 | /* | |
146 | * The driver only supports the SMP configuartion where all processors | |
147 | * share the clock and voltage and clock. Use cpufreq affected_cpus | |
148 | * interface to have all CPUs scaled together. | |
149 | */ | |
95ceafd4 SG |
150 | cpumask_setall(policy->cpus); |
151 | ||
152 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | static int cpu0_cpufreq_exit(struct cpufreq_policy *policy) | |
158 | { | |
159 | cpufreq_frequency_table_put_attr(policy->cpu); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | static struct freq_attr *cpu0_cpufreq_attr[] = { | |
165 | &cpufreq_freq_attr_scaling_available_freqs, | |
166 | NULL, | |
167 | }; | |
168 | ||
169 | static struct cpufreq_driver cpu0_cpufreq_driver = { | |
170 | .flags = CPUFREQ_STICKY, | |
171 | .verify = cpu0_verify_speed, | |
172 | .target = cpu0_set_target, | |
173 | .get = cpu0_get_speed, | |
174 | .init = cpu0_cpufreq_init, | |
175 | .exit = cpu0_cpufreq_exit, | |
176 | .name = "generic_cpu0", | |
177 | .attr = cpu0_cpufreq_attr, | |
178 | }; | |
179 | ||
5553f9e2 | 180 | static int cpu0_cpufreq_probe(struct platform_device *pdev) |
95ceafd4 SG |
181 | { |
182 | struct device_node *np; | |
183 | int ret; | |
184 | ||
6754f556 ML |
185 | for_each_child_of_node(of_find_node_by_path("/cpus"), np) { |
186 | if (of_get_property(np, "operating-points", NULL)) | |
187 | break; | |
188 | } | |
189 | ||
95ceafd4 SG |
190 | if (!np) { |
191 | pr_err("failed to find cpu0 node\n"); | |
192 | return -ENOENT; | |
193 | } | |
194 | ||
5553f9e2 | 195 | cpu_dev = &pdev->dev; |
95ceafd4 SG |
196 | cpu_dev->of_node = np; |
197 | ||
5553f9e2 | 198 | cpu_clk = devm_clk_get(cpu_dev, NULL); |
95ceafd4 SG |
199 | if (IS_ERR(cpu_clk)) { |
200 | ret = PTR_ERR(cpu_clk); | |
201 | pr_err("failed to get cpu0 clock: %d\n", ret); | |
202 | goto out_put_node; | |
203 | } | |
204 | ||
5553f9e2 | 205 | cpu_reg = devm_regulator_get(cpu_dev, "cpu0"); |
95ceafd4 SG |
206 | if (IS_ERR(cpu_reg)) { |
207 | pr_warn("failed to get cpu0 regulator\n"); | |
208 | cpu_reg = NULL; | |
209 | } | |
210 | ||
211 | ret = of_init_opp_table(cpu_dev); | |
212 | if (ret) { | |
213 | pr_err("failed to init OPP table: %d\n", ret); | |
214 | goto out_put_node; | |
215 | } | |
216 | ||
217 | ret = opp_init_cpufreq_table(cpu_dev, &freq_table); | |
218 | if (ret) { | |
219 | pr_err("failed to init cpufreq table: %d\n", ret); | |
220 | goto out_put_node; | |
221 | } | |
222 | ||
223 | of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); | |
224 | ||
225 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) | |
226 | transition_latency = CPUFREQ_ETERNAL; | |
227 | ||
228 | if (cpu_reg) { | |
229 | struct opp *opp; | |
230 | unsigned long min_uV, max_uV; | |
231 | int i; | |
232 | ||
233 | /* | |
234 | * OPP is maintained in order of increasing frequency, and | |
235 | * freq_table initialised from OPP is therefore sorted in the | |
236 | * same order. | |
237 | */ | |
238 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) | |
239 | ; | |
78e8eb8f | 240 | rcu_read_lock(); |
95ceafd4 SG |
241 | opp = opp_find_freq_exact(cpu_dev, |
242 | freq_table[0].frequency * 1000, true); | |
243 | min_uV = opp_get_voltage(opp); | |
244 | opp = opp_find_freq_exact(cpu_dev, | |
245 | freq_table[i-1].frequency * 1000, true); | |
246 | max_uV = opp_get_voltage(opp); | |
78e8eb8f | 247 | rcu_read_unlock(); |
95ceafd4 SG |
248 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
249 | if (ret > 0) | |
250 | transition_latency += ret * 1000; | |
251 | } | |
252 | ||
253 | ret = cpufreq_register_driver(&cpu0_cpufreq_driver); | |
254 | if (ret) { | |
255 | pr_err("failed register driver: %d\n", ret); | |
256 | goto out_free_table; | |
257 | } | |
258 | ||
259 | of_node_put(np); | |
260 | return 0; | |
261 | ||
262 | out_free_table: | |
263 | opp_free_cpufreq_table(cpu_dev, &freq_table); | |
264 | out_put_node: | |
265 | of_node_put(np); | |
266 | return ret; | |
267 | } | |
5553f9e2 SG |
268 | |
269 | static int cpu0_cpufreq_remove(struct platform_device *pdev) | |
270 | { | |
271 | cpufreq_unregister_driver(&cpu0_cpufreq_driver); | |
272 | opp_free_cpufreq_table(cpu_dev, &freq_table); | |
273 | ||
274 | return 0; | |
275 | } | |
276 | ||
277 | static struct platform_driver cpu0_cpufreq_platdrv = { | |
278 | .driver = { | |
279 | .name = "cpufreq-cpu0", | |
280 | .owner = THIS_MODULE, | |
281 | }, | |
282 | .probe = cpu0_cpufreq_probe, | |
283 | .remove = cpu0_cpufreq_remove, | |
284 | }; | |
285 | module_platform_driver(cpu0_cpufreq_platdrv); | |
95ceafd4 SG |
286 | |
287 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); | |
288 | MODULE_DESCRIPTION("Generic CPU0 cpufreq driver"); | |
289 | MODULE_LICENSE("GPL"); |