]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/cpufreq/cpufreq-dt.c
cpufreq: dt: Reuse dev_pm_opp_get_max_transition_latency()
[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / cpufreq-dt.c
CommitLineData
95ceafd4
SG
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
748c8766
VK
4 * Copyright (C) 2014 Linaro.
5 * Viresh Kumar <viresh.kumar@linaro.org>
6 *
bbcf0719 7 * The OPP code in function set_target() is reused from
95ceafd4
SG
8 * drivers/cpufreq/omap-cpufreq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
17#include <linux/clk.h>
e1825b25 18#include <linux/cpu.h>
77cff592 19#include <linux/cpu_cooling.h>
95ceafd4 20#include <linux/cpufreq.h>
34e5a527 21#include <linux/cpufreq-dt.h>
77cff592 22#include <linux/cpumask.h>
95ceafd4
SG
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/of.h>
e4db1c74 26#include <linux/pm_opp.h>
5553f9e2 27#include <linux/platform_device.h>
95ceafd4
SG
28#include <linux/regulator/consumer.h>
29#include <linux/slab.h>
77cff592 30#include <linux/thermal.h>
95ceafd4 31
d2f31f1d
VK
32struct private_data {
33 struct device *cpu_dev;
34 struct regulator *cpu_reg;
35 struct thermal_cooling_device *cdev;
36 unsigned int voltage_tolerance; /* in percentage */
050794aa 37 const char *reg_name;
d2f31f1d 38};
95ceafd4 39
21c36d35
BZ
40static struct freq_attr *cpufreq_dt_attr[] = {
41 &cpufreq_freq_attr_scaling_available_freqs,
42 NULL, /* Extra space for boost-attr if required */
43 NULL,
44};
45
bbcf0719 46static int set_target(struct cpufreq_policy *policy, unsigned int index)
95ceafd4 47{
47d43ba7 48 struct dev_pm_opp *opp;
d2f31f1d
VK
49 struct cpufreq_frequency_table *freq_table = policy->freq_table;
50 struct clk *cpu_clk = policy->clk;
51 struct private_data *priv = policy->driver_data;
52 struct device *cpu_dev = priv->cpu_dev;
53 struct regulator *cpu_reg = priv->cpu_reg;
929ca89c
AH
54 unsigned long volt = 0, tol = 0;
55 int volt_old = 0;
d4019f0a 56 unsigned int old_freq, new_freq;
0ca68436 57 long freq_Hz, freq_exact;
95ceafd4
SG
58 int ret;
59
95ceafd4 60 freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
2209b0c9 61 if (freq_Hz <= 0)
95ceafd4 62 freq_Hz = freq_table[index].frequency * 1000;
95ceafd4 63
d4019f0a
VK
64 freq_exact = freq_Hz;
65 new_freq = freq_Hz / 1000;
66 old_freq = clk_get_rate(cpu_clk) / 1000;
95ceafd4 67
4a511de9 68 if (!IS_ERR(cpu_reg)) {
0a1e879d
SW
69 unsigned long opp_freq;
70
78e8eb8f 71 rcu_read_lock();
5d4879cd 72 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz);
95ceafd4 73 if (IS_ERR(opp)) {
78e8eb8f 74 rcu_read_unlock();
fbd48ca5
VK
75 dev_err(cpu_dev, "failed to find OPP for %ld\n",
76 freq_Hz);
d4019f0a 77 return PTR_ERR(opp);
95ceafd4 78 }
5d4879cd 79 volt = dev_pm_opp_get_voltage(opp);
0a1e879d 80 opp_freq = dev_pm_opp_get_freq(opp);
78e8eb8f 81 rcu_read_unlock();
d2f31f1d 82 tol = volt * priv->voltage_tolerance / 100;
95ceafd4 83 volt_old = regulator_get_voltage(cpu_reg);
0a1e879d
SW
84 dev_dbg(cpu_dev, "Found OPP: %ld kHz, %ld uV\n",
85 opp_freq / 1000, volt);
95ceafd4
SG
86 }
87
929ca89c 88 dev_dbg(cpu_dev, "%u MHz, %d mV --> %u MHz, %ld mV\n",
8197bb1b 89 old_freq / 1000, (volt_old > 0) ? volt_old / 1000 : -1,
fbd48ca5 90 new_freq / 1000, volt ? volt / 1000 : -1);
95ceafd4
SG
91
92 /* scaling up? scale voltage before frequency */
d4019f0a 93 if (!IS_ERR(cpu_reg) && new_freq > old_freq) {
95ceafd4
SG
94 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
95 if (ret) {
fbd48ca5
VK
96 dev_err(cpu_dev, "failed to scale voltage up: %d\n",
97 ret);
d4019f0a 98 return ret;
95ceafd4
SG
99 }
100 }
101
0ca68436 102 ret = clk_set_rate(cpu_clk, freq_exact);
95ceafd4 103 if (ret) {
fbd48ca5 104 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
8197bb1b 105 if (!IS_ERR(cpu_reg) && volt_old > 0)
95ceafd4 106 regulator_set_voltage_tol(cpu_reg, volt_old, tol);
d4019f0a 107 return ret;
95ceafd4
SG
108 }
109
110 /* scaling down? scale voltage after frequency */
d4019f0a 111 if (!IS_ERR(cpu_reg) && new_freq < old_freq) {
95ceafd4
SG
112 ret = regulator_set_voltage_tol(cpu_reg, volt, tol);
113 if (ret) {
fbd48ca5
VK
114 dev_err(cpu_dev, "failed to scale voltage down: %d\n",
115 ret);
d4019f0a 116 clk_set_rate(cpu_clk, old_freq * 1000);
95ceafd4
SG
117 }
118 }
119
fd143b4d 120 return ret;
95ceafd4
SG
121}
122
050794aa
VK
123/*
124 * An earlier version of opp-v1 bindings used to name the regulator
125 * "cpu0-supply", we still need to handle that for backwards compatibility.
126 */
127static const char *find_supply_name(struct device *dev, struct device_node *np)
128{
129 struct property *pp;
130 int cpu = dev->id;
131
132 /* Try "cpu0" for older DTs */
133 if (!cpu) {
134 pp = of_find_property(np, "cpu0-supply", NULL);
135 if (pp)
136 return "cpu0";
137 }
138
139 pp = of_find_property(np, "cpu-supply", NULL);
140 if (pp)
141 return "cpu";
142
143 dev_dbg(dev, "no regulator for cpu%d\n", cpu);
144 return NULL;
145}
146
95b61058 147static int allocate_resources(int cpu, struct device **cdev,
d2f31f1d 148 struct regulator **creg, struct clk **cclk)
95ceafd4 149{
d2f31f1d
VK
150 struct device *cpu_dev;
151 struct regulator *cpu_reg;
152 struct clk *cpu_clk;
153 int ret = 0;
2d2c5e0e 154 char *reg_cpu0 = "cpu0", *reg_cpu = "cpu", *reg;
95ceafd4 155
95b61058 156 cpu_dev = get_cpu_device(cpu);
e1825b25 157 if (!cpu_dev) {
95b61058 158 pr_err("failed to get cpu%d device\n", cpu);
e1825b25
SH
159 return -ENODEV;
160 }
6754f556 161
2d2c5e0e 162 /* Try "cpu0" for older DTs */
95b61058
VK
163 if (!cpu)
164 reg = reg_cpu0;
165 else
166 reg = reg_cpu;
2d2c5e0e
VK
167
168try_again:
169 cpu_reg = regulator_get_optional(cpu_dev, reg);
b331bc20
AB
170 ret = PTR_ERR_OR_ZERO(cpu_reg);
171 if (ret) {
fc31d6f5 172 /*
95b61058 173 * If cpu's regulator supply node is present, but regulator is
fc31d6f5
NM
174 * not yet registered, we should try defering probe.
175 */
b331bc20 176 if (ret == -EPROBE_DEFER) {
95b61058
VK
177 dev_dbg(cpu_dev, "cpu%d regulator not ready, retry\n",
178 cpu);
b331bc20 179 return ret;
fc31d6f5 180 }
2d2c5e0e
VK
181
182 /* Try with "cpu-supply" */
183 if (reg == reg_cpu0) {
184 reg = reg_cpu;
185 goto try_again;
186 }
187
b331bc20 188 dev_dbg(cpu_dev, "no regulator for cpu%d: %d\n", cpu, ret);
fc31d6f5
NM
189 }
190
e3beb0ac 191 cpu_clk = clk_get(cpu_dev, NULL);
b331bc20
AB
192 ret = PTR_ERR_OR_ZERO(cpu_clk);
193 if (ret) {
d2f31f1d
VK
194 /* put regulator */
195 if (!IS_ERR(cpu_reg))
196 regulator_put(cpu_reg);
197
48a8624b
VK
198 /*
199 * If cpu's clk node is present, but clock is not yet
200 * registered, we should try defering probe.
201 */
202 if (ret == -EPROBE_DEFER)
95b61058 203 dev_dbg(cpu_dev, "cpu%d clock not ready, retry\n", cpu);
48a8624b 204 else
71796210
AK
205 dev_err(cpu_dev, "failed to get cpu%d clock: %d\n", cpu,
206 ret);
d2f31f1d
VK
207 } else {
208 *cdev = cpu_dev;
209 *creg = cpu_reg;
210 *cclk = cpu_clk;
211 }
212
213 return ret;
214}
215
bbcf0719 216static int cpufreq_init(struct cpufreq_policy *policy)
d2f31f1d
VK
217{
218 struct cpufreq_frequency_table *freq_table;
d2f31f1d
VK
219 struct device_node *np;
220 struct private_data *priv;
221 struct device *cpu_dev;
222 struct regulator *cpu_reg;
223 struct clk *cpu_clk;
953ba9ff 224 struct dev_pm_opp *suspend_opp;
d2f31f1d 225 unsigned int transition_latency;
457e99e6 226 bool opp_v1 = false;
050794aa 227 const char *name;
d2f31f1d
VK
228 int ret;
229
95b61058 230 ret = allocate_resources(policy->cpu, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d 231 if (ret) {
edd52b1c 232 pr_err("%s: Failed to allocate resources: %d\n", __func__, ret);
d2f31f1d
VK
233 return ret;
234 }
48a8624b 235
d2f31f1d
VK
236 np = of_node_get(cpu_dev->of_node);
237 if (!np) {
238 dev_err(cpu_dev, "failed to find cpu%d node\n", policy->cpu);
239 ret = -ENOENT;
240 goto out_put_reg_clk;
95ceafd4
SG
241 }
242
2e02d872 243 /* Get OPP-sharing information from "operating-points-v2" bindings */
8f8d37b2 244 ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, policy->cpus);
2e02d872
VK
245 if (ret) {
246 /*
247 * operating-points-v2 not supported, fallback to old method of
248 * finding shared-OPPs for backward compatibility.
249 */
250 if (ret == -ENOENT)
457e99e6 251 opp_v1 = true;
2e02d872
VK
252 else
253 goto out_node_put;
254 }
255
050794aa
VK
256 /*
257 * OPP layer will be taking care of regulators now, but it needs to know
258 * the name of the regulator first.
259 */
260 name = find_supply_name(cpu_dev, np);
261 if (name) {
262 ret = dev_pm_opp_set_regulator(cpu_dev, name);
263 if (ret) {
264 dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",
265 policy->cpu, ret);
266 goto out_node_put;
267 }
268 }
269
2e02d872
VK
270 /*
271 * Initialize OPP tables for all policy->cpus. They will be shared by
272 * all CPUs which have marked their CPUs shared with OPP bindings.
273 *
274 * For platforms not using operating-points-v2 bindings, we do this
275 * before updating policy->cpus. Otherwise, we will end up creating
276 * duplicate OPPs for policy->cpus.
277 *
278 * OPPs might be populated at runtime, don't check for error here
279 */
8f8d37b2 280 dev_pm_opp_of_cpumask_add_table(policy->cpus);
2e02d872 281
7d5d0c8b
VK
282 /*
283 * But we need OPP table to function so if it is not there let's
284 * give platform code chance to provide it for us.
285 */
286 ret = dev_pm_opp_get_opp_count(cpu_dev);
287 if (ret <= 0) {
896d6a4c 288 dev_dbg(cpu_dev, "OPP table is not ready, deferring probe\n");
7d5d0c8b
VK
289 ret = -EPROBE_DEFER;
290 goto out_free_opp;
291 }
292
457e99e6 293 if (opp_v1) {
2e02d872
VK
294 struct cpufreq_dt_platform_data *pd = cpufreq_get_driver_data();
295
296 if (!pd || !pd->independent_clocks)
297 cpumask_setall(policy->cpus);
298
299 /*
300 * OPP tables are initialized only for policy->cpu, do it for
301 * others as well.
302 */
8f8d37b2 303 ret = dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
8bc86284
VK
304 if (ret)
305 dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
306 __func__, ret);
2e02d872 307 }
95ceafd4 308
d2f31f1d
VK
309 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
310 if (!priv) {
311 ret = -ENOMEM;
2f0f609f 312 goto out_free_opp;
95ceafd4
SG
313 }
314
050794aa 315 priv->reg_name = name;
d2f31f1d 316 of_property_read_u32(np, "voltage-tolerance", &priv->voltage_tolerance);
95ceafd4 317
045ee45c
LS
318 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
319 if (ret) {
896d6a4c 320 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
045ee45c
LS
321 goto out_free_priv;
322 }
323
d2f31f1d
VK
324 priv->cpu_dev = cpu_dev;
325 priv->cpu_reg = cpu_reg;
326 policy->driver_data = priv;
327
328 policy->clk = cpu_clk;
953ba9ff
BZ
329
330 rcu_read_lock();
331 suspend_opp = dev_pm_opp_get_suspend_opp(cpu_dev);
332 if (suspend_opp)
333 policy->suspend_freq = dev_pm_opp_get_freq(suspend_opp) / 1000;
334 rcu_read_unlock();
335
34e5a527
TP
336 ret = cpufreq_table_validate_and_show(policy, freq_table);
337 if (ret) {
338 dev_err(cpu_dev, "%s: invalid frequency table: %d\n", __func__,
339 ret);
9a004428 340 goto out_free_cpufreq_table;
d15fa862
VK
341 }
342
343 /* Support turbo/boost mode */
344 if (policy_has_boost_freq(policy)) {
345 /* This gets disabled by core on driver unregister */
346 ret = cpufreq_enable_boost_support();
347 if (ret)
348 goto out_free_cpufreq_table;
21c36d35 349 cpufreq_dt_attr[1] = &cpufreq_freq_attr_scaling_boost_freqs;
34e5a527
TP
350 }
351
755b888f
VK
352 transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);
353 if (!transition_latency)
354 transition_latency = CPUFREQ_ETERNAL;
355
34e5a527
TP
356 policy->cpuinfo.transition_latency = transition_latency;
357
f9739d27
LS
358 of_node_put(np);
359
95ceafd4
SG
360 return 0;
361
9a004428 362out_free_cpufreq_table:
5d4879cd 363 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
045ee45c
LS
364out_free_priv:
365 kfree(priv);
2f0f609f 366out_free_opp:
8f8d37b2 367 dev_pm_opp_of_cpumask_remove_table(policy->cpus);
050794aa
VK
368 if (name)
369 dev_pm_opp_put_regulator(cpu_dev);
2e02d872 370out_node_put:
d2f31f1d
VK
371 of_node_put(np);
372out_put_reg_clk:
ed4b053c 373 clk_put(cpu_clk);
e3beb0ac
LS
374 if (!IS_ERR(cpu_reg))
375 regulator_put(cpu_reg);
d2f31f1d
VK
376
377 return ret;
378}
379
bbcf0719 380static int cpufreq_exit(struct cpufreq_policy *policy)
d2f31f1d
VK
381{
382 struct private_data *priv = policy->driver_data;
383
17ad13ba 384 cpufreq_cooling_unregister(priv->cdev);
d2f31f1d 385 dev_pm_opp_free_cpufreq_table(priv->cpu_dev, &policy->freq_table);
8f8d37b2 386 dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
050794aa
VK
387 if (priv->reg_name)
388 dev_pm_opp_put_regulator(priv->cpu_dev);
389
d2f31f1d
VK
390 clk_put(policy->clk);
391 if (!IS_ERR(priv->cpu_reg))
392 regulator_put(priv->cpu_reg);
393 kfree(priv);
394
395 return 0;
396}
397
9a004428
VK
398static void cpufreq_ready(struct cpufreq_policy *policy)
399{
400 struct private_data *priv = policy->driver_data;
401 struct device_node *np = of_node_get(priv->cpu_dev->of_node);
402
403 if (WARN_ON(!np))
404 return;
405
406 /*
407 * For now, just loading the cooling device;
408 * thermal DT code takes care of matching them.
409 */
410 if (of_find_property(np, "#cooling-cells", NULL)) {
f8fa8ae0
PA
411 u32 power_coefficient = 0;
412
413 of_property_read_u32(np, "dynamic-power-coefficient",
414 &power_coefficient);
415
416 priv->cdev = of_cpufreq_power_cooling_register(np,
417 policy->related_cpus, power_coefficient, NULL);
9a004428
VK
418 if (IS_ERR(priv->cdev)) {
419 dev_err(priv->cpu_dev,
420 "running cpufreq without cooling device: %ld\n",
421 PTR_ERR(priv->cdev));
422
423 priv->cdev = NULL;
424 }
425 }
426
427 of_node_put(np);
428}
429
bbcf0719 430static struct cpufreq_driver dt_cpufreq_driver = {
d2f31f1d
VK
431 .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
432 .verify = cpufreq_generic_frequency_table_verify,
bbcf0719 433 .target_index = set_target,
d2f31f1d 434 .get = cpufreq_generic_get,
bbcf0719
VK
435 .init = cpufreq_init,
436 .exit = cpufreq_exit,
9a004428 437 .ready = cpufreq_ready,
bbcf0719 438 .name = "cpufreq-dt",
21c36d35 439 .attr = cpufreq_dt_attr,
953ba9ff 440 .suspend = cpufreq_generic_suspend,
d2f31f1d
VK
441};
442
bbcf0719 443static int dt_cpufreq_probe(struct platform_device *pdev)
d2f31f1d
VK
444{
445 struct device *cpu_dev;
446 struct regulator *cpu_reg;
447 struct clk *cpu_clk;
448 int ret;
449
450 /*
451 * All per-cluster (CPUs sharing clock/voltages) initialization is done
452 * from ->init(). In probe(), we just need to make sure that clk and
453 * regulators are available. Else defer probe and retry.
454 *
455 * FIXME: Is checking this only for CPU0 sufficient ?
456 */
95b61058 457 ret = allocate_resources(0, &cpu_dev, &cpu_reg, &cpu_clk);
d2f31f1d
VK
458 if (ret)
459 return ret;
460
461 clk_put(cpu_clk);
462 if (!IS_ERR(cpu_reg))
463 regulator_put(cpu_reg);
464
34e5a527
TP
465 dt_cpufreq_driver.driver_data = dev_get_platdata(&pdev->dev);
466
bbcf0719 467 ret = cpufreq_register_driver(&dt_cpufreq_driver);
d2f31f1d
VK
468 if (ret)
469 dev_err(cpu_dev, "failed register driver: %d\n", ret);
470
95ceafd4
SG
471 return ret;
472}
5553f9e2 473
bbcf0719 474static int dt_cpufreq_remove(struct platform_device *pdev)
5553f9e2 475{
bbcf0719 476 cpufreq_unregister_driver(&dt_cpufreq_driver);
5553f9e2
SG
477 return 0;
478}
479
bbcf0719 480static struct platform_driver dt_cpufreq_platdrv = {
5553f9e2 481 .driver = {
bbcf0719 482 .name = "cpufreq-dt",
5553f9e2 483 },
bbcf0719
VK
484 .probe = dt_cpufreq_probe,
485 .remove = dt_cpufreq_remove,
5553f9e2 486};
bbcf0719 487module_platform_driver(dt_cpufreq_platdrv);
95ceafd4 488
07949bf9 489MODULE_ALIAS("platform:cpufreq-dt");
748c8766 490MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
95ceafd4 491MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
bbcf0719 492MODULE_DESCRIPTION("Generic cpufreq driver");
95ceafd4 493MODULE_LICENSE("GPL");