[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / cris-artpec3-cpufreq.c

#include <linux/init.h>
#include <linux/module.h>
#include <linux/cpufreq.h>
#include <hwregs/reg_map.h>
#include <hwregs/reg_rdwr.h>
#include <hwregs/clkgen_defs.h>
#include <hwregs/ddr2_defs.h>

static int
cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
	void *data);

static struct notifier_block cris_sdram_freq_notifier_block = {
	.notifier_call = cris_sdram_freq_notifier
};

static struct cpufreq_frequency_table cris_freq_table[] = {
	{0, 0x01, 6000},
	{0, 0x02, 200000},
	{0, 0, CPUFREQ_TABLE_END},
};

static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
{
	reg_clkgen_rw_clk_ctrl clk_ctrl;
	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
	return clk_ctrl.pll ? 200000 : 6000;
}

static int cris_freq_target(struct cpufreq_policy *policy, unsigned int state)
{
	reg_clkgen_rw_clk_ctrl clk_ctrl;
	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);

	local_irq_disable();

	/* Even though we may be SMP they will share the same clock
	 * so all settings are made on CPU0. */
	if (cris_freq_table[state].frequency == 200000)
		clk_ctrl.pll = 1;
	else
		clk_ctrl.pll = 0;
	REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);

	local_irq_enable();

	return 0;
}

static int cris_freq_cpu_init(struct cpufreq_policy *policy)
{
	return cpufreq_generic_init(policy, cris_freq_table, 1000000);
}

static struct cpufreq_driver cris_freq_driver = {
	.get	= cris_freq_get_cpu_frequency,
	.verify	= cpufreq_generic_frequency_table_verify,
	.target_index = cris_freq_target,
	.init	= cris_freq_cpu_init,
	.name	= "cris_freq",
	.attr	= cpufreq_generic_attr,
};

static int __init cris_freq_init(void)
{
	int ret;
	ret = cpufreq_register_driver(&cris_freq_driver);
	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
		CPUFREQ_TRANSITION_NOTIFIER);
	return ret;
}

static int
cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
	void *data)
{
	int i;
	struct cpufreq_freqs *freqs = data;
	if (val == CPUFREQ_PRECHANGE) {
		reg_ddr2_rw_cfg cfg =
		  REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
		cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);

		if (freqs->new == 200000)
			for (i = 0; i < 50000; i++);
		REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
	}
	return 0;
}


module_init(cris_freq_init);
Commit	Line	Data
035e111f JN	1	#include <linux/init.h>
	2	#include <linux/module.h>
	3	#include <linux/cpufreq.h>
	4	#include <hwregs/reg_map.h>
	5	#include <hwregs/reg_rdwr.h>
	6	#include <hwregs/clkgen_defs.h>
	7	#include <hwregs/ddr2_defs.h>
	8
	9	static int
	10	cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
	11	void *data);
	12
	13	static struct notifier_block cris_sdram_freq_notifier_block = {
	14	.notifier_call = cris_sdram_freq_notifier
	15	};
	16
	17	static struct cpufreq_frequency_table cris_freq_table[] = {
7f4b0461 VK	18	{0, 0x01, 6000},
	19	{0, 0x02, 200000},
	20	{0, 0, CPUFREQ_TABLE_END},
035e111f JN	21	};
	22
	23	static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
	24	{
	25	reg_clkgen_rw_clk_ctrl clk_ctrl;
	26	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
	27	return clk_ctrl.pll ? 200000 : 6000;
	28	}
	29
9c0ebcf7	30	static int cris_freq_target(struct cpufreq_policy *policy, unsigned int state)
035e111f	31	{
035e111f JN	32	reg_clkgen_rw_clk_ctrl clk_ctrl;
	33	clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
	34
035e111f JN	35	local_irq_disable();
	36
	37	/* Even though we may be SMP they will share the same clock
	38	* so all settings are made on CPU0. */
	39	if (cris_freq_table[state].frequency == 200000)
	40	clk_ctrl.pll = 1;
	41	else
	42	clk_ctrl.pll = 0;
	43	REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
	44
	45	local_irq_enable();
	46
035e111f JN	47	return 0;
	48	}
	49
	50	static int cris_freq_cpu_init(struct cpufreq_policy *policy)
	51	{
1870e111	52	return cpufreq_generic_init(policy, cris_freq_table, 1000000);
035e111f JN	53	}
035e111f JN	54
035e111f JN	55	static struct cpufreq_driver cris_freq_driver = {
035e111f JN	56	.get = cris_freq_get_cpu_frequency,
361db10f	57	.verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7	58	.target_index = cris_freq_target,
035e111f	59	.init = cris_freq_cpu_init,
035e111f	60	.name = "cris_freq",
361db10f	61	.attr = cpufreq_generic_attr,
035e111f JN	62	};
	63
	64	static int __init cris_freq_init(void)
	65	{
	66	int ret;
	67	ret = cpufreq_register_driver(&cris_freq_driver);
	68	cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
	69	CPUFREQ_TRANSITION_NOTIFIER);
	70	return ret;
	71	}
	72
	73	static int
	74	cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
	75	void *data)
	76	{
	77	int i;
	78	struct cpufreq_freqs *freqs = data;
	79	if (val == CPUFREQ_PRECHANGE) {
	80	reg_ddr2_rw_cfg cfg =
	81	REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
	82	cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);
	83
	84	if (freqs->new == 200000)
	85	for (i = 0; i < 50000; i++);
	86	REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
	87	}
	88	return 0;
	89	}
	90
	91
	92	module_init(cris_freq_init);