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Commit | Line | Data |
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7c1a70e9 | 1 | /* |
7c1a70e9 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
5 | * License Terms: GNU General Public License v2 | |
7c1a70e9 MP |
6 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
7 | * Author: Martin Persson <martin.persson@stericsson.com> | |
8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> | |
9 | * | |
10 | */ | |
b4689444 | 11 | #include <linux/module.h> |
7c1a70e9 MP |
12 | #include <linux/kernel.h> |
13 | #include <linux/cpufreq.h> | |
14 | #include <linux/delay.h> | |
72b2fd5c | 15 | #include <linux/slab.h> |
b4689444 | 16 | #include <linux/platform_device.h> |
73180f85 | 17 | #include <linux/mfd/dbx500-prcmu.h> |
72b2fd5c | 18 | #include <mach/id.h> |
7c1a70e9 MP |
19 | |
20 | static struct cpufreq_frequency_table freq_table[] = { | |
21 | [0] = { | |
22 | .index = 0, | |
6283e328 | 23 | .frequency = 200000, |
7c1a70e9 MP |
24 | }, |
25 | [1] = { | |
26 | .index = 1, | |
c72fe851 | 27 | .frequency = 400000, |
7c1a70e9 MP |
28 | }, |
29 | [2] = { | |
30 | .index = 2, | |
c72fe851 | 31 | .frequency = 800000, |
7c1a70e9 MP |
32 | }, |
33 | [3] = { | |
6283e328 | 34 | /* Used for MAX_OPP, if available */ |
7c1a70e9 MP |
35 | .index = 3, |
36 | .frequency = CPUFREQ_TABLE_END, | |
37 | }, | |
6283e328 LW |
38 | [4] = { |
39 | .index = 4, | |
40 | .frequency = CPUFREQ_TABLE_END, | |
41 | }, | |
7c1a70e9 MP |
42 | }; |
43 | ||
72b2fd5c | 44 | static enum arm_opp idx2opp[] = { |
6283e328 | 45 | ARM_EXTCLK, |
72b2fd5c LW |
46 | ARM_50_OPP, |
47 | ARM_100_OPP, | |
48 | ARM_MAX_OPP | |
49 | }; | |
50 | ||
51 | static struct freq_attr *db8500_cpufreq_attr[] = { | |
52 | &cpufreq_freq_attr_scaling_available_freqs, | |
53 | NULL, | |
7c1a70e9 MP |
54 | }; |
55 | ||
72b2fd5c | 56 | static int db8500_cpufreq_verify_speed(struct cpufreq_policy *policy) |
7c1a70e9 MP |
57 | { |
58 | return cpufreq_frequency_table_verify(policy, freq_table); | |
59 | } | |
60 | ||
72b2fd5c | 61 | static int db8500_cpufreq_target(struct cpufreq_policy *policy, |
7c1a70e9 MP |
62 | unsigned int target_freq, |
63 | unsigned int relation) | |
64 | { | |
65 | struct cpufreq_freqs freqs; | |
72b2fd5c | 66 | unsigned int idx; |
7c1a70e9 | 67 | |
72b2fd5c | 68 | /* scale the target frequency to one of the extremes supported */ |
7c1a70e9 MP |
69 | if (target_freq < policy->cpuinfo.min_freq) |
70 | target_freq = policy->cpuinfo.min_freq; | |
71 | if (target_freq > policy->cpuinfo.max_freq) | |
72 | target_freq = policy->cpuinfo.max_freq; | |
73 | ||
72b2fd5c LW |
74 | /* Lookup the next frequency */ |
75 | if (cpufreq_frequency_table_target | |
76 | (policy, freq_table, target_freq, relation, &idx)) { | |
77 | return -EINVAL; | |
7c1a70e9 MP |
78 | } |
79 | ||
80 | freqs.old = policy->cur; | |
72b2fd5c | 81 | freqs.new = freq_table[idx].frequency; |
7c1a70e9 | 82 | |
72b2fd5c | 83 | if (freqs.old == freqs.new) |
7c1a70e9 | 84 | return 0; |
7c1a70e9 | 85 | |
72b2fd5c | 86 | /* pre-change notification */ |
8efd072b VG |
87 | for_each_cpu(freqs.cpu, policy->cpus) |
88 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
7c1a70e9 | 89 | |
72b2fd5c LW |
90 | /* request the PRCM unit for opp change */ |
91 | if (prcmu_set_arm_opp(idx2opp[idx])) { | |
92 | pr_err("db8500-cpufreq: Failed to set OPP level\n"); | |
93 | return -EINVAL; | |
7c1a70e9 MP |
94 | } |
95 | ||
72b2fd5c | 96 | /* post change notification */ |
8efd072b VG |
97 | for_each_cpu(freqs.cpu, policy->cpus) |
98 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
7c1a70e9 | 99 | |
72b2fd5c | 100 | return 0; |
7c1a70e9 MP |
101 | } |
102 | ||
72b2fd5c | 103 | static unsigned int db8500_cpufreq_getspeed(unsigned int cpu) |
7c1a70e9 MP |
104 | { |
105 | int i; | |
72b2fd5c LW |
106 | /* request the prcm to get the current ARM opp */ |
107 | for (i = 0; prcmu_get_arm_opp() != idx2opp[i]; i++) | |
7c1a70e9 MP |
108 | ; |
109 | return freq_table[i].frequency; | |
110 | } | |
111 | ||
72b2fd5c | 112 | static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy) |
7c1a70e9 | 113 | { |
eb0b38a5 | 114 | int i, res; |
7c1a70e9 | 115 | |
72b2fd5c | 116 | BUILD_BUG_ON(ARRAY_SIZE(idx2opp) + 1 != ARRAY_SIZE(freq_table)); |
7c1a70e9 | 117 | |
c72fe851 DW |
118 | if (prcmu_has_arm_maxopp()) |
119 | freq_table[3].frequency = 1000000; | |
120 | ||
6283e328 | 121 | pr_info("db8500-cpufreq : Available frequencies:\n"); |
eb0b38a5 AL |
122 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) |
123 | pr_info(" %d Mhz\n", freq_table[i].frequency/1000); | |
7c1a70e9 MP |
124 | |
125 | /* get policy fields based on the table */ | |
126 | res = cpufreq_frequency_table_cpuinfo(policy, freq_table); | |
127 | if (!res) | |
128 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
129 | else { | |
72b2fd5c | 130 | pr_err("db8500-cpufreq : Failed to read policy table\n"); |
7c1a70e9 MP |
131 | return res; |
132 | } | |
133 | ||
134 | policy->min = policy->cpuinfo.min_freq; | |
135 | policy->max = policy->cpuinfo.max_freq; | |
72b2fd5c | 136 | policy->cur = db8500_cpufreq_getspeed(policy->cpu); |
7c1a70e9 MP |
137 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; |
138 | ||
139 | /* | |
140 | * FIXME : Need to take time measurement across the target() | |
141 | * function with no/some/all drivers in the notification | |
142 | * list. | |
143 | */ | |
72b2fd5c | 144 | policy->cpuinfo.transition_latency = 20 * 1000; /* in ns */ |
7c1a70e9 MP |
145 | |
146 | /* policy sharing between dual CPUs */ | |
88d8cd52 | 147 | cpumask_copy(policy->cpus, cpu_present_mask); |
7c1a70e9 MP |
148 | |
149 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
150 | ||
7c1a70e9 MP |
151 | return 0; |
152 | } | |
153 | ||
72b2fd5c LW |
154 | static struct cpufreq_driver db8500_cpufreq_driver = { |
155 | .flags = CPUFREQ_STICKY, | |
156 | .verify = db8500_cpufreq_verify_speed, | |
157 | .target = db8500_cpufreq_target, | |
158 | .get = db8500_cpufreq_getspeed, | |
159 | .init = db8500_cpufreq_init, | |
160 | .name = "DB8500", | |
161 | .attr = db8500_cpufreq_attr, | |
7c1a70e9 MP |
162 | }; |
163 | ||
b4689444 UH |
164 | static int db8500_cpufreq_probe(struct platform_device *pdev) |
165 | { | |
166 | return cpufreq_register_driver(&db8500_cpufreq_driver); | |
167 | } | |
168 | ||
169 | static struct platform_driver db8500_cpufreq_plat_driver = { | |
170 | .driver = { | |
171 | .name = "cpufreq-u8500", | |
172 | .owner = THIS_MODULE, | |
173 | }, | |
174 | .probe = db8500_cpufreq_probe, | |
175 | }; | |
176 | ||
72b2fd5c | 177 | static int __init db8500_cpufreq_register(void) |
7c1a70e9 | 178 | { |
bc71c096 | 179 | if (!cpu_is_u8500_family()) |
72b2fd5c | 180 | return -ENODEV; |
7c1a70e9 | 181 | |
72b2fd5c | 182 | pr_info("cpufreq for DB8500 started\n"); |
b4689444 | 183 | return platform_driver_register(&db8500_cpufreq_plat_driver); |
7c1a70e9 | 184 | } |
72b2fd5c | 185 | device_initcall(db8500_cpufreq_register); |
b4689444 UH |
186 | |
187 | MODULE_LICENSE("GPL v2"); | |
188 | MODULE_DESCRIPTION("cpufreq driver for DB8500"); |