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Commit | Line | Data |
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7c1a70e9 | 1 | /* |
7c1a70e9 MP |
2 | * Copyright (C) STMicroelectronics 2009 |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
5 | * License Terms: GNU General Public License v2 | |
7c1a70e9 MP |
6 | * Author: Sundar Iyer <sundar.iyer@stericsson.com> |
7 | * Author: Martin Persson <martin.persson@stericsson.com> | |
8 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> | |
9 | * | |
10 | */ | |
b4689444 | 11 | #include <linux/module.h> |
7c1a70e9 MP |
12 | #include <linux/kernel.h> |
13 | #include <linux/cpufreq.h> | |
14 | #include <linux/delay.h> | |
72b2fd5c | 15 | #include <linux/slab.h> |
b4689444 | 16 | #include <linux/platform_device.h> |
78e30d12 | 17 | #include <linux/clk.h> |
72b2fd5c | 18 | #include <mach/id.h> |
7c1a70e9 | 19 | |
fdb44464 | 20 | static struct cpufreq_frequency_table *freq_table; |
78e30d12 | 21 | static struct clk *armss_clk; |
72b2fd5c | 22 | |
edb10c11 | 23 | static struct freq_attr *dbx500_cpufreq_attr[] = { |
72b2fd5c LW |
24 | &cpufreq_freq_attr_scaling_available_freqs, |
25 | NULL, | |
7c1a70e9 MP |
26 | }; |
27 | ||
edb10c11 | 28 | static int dbx500_cpufreq_verify_speed(struct cpufreq_policy *policy) |
7c1a70e9 MP |
29 | { |
30 | return cpufreq_frequency_table_verify(policy, freq_table); | |
31 | } | |
32 | ||
edb10c11 | 33 | static int dbx500_cpufreq_target(struct cpufreq_policy *policy, |
7c1a70e9 MP |
34 | unsigned int target_freq, |
35 | unsigned int relation) | |
36 | { | |
37 | struct cpufreq_freqs freqs; | |
72b2fd5c | 38 | unsigned int idx; |
7c1a70e9 | 39 | |
72b2fd5c | 40 | /* scale the target frequency to one of the extremes supported */ |
7c1a70e9 MP |
41 | if (target_freq < policy->cpuinfo.min_freq) |
42 | target_freq = policy->cpuinfo.min_freq; | |
43 | if (target_freq > policy->cpuinfo.max_freq) | |
44 | target_freq = policy->cpuinfo.max_freq; | |
45 | ||
72b2fd5c LW |
46 | /* Lookup the next frequency */ |
47 | if (cpufreq_frequency_table_target | |
48 | (policy, freq_table, target_freq, relation, &idx)) { | |
49 | return -EINVAL; | |
7c1a70e9 MP |
50 | } |
51 | ||
52 | freqs.old = policy->cur; | |
72b2fd5c | 53 | freqs.new = freq_table[idx].frequency; |
7c1a70e9 | 54 | |
72b2fd5c | 55 | if (freqs.old == freqs.new) |
7c1a70e9 | 56 | return 0; |
7c1a70e9 | 57 | |
72b2fd5c | 58 | /* pre-change notification */ |
8efd072b VG |
59 | for_each_cpu(freqs.cpu, policy->cpus) |
60 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
7c1a70e9 | 61 | |
78e30d12 UH |
62 | /* update armss clk frequency */ |
63 | if (clk_set_rate(armss_clk, freq_table[idx].frequency * 1000)) { | |
edb10c11 | 64 | pr_err("dbx500-cpufreq: Failed to update armss clk\n"); |
72b2fd5c | 65 | return -EINVAL; |
7c1a70e9 MP |
66 | } |
67 | ||
72b2fd5c | 68 | /* post change notification */ |
8efd072b VG |
69 | for_each_cpu(freqs.cpu, policy->cpus) |
70 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
7c1a70e9 | 71 | |
72b2fd5c | 72 | return 0; |
7c1a70e9 MP |
73 | } |
74 | ||
edb10c11 | 75 | static unsigned int dbx500_cpufreq_getspeed(unsigned int cpu) |
7c1a70e9 | 76 | { |
fdb44464 | 77 | int i = 0; |
78e30d12 | 78 | unsigned long freq = clk_get_rate(armss_clk) / 1000; |
fdb44464 UH |
79 | |
80 | while (freq_table[i].frequency != CPUFREQ_TABLE_END) { | |
78e30d12 | 81 | if (freq <= freq_table[i].frequency) |
fdb44464 UH |
82 | return freq_table[i].frequency; |
83 | i++; | |
84 | } | |
85 | ||
78e30d12 | 86 | /* We could not find a corresponding frequency. */ |
edb10c11 | 87 | pr_err("dbx500-cpufreq: Failed to find cpufreq speed\n"); |
fdb44464 | 88 | return 0; |
7c1a70e9 MP |
89 | } |
90 | ||
edb10c11 | 91 | static int __cpuinit dbx500_cpufreq_init(struct cpufreq_policy *policy) |
7c1a70e9 | 92 | { |
fdb44464 | 93 | int res; |
c72fe851 | 94 | |
7c1a70e9 MP |
95 | /* get policy fields based on the table */ |
96 | res = cpufreq_frequency_table_cpuinfo(policy, freq_table); | |
97 | if (!res) | |
98 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
99 | else { | |
edb10c11 | 100 | pr_err("dbx500-cpufreq : Failed to read policy table\n"); |
7c1a70e9 MP |
101 | return res; |
102 | } | |
103 | ||
104 | policy->min = policy->cpuinfo.min_freq; | |
105 | policy->max = policy->cpuinfo.max_freq; | |
edb10c11 | 106 | policy->cur = dbx500_cpufreq_getspeed(policy->cpu); |
7c1a70e9 MP |
107 | policy->governor = CPUFREQ_DEFAULT_GOVERNOR; |
108 | ||
109 | /* | |
110 | * FIXME : Need to take time measurement across the target() | |
111 | * function with no/some/all drivers in the notification | |
112 | * list. | |
113 | */ | |
72b2fd5c | 114 | policy->cpuinfo.transition_latency = 20 * 1000; /* in ns */ |
7c1a70e9 MP |
115 | |
116 | /* policy sharing between dual CPUs */ | |
88d8cd52 | 117 | cpumask_copy(policy->cpus, cpu_present_mask); |
7c1a70e9 MP |
118 | |
119 | policy->shared_type = CPUFREQ_SHARED_TYPE_ALL; | |
120 | ||
7c1a70e9 MP |
121 | return 0; |
122 | } | |
123 | ||
edb10c11 | 124 | static struct cpufreq_driver dbx500_cpufreq_driver = { |
72b2fd5c | 125 | .flags = CPUFREQ_STICKY, |
edb10c11 LJ |
126 | .verify = dbx500_cpufreq_verify_speed, |
127 | .target = dbx500_cpufreq_target, | |
128 | .get = dbx500_cpufreq_getspeed, | |
129 | .init = dbx500_cpufreq_init, | |
130 | .name = "DBX500", | |
131 | .attr = dbx500_cpufreq_attr, | |
7c1a70e9 MP |
132 | }; |
133 | ||
edb10c11 | 134 | static int dbx500_cpufreq_probe(struct platform_device *pdev) |
b4689444 | 135 | { |
3e27996c | 136 | int i = 0; |
fdb44464 | 137 | |
3e27996c | 138 | freq_table = dev_get_platdata(&pdev->dev); |
fdb44464 | 139 | if (!freq_table) { |
edb10c11 | 140 | pr_err("dbx500-cpufreq: Failed to fetch cpufreq table\n"); |
fdb44464 UH |
141 | return -ENODEV; |
142 | } | |
143 | ||
3e27996c UH |
144 | armss_clk = clk_get(&pdev->dev, "armss"); |
145 | if (IS_ERR(armss_clk)) { | |
146 | pr_err("dbx500-cpufreq : Failed to get armss clk\n"); | |
147 | return PTR_ERR(armss_clk); | |
148 | } | |
149 | ||
150 | pr_info("dbx500-cpufreq : Available frequencies:\n"); | |
151 | while (freq_table[i].frequency != CPUFREQ_TABLE_END) { | |
152 | pr_info(" %d Mhz\n", freq_table[i].frequency/1000); | |
153 | i++; | |
154 | } | |
155 | ||
edb10c11 | 156 | return cpufreq_register_driver(&dbx500_cpufreq_driver); |
b4689444 UH |
157 | } |
158 | ||
edb10c11 | 159 | static struct platform_driver dbx500_cpufreq_plat_driver = { |
b4689444 | 160 | .driver = { |
edb10c11 | 161 | .name = "cpufreq-ux500", |
b4689444 UH |
162 | .owner = THIS_MODULE, |
163 | }, | |
edb10c11 | 164 | .probe = dbx500_cpufreq_probe, |
b4689444 UH |
165 | }; |
166 | ||
edb10c11 | 167 | static int __init dbx500_cpufreq_register(void) |
7c1a70e9 | 168 | { |
bc71c096 | 169 | if (!cpu_is_u8500_family()) |
72b2fd5c | 170 | return -ENODEV; |
7c1a70e9 | 171 | |
edb10c11 LJ |
172 | pr_info("cpufreq for DBX500 started\n"); |
173 | return platform_driver_register(&dbx500_cpufreq_plat_driver); | |
7c1a70e9 | 174 | } |
edb10c11 | 175 | device_initcall(dbx500_cpufreq_register); |
b4689444 UH |
176 | |
177 | MODULE_LICENSE("GPL v2"); | |
edb10c11 | 178 | MODULE_DESCRIPTION("cpufreq driver for DBX500"); |