]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/cpufreq/elanfreq.c
scsi: cxlflash: Create character device to provide host management interface
[mirror_ubuntu-zesty-kernel.git] / drivers / cpufreq / elanfreq.c
CommitLineData
1da177e4 1/*
32ee8c3e 2 * elanfreq: cpufreq driver for the AMD ELAN family
1da177e4
LT
3 *
4 * (c) Copyright 2002 Robert Schwebel <r.schwebel@pengutronix.de>
5 *
32ee8c3e 6 * Parts of this code are (c) Sven Geggus <sven@geggus.net>
1da177e4 7 *
32ee8c3e 8 * All Rights Reserved.
1da177e4
LT
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
32ee8c3e 13 * 2 of the License, or (at your option) any later version.
1da177e4
LT
14 *
15 * 2002-02-13: - initial revision for 2.4.18-pre9 by Robert Schwebel
16 *
17 */
18
1c5864e2
JP
19#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
1da177e4
LT
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24
1da177e4
LT
25#include <linux/delay.h>
26#include <linux/cpufreq.h>
27
fa8031ae 28#include <asm/cpu_device_id.h>
1da177e4 29#include <asm/msr.h>
18c6faa9
PC
30#include <linux/timex.h>
31#include <linux/io.h>
1da177e4 32
32ee8c3e 33#define REG_CSCIR 0x22 /* Chip Setup and Control Index Register */
1da177e4
LT
34#define REG_CSCDR 0x23 /* Chip Setup and Control Data Register */
35
36/* Module parameter */
37static int max_freq;
38
39struct s_elan_multiplier {
40 int clock; /* frequency in kHz */
41 int val40h; /* PMU Force Mode register */
42 int val80h; /* CPU Clock Speed Register */
43};
44
45/*
32ee8c3e 46 * It is important that the frequencies
1da177e4
LT
47 * are listed in ascending order here!
48 */
460f5ef2 49static struct s_elan_multiplier elan_multiplier[] = {
1da177e4
LT
50 {1000, 0x02, 0x18},
51 {2000, 0x02, 0x10},
52 {4000, 0x02, 0x08},
53 {8000, 0x00, 0x00},
54 {16000, 0x00, 0x02},
55 {33000, 0x00, 0x04},
56 {66000, 0x01, 0x04},
57 {99000, 0x01, 0x05}
58};
59
60static struct cpufreq_frequency_table elanfreq_table[] = {
7f4b0461
VK
61 {0, 0, 1000},
62 {0, 1, 2000},
63 {0, 2, 4000},
64 {0, 3, 8000},
65 {0, 4, 16000},
66 {0, 5, 33000},
67 {0, 6, 66000},
68 {0, 7, 99000},
69 {0, 0, CPUFREQ_TABLE_END},
1da177e4
LT
70};
71
72
73/**
74 * elanfreq_get_cpu_frequency: determine current cpu speed
75 *
76 * Finds out at which frequency the CPU of the Elan SOC runs
32ee8c3e 77 * at the moment. Frequencies from 1 to 33 MHz are generated
1da177e4 78 * the normal way, 66 and 99 MHz are called "Hyperspeed Mode"
32ee8c3e 79 * and have the rest of the chip running with 33 MHz.
1da177e4
LT
80 */
81
82static unsigned int elanfreq_get_cpu_frequency(unsigned int cpu)
83{
32ee8c3e
DJ
84 u8 clockspeed_reg; /* Clock Speed Register */
85
1da177e4 86 local_irq_disable();
18c6faa9 87 outb_p(0x80, REG_CSCIR);
32ee8c3e 88 clockspeed_reg = inb_p(REG_CSCDR);
1da177e4
LT
89 local_irq_enable();
90
32ee8c3e
DJ
91 if ((clockspeed_reg & 0xE0) == 0xE0)
92 return 0;
1da177e4 93
32ee8c3e
DJ
94 /* Are we in CPU clock multiplied mode (66/99 MHz)? */
95 if ((clockspeed_reg & 0xE0) == 0xC0) {
96 if ((clockspeed_reg & 0x01) == 0)
1da177e4 97 return 66000;
32ee8c3e
DJ
98 else
99 return 99000;
100 }
1da177e4
LT
101
102 /* 33 MHz is not 32 MHz... */
18c6faa9 103 if ((clockspeed_reg & 0xE0) == 0xA0)
1da177e4
LT
104 return 33000;
105
18c6faa9 106 return (1<<((clockspeed_reg & 0xE0) >> 5)) * 1000;
1da177e4
LT
107}
108
109
9c0ebcf7
VK
110static int elanfreq_target(struct cpufreq_policy *policy,
111 unsigned int state)
32ee8c3e 112{
32ee8c3e
DJ
113 /*
114 * Access to the Elan's internal registers is indexed via
115 * 0x22: Chip Setup & Control Register Index Register (CSCI)
116 * 0x23: Chip Setup & Control Register Data Register (CSCD)
1da177e4
LT
117 *
118 */
119
32ee8c3e
DJ
120 /*
121 * 0x40 is the Power Management Unit's Force Mode Register.
1da177e4
LT
122 * Bit 6 enables Hyperspeed Mode (66/100 MHz core frequency)
123 */
124
125 local_irq_disable();
18c6faa9
PC
126 outb_p(0x40, REG_CSCIR); /* Disable hyperspeed mode */
127 outb_p(0x00, REG_CSCDR);
1da177e4
LT
128 local_irq_enable(); /* wait till internal pipelines and */
129 udelay(1000); /* buffers have cleaned up */
130
131 local_irq_disable();
132
133 /* now, set the CPU clock speed register (0x80) */
18c6faa9
PC
134 outb_p(0x80, REG_CSCIR);
135 outb_p(elan_multiplier[state].val80h, REG_CSCDR);
1da177e4
LT
136
137 /* now, the hyperspeed bit in PMU Force Mode Register (0x40) */
18c6faa9
PC
138 outb_p(0x40, REG_CSCIR);
139 outb_p(elan_multiplier[state].val40h, REG_CSCDR);
1da177e4
LT
140 udelay(10000);
141 local_irq_enable();
142
1da177e4
LT
143 return 0;
144}
1da177e4
LT
145/*
146 * Module init and exit code
147 */
148
149static int elanfreq_cpu_init(struct cpufreq_policy *policy)
150{
92cb7612 151 struct cpuinfo_x86 *c = &cpu_data(0);
041526f9 152 struct cpufreq_frequency_table *pos;
1da177e4
LT
153
154 /* capability check */
155 if ((c->x86_vendor != X86_VENDOR_AMD) ||
18c6faa9 156 (c->x86 != 4) || (c->x86_model != 10))
1da177e4
LT
157 return -ENODEV;
158
159 /* max freq */
160 if (!max_freq)
161 max_freq = elanfreq_get_cpu_frequency(0);
162
163 /* table init */
041526f9
SK
164 cpufreq_for_each_entry(pos, elanfreq_table)
165 if (pos->frequency > max_freq)
166 pos->frequency = CPUFREQ_ENTRY_INVALID;
1da177e4
LT
167
168 /* cpuinfo and default policy values */
1da177e4 169 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
1da177e4 170
55bb85b7 171 return cpufreq_table_validate_and_show(policy, elanfreq_table);
1da177e4
LT
172}
173
174
1da177e4
LT
175#ifndef MODULE
176/**
177 * elanfreq_setup - elanfreq command line parameter parsing
178 *
179 * elanfreq command line parameter. Use:
180 * elanfreq=66000
181 * to set the maximum CPU frequency to 66 MHz. Note that in
182 * case you do not give this boot parameter, the maximum
183 * frequency will fall back to _current_ CPU frequency which
184 * might be lower. If you build this as a module, use the
185 * max_freq module parameter instead.
186 */
187static int __init elanfreq_setup(char *str)
188{
189 max_freq = simple_strtoul(str, &str, 0);
b49c22a6 190 pr_warn("You're using the deprecated elanfreq command line option. Use elanfreq.max_freq instead, please!\n");
1da177e4
LT
191 return 1;
192}
193__setup("elanfreq=", elanfreq_setup);
194#endif
195
196
221dee28 197static struct cpufreq_driver elanfreq_driver = {
32ee8c3e 198 .get = elanfreq_get_cpu_frequency,
06494eb7 199 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 200 .target_index = elanfreq_target,
1da177e4 201 .init = elanfreq_cpu_init,
1da177e4 202 .name = "elanfreq",
06494eb7 203 .attr = cpufreq_generic_attr,
1da177e4
LT
204};
205
fa8031ae
AK
206static const struct x86_cpu_id elan_id[] = {
207 { X86_VENDOR_AMD, 4, 10, },
208 {}
209};
210MODULE_DEVICE_TABLE(x86cpu, elan_id);
1da177e4 211
32ee8c3e
DJ
212static int __init elanfreq_init(void)
213{
fa8031ae 214 if (!x86_match_cpu(elan_id))
18c6faa9 215 return -ENODEV;
1da177e4
LT
216 return cpufreq_register_driver(&elanfreq_driver);
217}
218
219
32ee8c3e 220static void __exit elanfreq_exit(void)
1da177e4
LT
221{
222 cpufreq_unregister_driver(&elanfreq_driver);
223}
224
225
18c6faa9 226module_param(max_freq, int, 0444);
1da177e4
LT
227
228MODULE_LICENSE("GPL");
04cd1a99
DJ
229MODULE_AUTHOR("Robert Schwebel <r.schwebel@pengutronix.de>, "
230 "Sven Geggus <sven@geggus.net>");
1da177e4
LT
231MODULE_DESCRIPTION("cpufreq driver for AMD's Elan CPUs");
232
233module_init(elanfreq_init);
234module_exit(elanfreq_exit);