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a125a17f JL |
1 | /* |
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS - CPU frequency scaling support for EXYNOS series | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
a125a17f JL |
12 | #include <linux/kernel.h> |
13 | #include <linux/err.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/regulator/consumer.h> | |
18 | #include <linux/cpufreq.h> | |
19 | #include <linux/suspend.h> | |
a125a17f | 20 | |
6c523c61 | 21 | #include <plat/cpu.h> |
a125a17f | 22 | |
c4aaa295 KK |
23 | #include "exynos-cpufreq.h" |
24 | ||
a125a17f JL |
25 | static struct exynos_dvfs_info *exynos_info; |
26 | ||
27 | static struct regulator *arm_regulator; | |
28 | static struct cpufreq_freqs freqs; | |
29 | ||
30 | static unsigned int locking_frequency; | |
31 | static bool frequency_locked; | |
32 | static DEFINE_MUTEX(cpufreq_lock); | |
33 | ||
5542721a | 34 | static unsigned int exynos_getspeed(unsigned int cpu) |
a125a17f JL |
35 | { |
36 | return clk_get_rate(exynos_info->cpu_clk) / 1000; | |
37 | } | |
38 | ||
0e0e425f JC |
39 | static int exynos_cpufreq_get_index(unsigned int freq) |
40 | { | |
41 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; | |
42 | int index; | |
43 | ||
44 | for (index = 0; | |
45 | freq_table[index].frequency != CPUFREQ_TABLE_END; index++) | |
46 | if (freq_table[index].frequency == freq) | |
47 | break; | |
48 | ||
49 | if (freq_table[index].frequency == CPUFREQ_TABLE_END) | |
50 | return -EINVAL; | |
51 | ||
52 | return index; | |
53 | } | |
54 | ||
55 | static int exynos_cpufreq_scale(unsigned int target_freq) | |
a125a17f | 56 | { |
a125a17f JL |
57 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; |
58 | unsigned int *volt_table = exynos_info->volt_table; | |
0e0e425f JC |
59 | struct cpufreq_policy *policy = cpufreq_cpu_get(0); |
60 | unsigned int arm_volt, safe_arm_volt = 0; | |
a125a17f | 61 | unsigned int mpll_freq_khz = exynos_info->mpll_freq_khz; |
d271d077 | 62 | int index, old_index; |
0e0e425f | 63 | int ret = 0; |
a125a17f JL |
64 | |
65 | freqs.old = policy->cur; | |
c098ea74 | 66 | freqs.new = target_freq; |
a125a17f | 67 | |
53df1ad5 JL |
68 | /* |
69 | * The policy max have been changed so that we cannot get proper | |
70 | * old_index with cpufreq_frequency_table_target(). Thus, ignore | |
71 | * policy and get the index from the raw freqeuncy table. | |
72 | */ | |
0e0e425f JC |
73 | old_index = exynos_cpufreq_get_index(freqs.old); |
74 | if (old_index < 0) { | |
75 | ret = old_index; | |
a125a17f JL |
76 | goto out; |
77 | } | |
78 | ||
0e0e425f JC |
79 | index = exynos_cpufreq_get_index(target_freq); |
80 | if (index < 0) { | |
81 | ret = index; | |
a125a17f JL |
82 | goto out; |
83 | } | |
84 | ||
a125a17f JL |
85 | /* |
86 | * ARM clock source will be changed APLL to MPLL temporary | |
87 | * To support this level, need to control regulator for | |
88 | * required voltage level | |
89 | */ | |
90 | if (exynos_info->need_apll_change != NULL) { | |
91 | if (exynos_info->need_apll_change(old_index, index) && | |
92 | (freq_table[index].frequency < mpll_freq_khz) && | |
93 | (freq_table[old_index].frequency < mpll_freq_khz)) | |
94 | safe_arm_volt = volt_table[exynos_info->pll_safe_idx]; | |
95 | } | |
96 | arm_volt = volt_table[index]; | |
97 | ||
b43a7ffb | 98 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
a125a17f JL |
99 | |
100 | /* When the new frequency is higher than current frequency */ | |
101 | if ((freqs.new > freqs.old) && !safe_arm_volt) { | |
102 | /* Firstly, voltage up to increase frequency */ | |
0e0e425f JC |
103 | ret = regulator_set_voltage(arm_regulator, arm_volt, arm_volt); |
104 | if (ret) { | |
105 | pr_err("%s: failed to set cpu voltage to %d\n", | |
106 | __func__, arm_volt); | |
c3aca6b1 VK |
107 | freqs.new = freqs.old; |
108 | goto post_notify; | |
0e0e425f | 109 | } |
a125a17f JL |
110 | } |
111 | ||
0e0e425f JC |
112 | if (safe_arm_volt) { |
113 | ret = regulator_set_voltage(arm_regulator, safe_arm_volt, | |
a125a17f | 114 | safe_arm_volt); |
0e0e425f JC |
115 | if (ret) { |
116 | pr_err("%s: failed to set cpu voltage to %d\n", | |
117 | __func__, safe_arm_volt); | |
c3aca6b1 VK |
118 | freqs.new = freqs.old; |
119 | goto post_notify; | |
0e0e425f JC |
120 | } |
121 | } | |
857d90f7 JC |
122 | |
123 | exynos_info->set_freq(old_index, index); | |
a125a17f | 124 | |
c3aca6b1 | 125 | post_notify: |
b43a7ffb | 126 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
a125a17f | 127 | |
c3aca6b1 VK |
128 | if (ret) |
129 | goto out; | |
130 | ||
a125a17f JL |
131 | /* When the new frequency is lower than current frequency */ |
132 | if ((freqs.new < freqs.old) || | |
133 | ((freqs.new > freqs.old) && safe_arm_volt)) { | |
134 | /* down the voltage after frequency change */ | |
006454ae | 135 | ret = regulator_set_voltage(arm_regulator, arm_volt, |
a125a17f | 136 | arm_volt); |
0e0e425f JC |
137 | if (ret) { |
138 | pr_err("%s: failed to set cpu voltage to %d\n", | |
139 | __func__, arm_volt); | |
140 | goto out; | |
141 | } | |
a125a17f JL |
142 | } |
143 | ||
0e0e425f JC |
144 | out: |
145 | ||
146 | cpufreq_cpu_put(policy); | |
147 | ||
148 | return ret; | |
149 | } | |
150 | ||
9c0ebcf7 | 151 | static int exynos_target(struct cpufreq_policy *policy, unsigned int index) |
0e0e425f JC |
152 | { |
153 | struct cpufreq_frequency_table *freq_table = exynos_info->freq_table; | |
229b21e2 | 154 | int ret = 0; |
0e0e425f JC |
155 | |
156 | mutex_lock(&cpufreq_lock); | |
157 | ||
158 | if (frequency_locked) | |
159 | goto out; | |
160 | ||
9c0ebcf7 | 161 | ret = exynos_cpufreq_scale(freq_table[index].frequency); |
0e0e425f | 162 | |
a125a17f JL |
163 | out: |
164 | mutex_unlock(&cpufreq_lock); | |
165 | ||
166 | return ret; | |
167 | } | |
168 | ||
169 | #ifdef CONFIG_PM | |
170 | static int exynos_cpufreq_suspend(struct cpufreq_policy *policy) | |
171 | { | |
172 | return 0; | |
173 | } | |
174 | ||
175 | static int exynos_cpufreq_resume(struct cpufreq_policy *policy) | |
176 | { | |
177 | return 0; | |
178 | } | |
179 | #endif | |
180 | ||
181 | /** | |
182 | * exynos_cpufreq_pm_notifier - block CPUFREQ's activities in suspend-resume | |
183 | * context | |
184 | * @notifier | |
185 | * @pm_event | |
186 | * @v | |
187 | * | |
188 | * While frequency_locked == true, target() ignores every frequency but | |
189 | * locking_frequency. The locking_frequency value is the initial frequency, | |
190 | * which is set by the bootloader. In order to eliminate possible | |
191 | * inconsistency in clock values, we save and restore frequencies during | |
192 | * suspend and resume and block CPUFREQ activities. Note that the standard | |
193 | * suspend/resume cannot be used as they are too deep (syscore_ops) for | |
194 | * regulator actions. | |
195 | */ | |
196 | static int exynos_cpufreq_pm_notifier(struct notifier_block *notifier, | |
197 | unsigned long pm_event, void *v) | |
198 | { | |
0e0e425f | 199 | int ret; |
a125a17f | 200 | |
a125a17f JL |
201 | switch (pm_event) { |
202 | case PM_SUSPEND_PREPARE: | |
0e0e425f | 203 | mutex_lock(&cpufreq_lock); |
a125a17f | 204 | frequency_locked = true; |
0e0e425f | 205 | mutex_unlock(&cpufreq_lock); |
a125a17f | 206 | |
0e0e425f JC |
207 | ret = exynos_cpufreq_scale(locking_frequency); |
208 | if (ret < 0) | |
209 | return NOTIFY_BAD; | |
a125a17f | 210 | |
a125a17f JL |
211 | break; |
212 | ||
213 | case PM_POST_SUSPEND: | |
0e0e425f | 214 | mutex_lock(&cpufreq_lock); |
a125a17f | 215 | frequency_locked = false; |
0e0e425f | 216 | mutex_unlock(&cpufreq_lock); |
a125a17f JL |
217 | break; |
218 | } | |
a125a17f JL |
219 | |
220 | return NOTIFY_OK; | |
221 | } | |
222 | ||
223 | static struct notifier_block exynos_cpufreq_nb = { | |
224 | .notifier_call = exynos_cpufreq_pm_notifier, | |
225 | }; | |
226 | ||
227 | static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
228 | { | |
b249abae | 229 | return cpufreq_generic_init(policy, exynos_info->freq_table, 100000); |
a125a17f JL |
230 | } |
231 | ||
232 | static struct cpufreq_driver exynos_driver = { | |
233 | .flags = CPUFREQ_STICKY, | |
eea6181e | 234 | .verify = cpufreq_generic_frequency_table_verify, |
9c0ebcf7 | 235 | .target_index = exynos_target, |
a125a17f JL |
236 | .get = exynos_getspeed, |
237 | .init = exynos_cpufreq_cpu_init, | |
eea6181e | 238 | .exit = cpufreq_generic_exit, |
a125a17f | 239 | .name = "exynos_cpufreq", |
eea6181e | 240 | .attr = cpufreq_generic_attr, |
a125a17f JL |
241 | #ifdef CONFIG_PM |
242 | .suspend = exynos_cpufreq_suspend, | |
243 | .resume = exynos_cpufreq_resume, | |
244 | #endif | |
245 | }; | |
246 | ||
247 | static int __init exynos_cpufreq_init(void) | |
248 | { | |
249 | int ret = -EINVAL; | |
250 | ||
d5b73cd8 | 251 | exynos_info = kzalloc(sizeof(*exynos_info), GFP_KERNEL); |
a125a17f JL |
252 | if (!exynos_info) |
253 | return -ENOMEM; | |
254 | ||
255 | if (soc_is_exynos4210()) | |
256 | ret = exynos4210_cpufreq_init(exynos_info); | |
a35c5051 JL |
257 | else if (soc_is_exynos4212() || soc_is_exynos4412()) |
258 | ret = exynos4x12_cpufreq_init(exynos_info); | |
562a6cbe JL |
259 | else if (soc_is_exynos5250()) |
260 | ret = exynos5250_cpufreq_init(exynos_info); | |
a125a17f | 261 | else |
c1585207 | 262 | return 0; |
a125a17f JL |
263 | |
264 | if (ret) | |
265 | goto err_vdd_arm; | |
266 | ||
267 | if (exynos_info->set_freq == NULL) { | |
268 | pr_err("%s: No set_freq function (ERR)\n", __func__); | |
269 | goto err_vdd_arm; | |
270 | } | |
271 | ||
272 | arm_regulator = regulator_get(NULL, "vdd_arm"); | |
273 | if (IS_ERR(arm_regulator)) { | |
274 | pr_err("%s: failed to get resource vdd_arm\n", __func__); | |
275 | goto err_vdd_arm; | |
276 | } | |
277 | ||
6e45eb12 JC |
278 | locking_frequency = exynos_getspeed(0); |
279 | ||
a125a17f JL |
280 | register_pm_notifier(&exynos_cpufreq_nb); |
281 | ||
282 | if (cpufreq_register_driver(&exynos_driver)) { | |
283 | pr_err("%s: failed to register cpufreq driver\n", __func__); | |
284 | goto err_cpufreq; | |
285 | } | |
286 | ||
287 | return 0; | |
288 | err_cpufreq: | |
289 | unregister_pm_notifier(&exynos_cpufreq_nb); | |
290 | ||
184cddd1 | 291 | regulator_put(arm_regulator); |
a125a17f JL |
292 | err_vdd_arm: |
293 | kfree(exynos_info); | |
a125a17f JL |
294 | return -EINVAL; |
295 | } | |
296 | late_initcall(exynos_cpufreq_init); |