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c4aaa295 | 1 | /* |
a125a17f JL |
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
3 | * http://www.samsung.com | |
4 | * | |
5 | * EXYNOS - CPUFreq support | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | enum cpufreq_level_index { | |
13 | L0, L1, L2, L3, L4, | |
14 | L5, L6, L7, L8, L9, | |
15 | L10, L11, L12, L13, L14, | |
16 | L15, L16, L17, L18, L19, | |
17 | L20, | |
18 | }; | |
19 | ||
9d0554ff JC |
20 | #define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \ |
21 | { \ | |
22 | .freq = (f) * 1000, \ | |
23 | .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \ | |
24 | (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \ | |
25 | .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \ | |
26 | .mps = ((m) << 16 | (p) << 8 | (s)), \ | |
27 | } | |
28 | ||
29 | struct apll_freq { | |
30 | unsigned int freq; | |
31 | u32 clk_div_cpu0; | |
32 | u32 clk_div_cpu1; | |
33 | u32 mps; | |
34 | }; | |
35 | ||
a125a17f JL |
36 | struct exynos_dvfs_info { |
37 | unsigned long mpll_freq_khz; | |
38 | unsigned int pll_safe_idx; | |
a125a17f JL |
39 | struct clk *cpu_clk; |
40 | unsigned int *volt_table; | |
41 | struct cpufreq_frequency_table *freq_table; | |
42 | void (*set_freq)(unsigned int, unsigned int); | |
43 | bool (*need_apll_change)(unsigned int, unsigned int); | |
44 | }; | |
45 | ||
45e12086 | 46 | #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ |
a125a17f | 47 | extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *); |
45e12086 BZ |
48 | #else |
49 | static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) | |
50 | { | |
51 | return -EOPNOTSUPP; | |
52 | } | |
53 | #endif | |
54 | #ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ | |
a35c5051 | 55 | extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *); |
45e12086 BZ |
56 | #else |
57 | static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) | |
58 | { | |
59 | return -EOPNOTSUPP; | |
60 | } | |
61 | #endif | |
62 | #ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ | |
562a6cbe | 63 | extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *); |
45e12086 BZ |
64 | #else |
65 | static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) | |
66 | { | |
67 | return -EOPNOTSUPP; | |
68 | } | |
69 | #endif | |
df3e9c05 KK |
70 | |
71 | #include <plat/cpu.h> | |
72 | #include <mach/map.h> | |
73 | ||
74 | #define EXYNOS4_CLKSRC_CPU (S5P_VA_CMU + 0x14200) | |
75 | #define EXYNOS4_CLKMUX_STATCPU (S5P_VA_CMU + 0x14400) | |
76 | ||
77 | #define EXYNOS4_CLKDIV_CPU (S5P_VA_CMU + 0x14500) | |
78 | #define EXYNOS4_CLKDIV_CPU1 (S5P_VA_CMU + 0x14504) | |
79 | #define EXYNOS4_CLKDIV_STATCPU (S5P_VA_CMU + 0x14600) | |
80 | #define EXYNOS4_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x14604) | |
81 | ||
82 | #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) | |
83 | #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) | |
84 | ||
85 | #define EXYNOS5_APLL_LOCK (S5P_VA_CMU + 0x00000) | |
86 | #define EXYNOS5_APLL_CON0 (S5P_VA_CMU + 0x00100) | |
87 | #define EXYNOS5_CLKMUX_STATCPU (S5P_VA_CMU + 0x00400) | |
88 | #define EXYNOS5_CLKDIV_CPU0 (S5P_VA_CMU + 0x00500) | |
89 | #define EXYNOS5_CLKDIV_CPU1 (S5P_VA_CMU + 0x00504) | |
90 | #define EXYNOS5_CLKDIV_STATCPU0 (S5P_VA_CMU + 0x00600) | |
91 | #define EXYNOS5_CLKDIV_STATCPU1 (S5P_VA_CMU + 0x00604) |