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f7d77079 | 1 | /* |
7d30e8b3 | 2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
f40f91fe SK |
3 | * http://www.samsung.com |
4 | * | |
a125a17f | 5 | * EXYNOS4210 - CPU frequency scaling support |
f40f91fe SK |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
6c523c61 | 12 | #include <linux/module.h> |
f40f91fe SK |
13 | #include <linux/kernel.h> |
14 | #include <linux/err.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/slab.h> | |
f40f91fe SK |
18 | #include <linux/cpufreq.h> |
19 | ||
f40f91fe | 20 | #include <mach/regs-clock.h> |
a125a17f | 21 | #include <mach/cpufreq.h> |
f40f91fe | 22 | |
a125a17f JL |
23 | #define CPUFREQ_LEVEL_END L5 |
24 | ||
f40f91fe SK |
25 | static struct clk *cpu_clk; |
26 | static struct clk *moutcore; | |
27 | static struct clk *mout_mpll; | |
28 | static struct clk *mout_apll; | |
29 | ||
27f805dc | 30 | struct cpufreq_clkdiv { |
a125a17f | 31 | unsigned int index; |
27f805dc JL |
32 | unsigned int clkdiv; |
33 | }; | |
34 | ||
a125a17f JL |
35 | static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = { |
36 | 1250000, 1150000, 1050000, 975000, 950000, | |
f40f91fe SK |
37 | }; |
38 | ||
27f805dc | 39 | |
a125a17f JL |
40 | static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END]; |
41 | ||
42 | static struct cpufreq_frequency_table exynos4210_freq_table[] = { | |
ba9d7803 JL |
43 | {L0, 1200*1000}, |
44 | {L1, 1000*1000}, | |
45 | {L2, 800*1000}, | |
46 | {L3, 500*1000}, | |
47 | {L4, 200*1000}, | |
f40f91fe SK |
48 | {0, CPUFREQ_TABLE_END}, |
49 | }; | |
50 | ||
bf5ce054 | 51 | static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = { |
f40f91fe SK |
52 | /* |
53 | * Clock divider value for following | |
54 | * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, | |
55 | * DIVATB, DIVPCLK_DBG, DIVAPLL } | |
56 | */ | |
57 | ||
ba9d7803 JL |
58 | /* ARM L0: 1200MHz */ |
59 | { 0, 3, 7, 3, 4, 1, 7 }, | |
f40f91fe | 60 | |
ba9d7803 JL |
61 | /* ARM L1: 1000MHz */ |
62 | { 0, 3, 7, 3, 4, 1, 7 }, | |
f40f91fe | 63 | |
ba9d7803 JL |
64 | /* ARM L2: 800MHz */ |
65 | { 0, 3, 7, 3, 3, 1, 7 }, | |
f40f91fe | 66 | |
ba9d7803 JL |
67 | /* ARM L3: 500MHz */ |
68 | { 0, 3, 7, 3, 3, 1, 7 }, | |
69 | ||
70 | /* ARM L4: 200MHz */ | |
71 | { 0, 1, 3, 1, 3, 1, 0 }, | |
bf5ce054 | 72 | }; |
f40f91fe | 73 | |
bf5ce054 SJ |
74 | static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = { |
75 | /* | |
76 | * Clock divider value for following | |
77 | * { DIVCOPY, DIVHPM } | |
78 | */ | |
79 | ||
ba9d7803 JL |
80 | /* ARM L0: 1200MHz */ |
81 | { 5, 0 }, | |
82 | ||
83 | /* ARM L1: 1000MHz */ | |
84 | { 4, 0 }, | |
bf5ce054 | 85 | |
ba9d7803 | 86 | /* ARM L2: 800MHz */ |
bf5ce054 | 87 | { 3, 0 }, |
f40f91fe | 88 | |
ba9d7803 | 89 | /* ARM L3: 500MHz */ |
bf5ce054 SJ |
90 | { 3, 0 }, |
91 | ||
ba9d7803 | 92 | /* ARM L4: 200MHz */ |
bf5ce054 | 93 | { 3, 0 }, |
f40f91fe SK |
94 | }; |
95 | ||
a125a17f | 96 | static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = { |
ba9d7803 JL |
97 | /* APLL FOUT L0: 1200MHz */ |
98 | ((150 << 16) | (3 << 8) | 1), | |
99 | ||
100 | /* APLL FOUT L1: 1000MHz */ | |
bf5ce054 SJ |
101 | ((250 << 16) | (6 << 8) | 1), |
102 | ||
ba9d7803 | 103 | /* APLL FOUT L2: 800MHz */ |
bf5ce054 SJ |
104 | ((200 << 16) | (6 << 8) | 1), |
105 | ||
ba9d7803 JL |
106 | /* APLL FOUT L3: 500MHz */ |
107 | ((250 << 16) | (6 << 8) | 2), | |
bf5ce054 | 108 | |
ba9d7803 JL |
109 | /* APLL FOUT L4: 200MHz */ |
110 | ((200 << 16) | (6 << 8) | 3), | |
bf5ce054 SJ |
111 | }; |
112 | ||
a125a17f | 113 | static void exynos4210_set_clkdiv(unsigned int div_index) |
f40f91fe SK |
114 | { |
115 | unsigned int tmp; | |
116 | ||
117 | /* Change Divider - CPU0 */ | |
118 | ||
a125a17f | 119 | tmp = exynos4210_clkdiv_table[div_index].clkdiv; |
f40f91fe | 120 | |
09cee1ab | 121 | __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); |
f40f91fe SK |
122 | |
123 | do { | |
09cee1ab | 124 | tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU); |
f40f91fe SK |
125 | } while (tmp & 0x1111111); |
126 | ||
bf5ce054 SJ |
127 | /* Change Divider - CPU1 */ |
128 | ||
09cee1ab | 129 | tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1); |
bf5ce054 SJ |
130 | |
131 | tmp &= ~((0x7 << 4) | 0x7); | |
132 | ||
133 | tmp |= ((clkdiv_cpu1[div_index][0] << 4) | | |
134 | (clkdiv_cpu1[div_index][1] << 0)); | |
135 | ||
09cee1ab | 136 | __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); |
bf5ce054 SJ |
137 | |
138 | do { | |
09cee1ab | 139 | tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1); |
bf5ce054 | 140 | } while (tmp & 0x11); |
f40f91fe SK |
141 | } |
142 | ||
a125a17f | 143 | static void exynos4210_set_apll(unsigned int index) |
bf5ce054 SJ |
144 | { |
145 | unsigned int tmp; | |
146 | ||
147 | /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ | |
148 | clk_set_parent(moutcore, mout_mpll); | |
149 | ||
150 | do { | |
09cee1ab KK |
151 | tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU) |
152 | >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT); | |
bf5ce054 SJ |
153 | tmp &= 0x7; |
154 | } while (tmp != 0x2); | |
155 | ||
156 | /* 2. Set APLL Lock time */ | |
09cee1ab | 157 | __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK); |
bf5ce054 SJ |
158 | |
159 | /* 3. Change PLL PMS values */ | |
09cee1ab | 160 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
bf5ce054 | 161 | tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); |
a125a17f | 162 | tmp |= exynos4210_apll_pms_table[index]; |
09cee1ab | 163 | __raw_writel(tmp, EXYNOS4_APLL_CON0); |
bf5ce054 SJ |
164 | |
165 | /* 4. wait_lock_time */ | |
166 | do { | |
09cee1ab KK |
167 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
168 | } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT))); | |
bf5ce054 SJ |
169 | |
170 | /* 5. MUX_CORE_SEL = APLL */ | |
171 | clk_set_parent(moutcore, mout_apll); | |
172 | ||
173 | do { | |
09cee1ab KK |
174 | tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU); |
175 | tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK; | |
176 | } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); | |
bf5ce054 SJ |
177 | } |
178 | ||
a125a17f JL |
179 | bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index) |
180 | { | |
181 | unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8); | |
182 | unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8); | |
183 | ||
184 | return (old_pm == new_pm) ? 0 : 1; | |
185 | } | |
186 | ||
187 | static void exynos4210_set_frequency(unsigned int old_index, | |
188 | unsigned int new_index) | |
bf5ce054 SJ |
189 | { |
190 | unsigned int tmp; | |
191 | ||
192 | if (old_index > new_index) { | |
a125a17f | 193 | if (!exynos4210_pms_change(old_index, new_index)) { |
bf5ce054 | 194 | /* 1. Change the system clock divider values */ |
a125a17f | 195 | exynos4210_set_clkdiv(new_index); |
bf5ce054 SJ |
196 | |
197 | /* 2. Change just s value in apll m,p,s value */ | |
09cee1ab | 198 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
bf5ce054 | 199 | tmp &= ~(0x7 << 0); |
a125a17f | 200 | tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); |
09cee1ab | 201 | __raw_writel(tmp, EXYNOS4_APLL_CON0); |
bf5ce054 | 202 | } else { |
27f805dc JL |
203 | /* Clock Configuration Procedure */ |
204 | /* 1. Change the system clock divider values */ | |
a125a17f | 205 | exynos4210_set_clkdiv(new_index); |
27f805dc | 206 | /* 2. Change the apll m,p,s value */ |
a125a17f | 207 | exynos4210_set_apll(new_index); |
27f805dc JL |
208 | } |
209 | } else if (old_index < new_index) { | |
a125a17f | 210 | if (!exynos4210_pms_change(old_index, new_index)) { |
bf5ce054 | 211 | /* 1. Change just s value in apll m,p,s value */ |
09cee1ab | 212 | tmp = __raw_readl(EXYNOS4_APLL_CON0); |
bf5ce054 | 213 | tmp &= ~(0x7 << 0); |
a125a17f | 214 | tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); |
09cee1ab | 215 | __raw_writel(tmp, EXYNOS4_APLL_CON0); |
bf5ce054 | 216 | |
27f805dc | 217 | /* 2. Change the system clock divider values */ |
a125a17f | 218 | exynos4210_set_clkdiv(new_index); |
27f805dc JL |
219 | } else { |
220 | /* Clock Configuration Procedure */ | |
221 | /* 1. Change the apll m,p,s value */ | |
a125a17f | 222 | exynos4210_set_apll(new_index); |
bf5ce054 | 223 | /* 2. Change the system clock divider values */ |
a125a17f | 224 | exynos4210_set_clkdiv(new_index); |
bf5ce054 SJ |
225 | } |
226 | } | |
227 | } | |
228 | ||
a125a17f | 229 | int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) |
f40f91fe | 230 | { |
27f805dc JL |
231 | int i; |
232 | unsigned int tmp; | |
a125a17f | 233 | unsigned long rate; |
27f805dc | 234 | |
f40f91fe SK |
235 | cpu_clk = clk_get(NULL, "armclk"); |
236 | if (IS_ERR(cpu_clk)) | |
237 | return PTR_ERR(cpu_clk); | |
238 | ||
239 | moutcore = clk_get(NULL, "moutcore"); | |
240 | if (IS_ERR(moutcore)) | |
a125a17f | 241 | goto err_moutcore; |
f40f91fe SK |
242 | |
243 | mout_mpll = clk_get(NULL, "mout_mpll"); | |
244 | if (IS_ERR(mout_mpll)) | |
a125a17f JL |
245 | goto err_mout_mpll; |
246 | ||
247 | rate = clk_get_rate(mout_mpll) / 1000; | |
f40f91fe SK |
248 | |
249 | mout_apll = clk_get(NULL, "mout_apll"); | |
250 | if (IS_ERR(mout_apll)) | |
a125a17f | 251 | goto err_mout_apll; |
0073f538 | 252 | |
09cee1ab | 253 | tmp = __raw_readl(EXYNOS4_CLKDIV_CPU); |
27f805dc JL |
254 | |
255 | for (i = L0; i < CPUFREQ_LEVEL_END; i++) { | |
09cee1ab KK |
256 | tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK | |
257 | EXYNOS4_CLKDIV_CPU0_COREM0_MASK | | |
258 | EXYNOS4_CLKDIV_CPU0_COREM1_MASK | | |
259 | EXYNOS4_CLKDIV_CPU0_PERIPH_MASK | | |
260 | EXYNOS4_CLKDIV_CPU0_ATB_MASK | | |
261 | EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK | | |
262 | EXYNOS4_CLKDIV_CPU0_APLL_MASK); | |
263 | ||
264 | tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) | | |
265 | (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) | | |
266 | (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) | | |
267 | (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) | | |
268 | (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) | | |
269 | (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) | | |
270 | (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT)); | |
27f805dc | 271 | |
a125a17f | 272 | exynos4210_clkdiv_table[i].clkdiv = tmp; |
27f805dc JL |
273 | } |
274 | ||
a125a17f | 275 | info->mpll_freq_khz = rate; |
a125a17f | 276 | info->pll_safe_idx = L2; |
a125a17f JL |
277 | info->cpu_clk = cpu_clk; |
278 | info->volt_table = exynos4210_volt_table; | |
279 | info->freq_table = exynos4210_freq_table; | |
280 | info->set_freq = exynos4210_set_frequency; | |
281 | info->need_apll_change = exynos4210_pms_change; | |
f40f91fe | 282 | |
a125a17f | 283 | return 0; |
f40f91fe | 284 | |
a125a17f | 285 | err_mout_apll: |
184cddd1 | 286 | clk_put(mout_mpll); |
a125a17f | 287 | err_mout_mpll: |
184cddd1 | 288 | clk_put(moutcore); |
a125a17f | 289 | err_moutcore: |
184cddd1 | 290 | clk_put(cpu_clk); |
f40f91fe | 291 | |
a125a17f | 292 | pr_debug("%s: failed initialization\n", __func__); |
f40f91fe SK |
293 | return -EINVAL; |
294 | } | |
a125a17f | 295 | EXPORT_SYMBOL(exynos4210_cpufreq_init); |