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cpufreq: exynos: Check old & new frequency early
[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / exynos4x12-cpufreq.c
CommitLineData
a35c5051
JL		 1/*
2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * EXYNOS4X12 - CPU frequency scaling support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/slab.h>
18#include <linux/cpufreq.h>
19
20#include <mach/regs-clock.h>
21#include <mach/cpufreq.h>
22
23#define CPUFREQ_LEVEL_END (L13 + 1)
24
a35c5051
JL		 25static struct clk *cpu_clk;
26static struct clk *moutcore;
27static struct clk *mout_mpll;
28static struct clk *mout_apll;
29
30struct cpufreq_clkdiv {
31 unsigned int index;
32 unsigned int clkdiv;
33 unsigned int clkdiv1;
34};
35
36static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
37
38static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
39 {L0, 1500 * 1000},
40 {L1, 1400 * 1000},
41 {L2, 1300 * 1000},
42 {L3, 1200 * 1000},
43 {L4, 1100 * 1000},
44 {L5, 1000 * 1000},
45 {L6, 900 * 1000},
46 {L7, 800 * 1000},
47 {L8, 700 * 1000},
48 {L9, 600 * 1000},
49 {L10, 500 * 1000},
50 {L11, 400 * 1000},
51 {L12, 300 * 1000},
52 {L13, 200 * 1000},
53 {0, CPUFREQ_TABLE_END},
54};
55
56static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END];
57
58static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = {
59 /*
60 * Clock divider value for following
61 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
62 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
63 */
64 /* ARM L0: 1500 MHz */
65 { 0, 3, 7, 0, 6, 1, 2, 0 },
66
67 /* ARM L1: 1400 MHz */
68 { 0, 3, 7, 0, 6, 1, 2, 0 },
69
70 /* ARM L2: 1300 MHz */
71 { 0, 3, 7, 0, 5, 1, 2, 0 },
72
73 /* ARM L3: 1200 MHz */
74 { 0, 3, 7, 0, 5, 1, 2, 0 },
75
76 /* ARM L4: 1100 MHz */
77 { 0, 3, 6, 0, 4, 1, 2, 0 },
78
79 /* ARM L5: 1000 MHz */
80 { 0, 2, 5, 0, 4, 1, 1, 0 },
81
82 /* ARM L6: 900 MHz */
83 { 0, 2, 5, 0, 3, 1, 1, 0 },
84
85 /* ARM L7: 800 MHz */
86 { 0, 2, 5, 0, 3, 1, 1, 0 },
87
88 /* ARM L8: 700 MHz */
89 { 0, 2, 4, 0, 3, 1, 1, 0 },
90
91 /* ARM L9: 600 MHz */
92 { 0, 2, 4, 0, 3, 1, 1, 0 },
93
94 /* ARM L10: 500 MHz */
95 { 0, 2, 4, 0, 3, 1, 1, 0 },
96
97 /* ARM L11: 400 MHz */
98 { 0, 2, 4, 0, 3, 1, 1, 0 },
99
100 /* ARM L12: 300 MHz */
101 { 0, 2, 4, 0, 2, 1, 1, 0 },
102
103 /* ARM L13: 200 MHz */
104 { 0, 1, 3, 0, 1, 1, 1, 0 },
105};
106
107static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = {
108 /*
109 * Clock divider value for following
110 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
111 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 }
112 */
113 /* ARM L0: 1500 MHz */
114 { 0, 3, 7, 0, 6, 1, 2, 0 },
115
116 /* ARM L1: 1400 MHz */
117 { 0, 3, 7, 0, 6, 1, 2, 0 },
118
119 /* ARM L2: 1300 MHz */
120 { 0, 3, 7, 0, 5, 1, 2, 0 },
121
122 /* ARM L3: 1200 MHz */
123 { 0, 3, 7, 0, 5, 1, 2, 0 },
124
125 /* ARM L4: 1100 MHz */
126 { 0, 3, 6, 0, 4, 1, 2, 0 },
127
128 /* ARM L5: 1000 MHz */
129 { 0, 2, 5, 0, 4, 1, 1, 0 },
130
131 /* ARM L6: 900 MHz */
132 { 0, 2, 5, 0, 3, 1, 1, 0 },
133
134 /* ARM L7: 800 MHz */
135 { 0, 2, 5, 0, 3, 1, 1, 0 },
136
137 /* ARM L8: 700 MHz */
138 { 0, 2, 4, 0, 3, 1, 1, 0 },
139
140 /* ARM L9: 600 MHz */
141 { 0, 2, 4, 0, 3, 1, 1, 0 },
142
143 /* ARM L10: 500 MHz */
144 { 0, 2, 4, 0, 3, 1, 1, 0 },
145
146 /* ARM L11: 400 MHz */
147 { 0, 2, 4, 0, 3, 1, 1, 0 },
148
149 /* ARM L12: 300 MHz */
150 { 0, 2, 4, 0, 2, 1, 1, 0 },
151
152 /* ARM L13: 200 MHz */
153 { 0, 1, 3, 0, 1, 1, 1, 0 },
154};
155
156static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
157 /* Clock divider value for following
158 * { DIVCOPY, DIVHPM }
159 */
160 /* ARM L0: 1500 MHz */
161 { 6, 0 },
162
163 /* ARM L1: 1400 MHz */
164 { 6, 0 },
165
166 /* ARM L2: 1300 MHz */
167 { 5, 0 },
168
169 /* ARM L3: 1200 MHz */
170 { 5, 0 },
171
172 /* ARM L4: 1100 MHz */
173 { 4, 0 },
174
175 /* ARM L5: 1000 MHz */
176 { 4, 0 },
177
178 /* ARM L6: 900 MHz */
179 { 3, 0 },
180
181 /* ARM L7: 800 MHz */
182 { 3, 0 },
183
184 /* ARM L8: 700 MHz */
185 { 3, 0 },
186
187 /* ARM L9: 600 MHz */
188 { 3, 0 },
189
190 /* ARM L10: 500 MHz */
191 { 3, 0 },
192
193 /* ARM L11: 400 MHz */
194 { 3, 0 },
195
196 /* ARM L12: 300 MHz */
197 { 3, 0 },
198
199 /* ARM L13: 200 MHz */
200 { 3, 0 },
201};
202
203static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
204 /* Clock divider value for following
205 * { DIVCOPY, DIVHPM, DIVCORES }
206 */
207 /* ARM L0: 1500 MHz */
208 { 6, 0, 7 },
209
210 /* ARM L1: 1400 MHz */
211 { 6, 0, 6 },
212
213 /* ARM L2: 1300 MHz */
214 { 5, 0, 6 },
215
216 /* ARM L3: 1200 MHz */
217 { 5, 0, 5 },
218
219 /* ARM L4: 1100 MHz */
220 { 4, 0, 5 },
221
222 /* ARM L5: 1000 MHz */
223 { 4, 0, 4 },
224
225 /* ARM L6: 900 MHz */
226 { 3, 0, 4 },
227
228 /* ARM L7: 800 MHz */
229 { 3, 0, 3 },
230
231 /* ARM L8: 700 MHz */
232 { 3, 0, 3 },
233
234 /* ARM L9: 600 MHz */
235 { 3, 0, 2 },
236
237 /* ARM L10: 500 MHz */
238 { 3, 0, 2 },
239
240 /* ARM L11: 400 MHz */
241 { 3, 0, 1 },
242
243 /* ARM L12: 300 MHz */
244 { 3, 0, 1 },
245
246 /* ARM L13: 200 MHz */
247 { 3, 0, 0 },
248};
249
250static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
251 /* APLL FOUT L0: 1500 MHz */
252 ((250 << 16) | (4 << 8) | (0x0)),
253
254 /* APLL FOUT L1: 1400 MHz */
255 ((175 << 16) | (3 << 8) | (0x0)),
256
257 /* APLL FOUT L2: 1300 MHz */
258 ((325 << 16) | (6 << 8) | (0x0)),
259
260 /* APLL FOUT L3: 1200 MHz */
261 ((200 << 16) | (4 << 8) | (0x0)),
262
263 /* APLL FOUT L4: 1100 MHz */
264 ((275 << 16) | (6 << 8) | (0x0)),
265
266 /* APLL FOUT L5: 1000 MHz */
267 ((125 << 16) | (3 << 8) | (0x0)),
268
269 /* APLL FOUT L6: 900 MHz */
270 ((150 << 16) | (4 << 8) | (0x0)),
271
272 /* APLL FOUT L7: 800 MHz */
273 ((100 << 16) | (3 << 8) | (0x0)),
274
275 /* APLL FOUT L8: 700 MHz */
276 ((175 << 16) | (3 << 8) | (0x1)),
277
278 /* APLL FOUT L9: 600 MHz */
279 ((200 << 16) | (4 << 8) | (0x1)),
280
281 /* APLL FOUT L10: 500 MHz */
282 ((125 << 16) | (3 << 8) | (0x1)),
283
284 /* APLL FOUT L11 400 MHz */
285 ((100 << 16) | (3 << 8) | (0x1)),
286
287 /* APLL FOUT L12: 300 MHz */
288 ((200 << 16) | (4 << 8) | (0x2)),
289
290 /* APLL FOUT L13: 200 MHz */
291 ((100 << 16) | (3 << 8) | (0x2)),
292};
293
294static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
295 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
296 1000000, 987500, 975000, 950000, 925000, 900000, 900000
297};
298
299static void exynos4x12_set_clkdiv(unsigned int div_index)
300{
301 unsigned int tmp;
302 unsigned int stat_cpu1;
303
304 /* Change Divider - CPU0 */
305
306 tmp = exynos4x12_clkdiv_table[div_index].clkdiv;
307
308 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
309
310 while (__raw_readl(EXYNOS4_CLKDIV_STATCPU) & 0x11111111)
311 cpu_relax();
312
313 /* Change Divider - CPU1 */
314 tmp = exynos4x12_clkdiv_table[div_index].clkdiv1;
315
316 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
317 if (soc_is_exynos4212())
318 stat_cpu1 = 0x11;
319 else
320 stat_cpu1 = 0x111;
321
322 while (__raw_readl(EXYNOS4_CLKDIV_STATCPU1) & stat_cpu1)
323 cpu_relax();
324}
325
326static void exynos4x12_set_apll(unsigned int index)
327{
328 unsigned int tmp, pdiv;
329
330 /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
331 clk_set_parent(moutcore, mout_mpll);
332
333 do {
334 cpu_relax();
335 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
336 >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
337 tmp &= 0x7;
338 } while (tmp != 0x2);
339
340 /* 2. Set APLL Lock time */
341 pdiv = ((exynos4x12_apll_pms_table[index] >> 8) & 0x3f);
342
343 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
344
345 /* 3. Change PLL PMS values */
346 tmp = __raw_readl(EXYNOS4_APLL_CON0);
347 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
348 tmp |= exynos4x12_apll_pms_table[index];
349 __raw_writel(tmp, EXYNOS4_APLL_CON0);
350
351 /* 4. wait_lock_time */
352 do {
353 cpu_relax();
354 tmp = __raw_readl(EXYNOS4_APLL_CON0);
355 } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
356
357 /* 5. MUX_CORE_SEL = APLL */
358 clk_set_parent(moutcore, mout_apll);
359
360 do {
361 cpu_relax();
362 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
363 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
364 } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
365}
366
367bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
368{
369 unsigned int old_pm = exynos4x12_apll_pms_table[old_index] >> 8;
370 unsigned int new_pm = exynos4x12_apll_pms_table[new_index] >> 8;
371
372 return (old_pm == new_pm) ? 0 : 1;
373}
374
375static void exynos4x12_set_frequency(unsigned int old_index,
376 unsigned int new_index)
377{
378 unsigned int tmp;
379
380 if (old_index > new_index) {
381 if (!exynos4x12_pms_change(old_index, new_index)) {
382 /* 1. Change the system clock divider values */
383 exynos4x12_set_clkdiv(new_index);
384 /* 2. Change just s value in apll m,p,s value */
385 tmp = __raw_readl(EXYNOS4_APLL_CON0);
386 tmp &= ~(0x7 << 0);
387 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
388 __raw_writel(tmp, EXYNOS4_APLL_CON0);
389
390 } else {
391 /* Clock Configuration Procedure */
392 /* 1. Change the system clock divider values */
393 exynos4x12_set_clkdiv(new_index);
394 /* 2. Change the apll m,p,s value */
395 exynos4x12_set_apll(new_index);
396 }
397 } else if (old_index < new_index) {
398 if (!exynos4x12_pms_change(old_index, new_index)) {
399 /* 1. Change just s value in apll m,p,s value */
400 tmp = __raw_readl(EXYNOS4_APLL_CON0);
401 tmp &= ~(0x7 << 0);
402 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7);
403 __raw_writel(tmp, EXYNOS4_APLL_CON0);
404 /* 2. Change the system clock divider values */
405 exynos4x12_set_clkdiv(new_index);
406 } else {
407 /* Clock Configuration Procedure */
408 /* 1. Change the apll m,p,s value */
409 exynos4x12_set_apll(new_index);
410 /* 2. Change the system clock divider values */
411 exynos4x12_set_clkdiv(new_index);
412 }
413 }
414}
415
416static void __init set_volt_table(void)
417{
418 unsigned int i;
419
a35c5051
JL		 420 /* Not supported */
421 exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
422
423 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
424 exynos4x12_volt_table[i] = asv_voltage_4x12[i];
425}
426
427int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
428{
429 int i;
430 unsigned int tmp;
431 unsigned long rate;
432
433 set_volt_table();
434
435 cpu_clk = clk_get(NULL, "armclk");
436 if (IS_ERR(cpu_clk))
437 return PTR_ERR(cpu_clk);
438
439 moutcore = clk_get(NULL, "moutcore");
440 if (IS_ERR(moutcore))
441 goto err_moutcore;
442
443 mout_mpll = clk_get(NULL, "mout_mpll");
444 if (IS_ERR(mout_mpll))
445 goto err_mout_mpll;
446
447 rate = clk_get_rate(mout_mpll) / 1000;
448
449 mout_apll = clk_get(NULL, "mout_apll");
450 if (IS_ERR(mout_apll))
451 goto err_mout_apll;
452
453 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
454
455 exynos4x12_clkdiv_table[i].index = i;
456
457 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
458
459 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
460 EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
461 EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
462 EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
463 EXYNOS4_CLKDIV_CPU0_ATB_MASK |
464 EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
465 EXYNOS4_CLKDIV_CPU0_APLL_MASK);
466
467 if (soc_is_exynos4212()) {
468 tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
469 (clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
470 (clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
471 (clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
472 (clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
473 (clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
474 (clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
475 } else {
476 tmp &= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
477
478 tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
479 (clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
480 (clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
481 (clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
482 (clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
483 (clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
484 (clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
485 (clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
486 }
487
488 exynos4x12_clkdiv_table[i].clkdiv = tmp;
489
490 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
491
492 if (soc_is_exynos4212()) {
493 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
494 EXYNOS4_CLKDIV_CPU1_HPM_MASK);
495 tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
496 (clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
497 } else {
498 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
499 EXYNOS4_CLKDIV_CPU1_HPM_MASK |
500 EXYNOS4_CLKDIV_CPU1_CORES_MASK);
501 tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
502 (clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
503 (clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
504 }
505 exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
506 }
507
508 info->mpll_freq_khz = rate;
a35c5051 509 info->pll_safe_idx = L7;
a35c5051
JL		 510 info->cpu_clk = cpu_clk;
511 info->volt_table = exynos4x12_volt_table;
512 info->freq_table = exynos4x12_freq_table;
513 info->set_freq = exynos4x12_set_frequency;
514 info->need_apll_change = exynos4x12_pms_change;
515
516 return 0;
517
518err_mout_apll:
519 clk_put(mout_mpll);
520err_mout_mpll:
521 clk_put(moutcore);
522err_moutcore:
523 clk_put(cpu_clk);
524
525 pr_debug("%s: failed initialization\n", __func__);
526 return -EINVAL;
527}
528EXPORT_SYMBOL(exynos4x12_cpufreq_init);
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