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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Cyrix MediaGX and NatSemi Geode Suspend Modulation | |
3 | * (C) 2002 Zwane Mwaikambo <zwane@commfireservices.com> | |
4 | * (C) 2002 Hiroshi Miura <miura@da-cha.org> | |
5 | * All Rights Reserved | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
32ee8c3e | 9 | * version 2 as published by the Free Software Foundation |
1da177e4 LT |
10 | * |
11 | * The author(s) of this software shall not be held liable for damages | |
12 | * of any nature resulting due to the use of this software. This | |
13 | * software is provided AS-IS with no warranties. | |
32ee8c3e | 14 | * |
27b46d76 | 15 | * Theoretical note: |
1da177e4 LT |
16 | * |
17 | * (see Geode(tm) CS5530 manual (rev.4.1) page.56) | |
18 | * | |
19 | * CPU frequency control on NatSemi Geode GX1/GXLV processor and CS55x0 | |
27b46d76 | 20 | * are based on Suspend Modulation. |
1da177e4 LT |
21 | * |
22 | * Suspend Modulation works by asserting and de-asserting the SUSP# pin | |
23 | * to CPU(GX1/GXLV) for configurable durations. When asserting SUSP# | |
32ee8c3e | 24 | * the CPU enters an idle state. GX1 stops its core clock when SUSP# is |
1da177e4 LT |
25 | * asserted then power consumption is reduced. |
26 | * | |
32ee8c3e | 27 | * Suspend Modulation's OFF/ON duration are configurable |
1da177e4 LT |
28 | * with 'Suspend Modulation OFF Count Register' |
29 | * and 'Suspend Modulation ON Count Register'. | |
32ee8c3e | 30 | * These registers are 8bit counters that represent the number of |
1da177e4 LT |
31 | * 32us intervals which the SUSP# pin is asserted(ON)/de-asserted(OFF) |
32 | * to the processor. | |
33 | * | |
32ee8c3e DJ |
34 | * These counters define a ratio which is the effective frequency |
35 | * of operation of the system. | |
1da177e4 LT |
36 | * |
37 | * OFF Count | |
38 | * F_eff = Fgx * ---------------------- | |
39 | * OFF Count + ON Count | |
40 | * | |
41 | * 0 <= On Count, Off Count <= 255 | |
42 | * | |
32ee8c3e | 43 | * From these limits, we can get register values |
1da177e4 LT |
44 | * |
45 | * off_duration + on_duration <= MAX_DURATION | |
46 | * on_duration = off_duration * (stock_freq - freq) / freq | |
47 | * | |
32ee8c3e DJ |
48 | * off_duration = (freq * DURATION) / stock_freq |
49 | * on_duration = DURATION - off_duration | |
1da177e4 LT |
50 | * |
51 | * | |
52 | *--------------------------------------------------------------------------- | |
53 | * | |
54 | * ChangeLog: | |
32ee8c3e DJ |
55 | * Dec. 12, 2003 Hiroshi Miura <miura@da-cha.org> |
56 | * - fix on/off register mistake | |
57 | * - fix cpu_khz calc when it stops cpu modulation. | |
1da177e4 | 58 | * |
32ee8c3e DJ |
59 | * Dec. 11, 2002 Hiroshi Miura <miura@da-cha.org> |
60 | * - rewrite for Cyrix MediaGX Cx5510/5520 and | |
1da177e4 LT |
61 | * NatSemi Geode Cs5530(A). |
62 | * | |
63 | * Jul. ??, 2002 Zwane Mwaikambo <zwane@commfireservices.com> | |
64 | * - cs5530_mod patch for 2.4.19-rc1. | |
65 | * | |
66 | *--------------------------------------------------------------------------- | |
67 | * | |
68 | * Todo | |
69 | * Test on machines with 5510, 5530, 5530A | |
70 | */ | |
71 | ||
72 | /************************************************************************ | |
73 | * Suspend Modulation - Definitions * | |
74 | ************************************************************************/ | |
75 | ||
76 | #include <linux/kernel.h> | |
32ee8c3e | 77 | #include <linux/module.h> |
1da177e4 LT |
78 | #include <linux/init.h> |
79 | #include <linux/smp.h> | |
80 | #include <linux/cpufreq.h> | |
81 | #include <linux/pci.h> | |
00f6a235 | 82 | #include <linux/errno.h> |
5a0e3ad6 | 83 | #include <linux/slab.h> |
00f6a235 | 84 | |
fa8031ae | 85 | #include <asm/cpu_device_id.h> |
f25f64ed | 86 | #include <asm/processor-cyrix.h> |
1da177e4 LT |
87 | |
88 | /* PCI config registers, all at F0 */ | |
32ee8c3e DJ |
89 | #define PCI_PMER1 0x80 /* power management enable register 1 */ |
90 | #define PCI_PMER2 0x81 /* power management enable register 2 */ | |
91 | #define PCI_PMER3 0x82 /* power management enable register 3 */ | |
92 | #define PCI_IRQTC 0x8c /* irq speedup timer counter register:typical 2 to 4ms */ | |
93 | #define PCI_VIDTC 0x8d /* video speedup timer counter register: typical 50 to 100ms */ | |
94 | #define PCI_MODOFF 0x94 /* suspend modulation OFF counter register, 1 = 32us */ | |
95 | #define PCI_MODON 0x95 /* suspend modulation ON counter register */ | |
96 | #define PCI_SUSCFG 0x96 /* suspend configuration register */ | |
1da177e4 LT |
97 | |
98 | /* PMER1 bits */ | |
32ee8c3e DJ |
99 | #define GPM (1<<0) /* global power management */ |
100 | #define GIT (1<<1) /* globally enable PM device idle timers */ | |
101 | #define GTR (1<<2) /* globally enable IO traps */ | |
102 | #define IRQ_SPDUP (1<<3) /* disable clock throttle during interrupt handling */ | |
103 | #define VID_SPDUP (1<<4) /* disable clock throttle during vga video handling */ | |
1da177e4 LT |
104 | |
105 | /* SUSCFG bits */ | |
32ee8c3e | 106 | #define SUSMOD (1<<0) /* enable/disable suspend modulation */ |
27b46d76 | 107 | /* the below is supported only with cs5530 (after rev.1.2)/cs5530A */ |
32ee8c3e DJ |
108 | #define SMISPDUP (1<<1) /* select how SMI re-enable suspend modulation: */ |
109 | /* IRQTC timer or read SMI speedup disable reg.(F1BAR[08-09h]) */ | |
110 | #define SUSCFG (1<<2) /* enable powering down a GXLV processor. "Special 3Volt Suspend" mode */ | |
27b46d76 | 111 | /* the below is supported only with cs5530A */ |
32ee8c3e DJ |
112 | #define PWRSVE_ISA (1<<3) /* stop ISA clock */ |
113 | #define PWRSVE (1<<4) /* active idle */ | |
1da177e4 LT |
114 | |
115 | struct gxfreq_params { | |
116 | u8 on_duration; | |
117 | u8 off_duration; | |
118 | u8 pci_suscfg; | |
119 | u8 pci_pmer1; | |
120 | u8 pci_pmer2; | |
1da177e4 LT |
121 | struct pci_dev *cs55x0; |
122 | }; | |
123 | ||
124 | static struct gxfreq_params *gx_params; | |
125 | static int stock_freq; | |
126 | ||
127 | /* PCI bus clock - defaults to 30.000 if cpu_khz is not available */ | |
00f6a235 DJ |
128 | static int pci_busclk; |
129 | module_param(pci_busclk, int, 0444); | |
1da177e4 LT |
130 | |
131 | /* maximum duration for which the cpu may be suspended | |
132 | * (32us * MAX_DURATION). If no parameter is given, this defaults | |
32ee8c3e | 133 | * to 255. |
1da177e4 LT |
134 | * Note that this leads to a maximum of 8 ms(!) where the CPU clock |
135 | * is suspended -- processing power is just 0.39% of what it used to be, | |
136 | * though. 781.25 kHz(!) for a 200 MHz processor -- wow. */ | |
137 | static int max_duration = 255; | |
00f6a235 | 138 | module_param(max_duration, int, 0444); |
1da177e4 LT |
139 | |
140 | /* For the default policy, we want at least some processing power | |
141 | * - let's say 5%. (min = maxfreq / POLICY_MIN_DIV) | |
142 | */ | |
143 | #define POLICY_MIN_DIV 20 | |
144 | ||
145 | ||
1da177e4 | 146 | /** |
32ee8c3e DJ |
147 | * we can detect a core multipiler from dir0_lsb |
148 | * from GX1 datasheet p.56, | |
149 | * MULT[3:0]: | |
150 | * 0000 = SYSCLK multiplied by 4 (test only) | |
151 | * 0001 = SYSCLK multiplied by 10 | |
152 | * 0010 = SYSCLK multiplied by 4 | |
153 | * 0011 = SYSCLK multiplied by 6 | |
154 | * 0100 = SYSCLK multiplied by 9 | |
155 | * 0101 = SYSCLK multiplied by 5 | |
156 | * 0110 = SYSCLK multiplied by 7 | |
157 | * 0111 = SYSCLK multiplied by 8 | |
1da177e4 LT |
158 | * of 33.3MHz |
159 | **/ | |
160 | static int gx_freq_mult[16] = { | |
161 | 4, 10, 4, 6, 9, 5, 7, 8, | |
162 | 0, 0, 0, 0, 0, 0, 0, 0 | |
163 | }; | |
164 | ||
165 | ||
166 | /**************************************************************** | |
32ee8c3e | 167 | * Low Level chipset interface * |
1da177e4 LT |
168 | ****************************************************************/ |
169 | static struct pci_device_id gx_chipset_tbl[] __initdata = { | |
55c789bb PH |
170 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY), }, |
171 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), }, | |
172 | { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, | |
32ee8c3e | 173 | { 0, }, |
1da177e4 | 174 | }; |
b3012e12 | 175 | MODULE_DEVICE_TABLE(pci, gx_chipset_tbl); |
1da177e4 | 176 | |
00f6a235 DJ |
177 | static void gx_write_byte(int reg, int value) |
178 | { | |
179 | pci_write_config_byte(gx_params->cs55x0, reg, value); | |
180 | } | |
181 | ||
1da177e4 | 182 | /** |
32ee8c3e | 183 | * gx_detect_chipset: |
1da177e4 LT |
184 | * |
185 | **/ | |
af97385a | 186 | static struct pci_dev * __init gx_detect_chipset(void) |
1da177e4 LT |
187 | { |
188 | struct pci_dev *gx_pci = NULL; | |
189 | ||
1da177e4 | 190 | /* detect which companion chip is used */ |
ccc5638a | 191 | for_each_pci_dev(gx_pci) { |
32ee8c3e | 192 | if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL) |
1da177e4 | 193 | return gx_pci; |
1da177e4 LT |
194 | } |
195 | ||
2d06d8c4 | 196 | pr_debug("error: no supported chipset found!\n"); |
1da177e4 LT |
197 | return NULL; |
198 | } | |
199 | ||
200 | /** | |
32ee8c3e | 201 | * gx_get_cpuspeed: |
1da177e4 | 202 | * |
00f6a235 DJ |
203 | * Finds out at which efficient frequency the Cyrix MediaGX/NatSemi |
204 | * Geode CPU runs. | |
1da177e4 LT |
205 | */ |
206 | static unsigned int gx_get_cpuspeed(unsigned int cpu) | |
207 | { | |
32ee8c3e | 208 | if ((gx_params->pci_suscfg & SUSMOD) == 0) |
1da177e4 LT |
209 | return stock_freq; |
210 | ||
32ee8c3e | 211 | return (stock_freq * gx_params->off_duration) |
1da177e4 LT |
212 | / (gx_params->on_duration + gx_params->off_duration); |
213 | } | |
214 | ||
215 | /** | |
216 | * gx_validate_speed: | |
217 | * determine current cpu speed | |
32ee8c3e DJ |
218 | * |
219 | **/ | |
1da177e4 | 220 | |
00f6a235 DJ |
221 | static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, |
222 | u8 *off_duration) | |
1da177e4 LT |
223 | { |
224 | unsigned int i; | |
225 | u8 tmp_on, tmp_off; | |
226 | int old_tmp_freq = stock_freq; | |
227 | int tmp_freq; | |
228 | ||
00f6a235 DJ |
229 | *off_duration = 1; |
230 | *on_duration = 0; | |
1da177e4 | 231 | |
00f6a235 | 232 | for (i = max_duration; i > 0; i--) { |
32ee8c3e | 233 | tmp_off = ((khz * i) / stock_freq) & 0xff; |
1da177e4 LT |
234 | tmp_on = i - tmp_off; |
235 | tmp_freq = (stock_freq * tmp_off) / i; | |
236 | /* if this relation is closer to khz, use this. If it's equal, | |
237 | * prefer it, too - lower latency */ | |
238 | if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { | |
239 | *on_duration = tmp_on; | |
240 | *off_duration = tmp_off; | |
241 | old_tmp_freq = tmp_freq; | |
242 | } | |
243 | } | |
244 | ||
245 | return old_tmp_freq; | |
246 | } | |
247 | ||
248 | ||
249 | /** | |
32ee8c3e DJ |
250 | * gx_set_cpuspeed: |
251 | * set cpu speed in khz. | |
1da177e4 LT |
252 | **/ |
253 | ||
b43a7ffb | 254 | static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) |
1da177e4 | 255 | { |
32ee8c3e | 256 | u8 suscfg, pmer1; |
1da177e4 LT |
257 | unsigned int new_khz; |
258 | unsigned long flags; | |
259 | struct cpufreq_freqs freqs; | |
260 | ||
1da177e4 LT |
261 | freqs.old = gx_get_cpuspeed(0); |
262 | ||
00f6a235 DJ |
263 | new_khz = gx_validate_speed(khz, &gx_params->on_duration, |
264 | &gx_params->off_duration); | |
1da177e4 LT |
265 | |
266 | freqs.new = new_khz; | |
267 | ||
b43a7ffb | 268 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
1da177e4 LT |
269 | local_irq_save(flags); |
270 | ||
00f6a235 DJ |
271 | if (new_khz != stock_freq) { |
272 | /* if new khz == 100% of CPU speed, it is special case */ | |
1da177e4 LT |
273 | switch (gx_params->cs55x0->device) { |
274 | case PCI_DEVICE_ID_CYRIX_5530_LEGACY: | |
275 | pmer1 = gx_params->pci_pmer1 | IRQ_SPDUP | VID_SPDUP; | |
276 | /* FIXME: need to test other values -- Zwane,Miura */ | |
00f6a235 DJ |
277 | /* typical 2 to 4ms */ |
278 | gx_write_byte(PCI_IRQTC, 4); | |
279 | /* typical 50 to 100ms */ | |
280 | gx_write_byte(PCI_VIDTC, 100); | |
281 | gx_write_byte(PCI_PMER1, pmer1); | |
282 | ||
283 | if (gx_params->cs55x0->revision < 0x10) { | |
284 | /* CS5530(rev 1.2, 1.3) */ | |
285 | suscfg = gx_params->pci_suscfg|SUSMOD; | |
286 | } else { | |
287 | /* CS5530A,B.. */ | |
288 | suscfg = gx_params->pci_suscfg|SUSMOD|PWRSVE; | |
1da177e4 LT |
289 | } |
290 | break; | |
291 | case PCI_DEVICE_ID_CYRIX_5520: | |
292 | case PCI_DEVICE_ID_CYRIX_5510: | |
293 | suscfg = gx_params->pci_suscfg | SUSMOD; | |
294 | break; | |
295 | default: | |
296 | local_irq_restore(flags); | |
2d06d8c4 | 297 | pr_debug("fatal: try to set unknown chipset.\n"); |
1da177e4 LT |
298 | return; |
299 | } | |
300 | } else { | |
301 | suscfg = gx_params->pci_suscfg & ~(SUSMOD); | |
302 | gx_params->off_duration = 0; | |
303 | gx_params->on_duration = 0; | |
2d06d8c4 | 304 | pr_debug("suspend modulation disabled: cpu runs 100%% speed.\n"); |
1da177e4 LT |
305 | } |
306 | ||
00f6a235 DJ |
307 | gx_write_byte(PCI_MODOFF, gx_params->off_duration); |
308 | gx_write_byte(PCI_MODON, gx_params->on_duration); | |
1da177e4 | 309 | |
00f6a235 | 310 | gx_write_byte(PCI_SUSCFG, suscfg); |
32ee8c3e | 311 | pci_read_config_byte(gx_params->cs55x0, PCI_SUSCFG, &suscfg); |
1da177e4 | 312 | |
32ee8c3e | 313 | local_irq_restore(flags); |
1da177e4 LT |
314 | |
315 | gx_params->pci_suscfg = suscfg; | |
316 | ||
b43a7ffb | 317 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
1da177e4 | 318 | |
2d06d8c4 | 319 | pr_debug("suspend modulation w/ duration of ON:%d us, OFF:%d us\n", |
32ee8c3e | 320 | gx_params->on_duration * 32, gx_params->off_duration * 32); |
2d06d8c4 | 321 | pr_debug("suspend modulation w/ clock speed: %d kHz.\n", freqs.new); |
1da177e4 LT |
322 | } |
323 | ||
324 | /**************************************************************** | |
325 | * High level functions * | |
326 | ****************************************************************/ | |
327 | ||
328 | /* | |
32ee8c3e | 329 | * cpufreq_gx_verify: test if frequency range is valid |
1da177e4 | 330 | * |
32ee8c3e DJ |
331 | * This function checks if a given frequency range in kHz is valid |
332 | * for the hardware supported by the driver. | |
1da177e4 LT |
333 | */ |
334 | ||
335 | static int cpufreq_gx_verify(struct cpufreq_policy *policy) | |
336 | { | |
337 | unsigned int tmp_freq = 0; | |
338 | u8 tmp1, tmp2; | |
339 | ||
32ee8c3e DJ |
340 | if (!stock_freq || !policy) |
341 | return -EINVAL; | |
1da177e4 LT |
342 | |
343 | policy->cpu = 0; | |
00f6a235 DJ |
344 | cpufreq_verify_within_limits(policy, (stock_freq / max_duration), |
345 | stock_freq); | |
1da177e4 LT |
346 | |
347 | /* it needs to be assured that at least one supported frequency is | |
348 | * within policy->min and policy->max. If it is not, policy->max | |
349 | * needs to be increased until one freuqency is supported. | |
32ee8c3e | 350 | * policy->min may not be decreased, though. This way we guarantee a |
1da177e4 LT |
351 | * specific processing capacity. |
352 | */ | |
353 | tmp_freq = gx_validate_speed(policy->min, &tmp1, &tmp2); | |
32ee8c3e | 354 | if (tmp_freq < policy->min) |
1da177e4 LT |
355 | tmp_freq += stock_freq / max_duration; |
356 | policy->min = tmp_freq; | |
32ee8c3e | 357 | if (policy->min > policy->max) |
1da177e4 LT |
358 | policy->max = tmp_freq; |
359 | tmp_freq = gx_validate_speed(policy->max, &tmp1, &tmp2); | |
360 | if (tmp_freq > policy->max) | |
361 | tmp_freq -= stock_freq / max_duration; | |
362 | policy->max = tmp_freq; | |
363 | if (policy->max < policy->min) | |
364 | policy->max = policy->min; | |
00f6a235 DJ |
365 | cpufreq_verify_within_limits(policy, (stock_freq / max_duration), |
366 | stock_freq); | |
32ee8c3e | 367 | |
1da177e4 LT |
368 | return 0; |
369 | } | |
370 | ||
371 | /* | |
32ee8c3e | 372 | * cpufreq_gx_target: |
1da177e4 LT |
373 | * |
374 | */ | |
375 | static int cpufreq_gx_target(struct cpufreq_policy *policy, | |
376 | unsigned int target_freq, | |
377 | unsigned int relation) | |
378 | { | |
379 | u8 tmp1, tmp2; | |
380 | unsigned int tmp_freq; | |
381 | ||
32ee8c3e DJ |
382 | if (!stock_freq || !policy) |
383 | return -EINVAL; | |
1da177e4 LT |
384 | |
385 | policy->cpu = 0; | |
386 | ||
387 | tmp_freq = gx_validate_speed(target_freq, &tmp1, &tmp2); | |
388 | while (tmp_freq < policy->min) { | |
389 | tmp_freq += stock_freq / max_duration; | |
390 | tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2); | |
391 | } | |
392 | while (tmp_freq > policy->max) { | |
393 | tmp_freq -= stock_freq / max_duration; | |
394 | tmp_freq = gx_validate_speed(tmp_freq, &tmp1, &tmp2); | |
395 | } | |
396 | ||
b43a7ffb | 397 | gx_set_cpuspeed(policy, tmp_freq); |
1da177e4 LT |
398 | |
399 | return 0; | |
400 | } | |
401 | ||
402 | static int cpufreq_gx_cpu_init(struct cpufreq_policy *policy) | |
403 | { | |
cd590643 | 404 | unsigned int maxfreq; |
1da177e4 LT |
405 | |
406 | if (!policy || policy->cpu != 0) | |
407 | return -ENODEV; | |
408 | ||
409 | /* determine maximum frequency */ | |
00f6a235 | 410 | if (pci_busclk) |
1da177e4 | 411 | maxfreq = pci_busclk * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f]; |
00f6a235 | 412 | else if (cpu_khz) |
1da177e4 | 413 | maxfreq = cpu_khz; |
00f6a235 | 414 | else |
1da177e4 | 415 | maxfreq = 30000 * gx_freq_mult[getCx86(CX86_DIR1) & 0x0f]; |
00f6a235 | 416 | |
1da177e4 | 417 | stock_freq = maxfreq; |
1da177e4 | 418 | |
2d06d8c4 | 419 | pr_debug("cpu max frequency is %d.\n", maxfreq); |
1da177e4 LT |
420 | |
421 | /* setup basic struct for cpufreq API */ | |
422 | policy->cpu = 0; | |
423 | ||
424 | if (max_duration < POLICY_MIN_DIV) | |
425 | policy->min = maxfreq / max_duration; | |
426 | else | |
427 | policy->min = maxfreq / POLICY_MIN_DIV; | |
428 | policy->max = maxfreq; | |
1da177e4 LT |
429 | policy->cpuinfo.min_freq = maxfreq / max_duration; |
430 | policy->cpuinfo.max_freq = maxfreq; | |
431 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
432 | ||
433 | return 0; | |
434 | } | |
435 | ||
32ee8c3e | 436 | /* |
1da177e4 LT |
437 | * cpufreq_gx_init: |
438 | * MediaGX/Geode GX initialize cpufreq driver | |
439 | */ | |
221dee28 | 440 | static struct cpufreq_driver gx_suspmod_driver = { |
1da177e4 LT |
441 | .get = gx_get_cpuspeed, |
442 | .verify = cpufreq_gx_verify, | |
443 | .target = cpufreq_gx_target, | |
444 | .init = cpufreq_gx_cpu_init, | |
445 | .name = "gx-suspmod", | |
1da177e4 LT |
446 | }; |
447 | ||
448 | static int __init cpufreq_gx_init(void) | |
449 | { | |
450 | int ret; | |
451 | struct gxfreq_params *params; | |
452 | struct pci_dev *gx_pci; | |
1da177e4 LT |
453 | |
454 | /* Test if we have the right hardware */ | |
00f6a235 DJ |
455 | gx_pci = gx_detect_chipset(); |
456 | if (gx_pci == NULL) | |
1da177e4 LT |
457 | return -ENODEV; |
458 | ||
459 | /* check whether module parameters are sane */ | |
460 | if (max_duration > 0xff) | |
461 | max_duration = 0xff; | |
462 | ||
2d06d8c4 | 463 | pr_debug("geode suspend modulation available.\n"); |
1da177e4 | 464 | |
d5b73cd8 | 465 | params = kzalloc(sizeof(*params), GFP_KERNEL); |
1da177e4 LT |
466 | if (params == NULL) |
467 | return -ENOMEM; | |
1da177e4 LT |
468 | |
469 | params->cs55x0 = gx_pci; | |
470 | gx_params = params; | |
471 | ||
472 | /* keep cs55x0 configurations */ | |
473 | pci_read_config_byte(params->cs55x0, PCI_SUSCFG, &(params->pci_suscfg)); | |
474 | pci_read_config_byte(params->cs55x0, PCI_PMER1, &(params->pci_pmer1)); | |
475 | pci_read_config_byte(params->cs55x0, PCI_PMER2, &(params->pci_pmer2)); | |
476 | pci_read_config_byte(params->cs55x0, PCI_MODON, &(params->on_duration)); | |
00f6a235 DJ |
477 | pci_read_config_byte(params->cs55x0, PCI_MODOFF, |
478 | &(params->off_duration)); | |
1da177e4 | 479 | |
00f6a235 DJ |
480 | ret = cpufreq_register_driver(&gx_suspmod_driver); |
481 | if (ret) { | |
1da177e4 LT |
482 | kfree(params); |
483 | return ret; /* register error! */ | |
484 | } | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | static void __exit cpufreq_gx_exit(void) | |
490 | { | |
491 | cpufreq_unregister_driver(&gx_suspmod_driver); | |
492 | pci_dev_put(gx_params->cs55x0); | |
493 | kfree(gx_params); | |
494 | } | |
495 | ||
00f6a235 DJ |
496 | MODULE_AUTHOR("Hiroshi Miura <miura@da-cha.org>"); |
497 | MODULE_DESCRIPTION("Cpufreq driver for Cyrix MediaGX and NatSemi Geode"); | |
498 | MODULE_LICENSE("GPL"); | |
1da177e4 LT |
499 | |
500 | module_init(cpufreq_gx_init); | |
501 | module_exit(cpufreq_gx_exit); | |
502 |