]>
Commit | Line | Data |
---|---|---|
93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
55687da1 | 22 | #include <linux/sched/cpufreq.h> |
93f0822d DB |
23 | #include <linux/list.h> |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
d77d4888 | 40 | #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) |
eabd22c6 | 41 | |
001c76f0 | 42 | #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 |
1b72e7fd | 43 | #define INTEL_CPUFREQ_TRANSITION_DELAY 500 |
001c76f0 | 44 | |
9522a2ff SP |
45 | #ifdef CONFIG_ACPI |
46 | #include <acpi/processor.h> | |
17669006 | 47 | #include <acpi/cppc_acpi.h> |
9522a2ff SP |
48 | #endif |
49 | ||
f0fe3cd7 | 50 | #define FRAC_BITS 8 |
93f0822d DB |
51 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
52 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 53 | |
a1c9787d RW |
54 | #define EXT_BITS 6 |
55 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
d5dd33d9 SP |
56 | #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) |
57 | #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) | |
a1c9787d | 58 | |
93f0822d DB |
59 | static inline int32_t mul_fp(int32_t x, int32_t y) |
60 | { | |
61 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
62 | } | |
63 | ||
7180dddf | 64 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 65 | { |
7180dddf | 66 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
67 | } |
68 | ||
d022a65e DB |
69 | static inline int ceiling_fp(int32_t x) |
70 | { | |
71 | int mask, ret; | |
72 | ||
73 | ret = fp_toint(x); | |
74 | mask = (1 << FRAC_BITS) - 1; | |
75 | if (x & mask) | |
76 | ret += 1; | |
77 | return ret; | |
78 | } | |
79 | ||
ff35f02e RW |
80 | static inline int32_t percent_fp(int percent) |
81 | { | |
82 | return div_fp(percent, 100); | |
83 | } | |
84 | ||
a1c9787d RW |
85 | static inline u64 mul_ext_fp(u64 x, u64 y) |
86 | { | |
87 | return (x * y) >> EXT_FRAC_BITS; | |
88 | } | |
89 | ||
90 | static inline u64 div_ext_fp(u64 x, u64 y) | |
91 | { | |
92 | return div64_u64(x << EXT_FRAC_BITS, y); | |
93 | } | |
94 | ||
e4c204ce RW |
95 | static inline int32_t percent_ext_fp(int percent) |
96 | { | |
97 | return div_ext_fp(percent, 100); | |
98 | } | |
99 | ||
13ad7701 SP |
100 | /** |
101 | * struct sample - Store performance sample | |
a1c9787d | 102 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
103 | * performance during last sample period |
104 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 105 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
106 | * to account for cpu idle period |
107 | * @aperf: Difference of actual performance frequency clock count | |
108 | * read from APERF MSR between last and current sample | |
109 | * @mperf: Difference of maximum performance frequency clock count | |
110 | * read from MPERF MSR between last and current sample | |
111 | * @tsc: Difference of time stamp counter between last and | |
112 | * current sample | |
13ad7701 SP |
113 | * @time: Current time from scheduler |
114 | * | |
115 | * This structure is used in the cpudata structure to store performance sample | |
116 | * data for choosing next P State. | |
117 | */ | |
93f0822d | 118 | struct sample { |
a1c9787d | 119 | int32_t core_avg_perf; |
157386b6 | 120 | int32_t busy_scaled; |
93f0822d DB |
121 | u64 aperf; |
122 | u64 mperf; | |
4055fad3 | 123 | u64 tsc; |
a4675fbc | 124 | u64 time; |
93f0822d DB |
125 | }; |
126 | ||
13ad7701 SP |
127 | /** |
128 | * struct pstate_data - Store P state data | |
129 | * @current_pstate: Current requested P state | |
130 | * @min_pstate: Min P state possible for this platform | |
131 | * @max_pstate: Max P state possible for this platform | |
132 | * @max_pstate_physical:This is physical Max P state for a processor | |
133 | * This can be higher than the max_pstate which can | |
134 | * be limited by platform thermal design power limits | |
135 | * @scaling: Scaling factor to convert frequency to cpufreq | |
136 | * frequency units | |
137 | * @turbo_pstate: Max Turbo P state possible for this platform | |
001c76f0 RW |
138 | * @max_freq: @max_pstate frequency in cpufreq units |
139 | * @turbo_freq: @turbo_pstate frequency in cpufreq units | |
13ad7701 SP |
140 | * |
141 | * Stores the per cpu model P state limits and current P state. | |
142 | */ | |
93f0822d DB |
143 | struct pstate_data { |
144 | int current_pstate; | |
145 | int min_pstate; | |
146 | int max_pstate; | |
3bcc6fa9 | 147 | int max_pstate_physical; |
b27580b0 | 148 | int scaling; |
93f0822d | 149 | int turbo_pstate; |
001c76f0 RW |
150 | unsigned int max_freq; |
151 | unsigned int turbo_freq; | |
93f0822d DB |
152 | }; |
153 | ||
13ad7701 SP |
154 | /** |
155 | * struct vid_data - Stores voltage information data | |
156 | * @min: VID data for this platform corresponding to | |
157 | * the lowest P state | |
158 | * @max: VID data corresponding to the highest P State. | |
159 | * @turbo: VID data for turbo P state | |
160 | * @ratio: Ratio of (vid max - vid min) / | |
161 | * (max P state - Min P State) | |
162 | * | |
163 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
164 | * This data is used in Atom platforms, where in addition to target P state, | |
165 | * the voltage data needs to be specified to select next P State. | |
166 | */ | |
007bea09 | 167 | struct vid_data { |
21855ff5 DB |
168 | int min; |
169 | int max; | |
170 | int turbo; | |
007bea09 DB |
171 | int32_t ratio; |
172 | }; | |
173 | ||
c5a2ee7d RW |
174 | /** |
175 | * struct global_params - Global parameters, mostly tunable via sysfs. | |
176 | * @no_turbo: Whether or not to use turbo P-states. | |
177 | * @turbo_disabled: Whethet or not turbo P-states are available at all, | |
178 | * based on the MSR_IA32_MISC_ENABLE value and whether or | |
179 | * not the maximum reported turbo P-state is different from | |
180 | * the maximum reported non-turbo one. | |
181 | * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo | |
182 | * P-state capacity. | |
183 | * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo | |
184 | * P-state capacity. | |
185 | */ | |
186 | struct global_params { | |
187 | bool no_turbo; | |
188 | bool turbo_disabled; | |
189 | int max_perf_pct; | |
190 | int min_perf_pct; | |
eae48f04 SP |
191 | }; |
192 | ||
13ad7701 SP |
193 | /** |
194 | * struct cpudata - Per CPU instance data storage | |
195 | * @cpu: CPU number for this instance data | |
2f1d407a | 196 | * @policy: CPUFreq policy value |
13ad7701 | 197 | * @update_util: CPUFreq utility callback information |
4578ee7e | 198 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
199 | * @iowait_boost: iowait-related boost fraction |
200 | * @last_update: Time of the last update. | |
13ad7701 SP |
201 | * @pstate: Stores P state limits for this CPU |
202 | * @vid: Stores VID limits for this CPU | |
13ad7701 | 203 | * @last_sample_time: Last Sample time |
6e34e1f2 SP |
204 | * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented |
205 | * This shift is a multiplier to mperf delta to | |
206 | * calculate CPU busy. | |
13ad7701 SP |
207 | * @prev_aperf: Last APERF value read from APERF MSR |
208 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
209 | * @prev_tsc: Last timestamp counter (TSC) value | |
210 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
211 | * current sample | |
212 | * @sample: Storage for storing last Sample data | |
1a4fe38a SP |
213 | * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios |
214 | * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios | |
9522a2ff SP |
215 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
216 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
984edbdc SP |
217 | * @epp_powersave: Last saved HWP energy performance preference |
218 | * (EPP) or energy performance bias (EPB), | |
219 | * when policy switched to performance | |
8442885f | 220 | * @epp_policy: Last saved policy used to set EPP/EPB |
984edbdc SP |
221 | * @epp_default: Power on default HWP energy performance |
222 | * preference/bias | |
223 | * @epp_saved: Saved EPP/EPB during system suspend or CPU offline | |
224 | * operation | |
13ad7701 SP |
225 | * |
226 | * This structure stores per CPU instance data for all CPUs. | |
227 | */ | |
93f0822d DB |
228 | struct cpudata { |
229 | int cpu; | |
230 | ||
2f1d407a | 231 | unsigned int policy; |
a4675fbc | 232 | struct update_util_data update_util; |
4578ee7e | 233 | bool update_util_set; |
93f0822d | 234 | |
93f0822d | 235 | struct pstate_data pstate; |
007bea09 | 236 | struct vid_data vid; |
93f0822d | 237 | |
09c448d3 | 238 | u64 last_update; |
a4675fbc | 239 | u64 last_sample_time; |
6e34e1f2 | 240 | u64 aperf_mperf_shift; |
93f0822d DB |
241 | u64 prev_aperf; |
242 | u64 prev_mperf; | |
4055fad3 | 243 | u64 prev_tsc; |
63d1d656 | 244 | u64 prev_cummulative_iowait; |
d37e2b76 | 245 | struct sample sample; |
1a4fe38a SP |
246 | int32_t min_perf_ratio; |
247 | int32_t max_perf_ratio; | |
9522a2ff SP |
248 | #ifdef CONFIG_ACPI |
249 | struct acpi_processor_performance acpi_perf_data; | |
250 | bool valid_pss_table; | |
251 | #endif | |
09c448d3 | 252 | unsigned int iowait_boost; |
984edbdc | 253 | s16 epp_powersave; |
8442885f | 254 | s16 epp_policy; |
984edbdc SP |
255 | s16 epp_default; |
256 | s16 epp_saved; | |
93f0822d DB |
257 | }; |
258 | ||
259 | static struct cpudata **all_cpu_data; | |
13ad7701 | 260 | |
13ad7701 SP |
261 | /** |
262 | * struct pstate_funcs - Per CPU model specific callbacks | |
263 | * @get_max: Callback to get maximum non turbo effective P state | |
264 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
265 | * @get_min: Callback to get minimum P state | |
266 | * @get_turbo: Callback to get turbo P state | |
267 | * @get_scaling: Callback to get frequency scaling factor | |
268 | * @get_val: Callback to convert P state to actual MSR write value | |
269 | * @get_vid: Callback to get VID data for Atom platforms | |
13ad7701 SP |
270 | * |
271 | * Core and Atom CPU models have different way to get P State limits. This | |
272 | * structure is used to store those callbacks. | |
273 | */ | |
016c8150 DB |
274 | struct pstate_funcs { |
275 | int (*get_max)(void); | |
3bcc6fa9 | 276 | int (*get_max_physical)(void); |
016c8150 DB |
277 | int (*get_min)(void); |
278 | int (*get_turbo)(void); | |
b27580b0 | 279 | int (*get_scaling)(void); |
6e34e1f2 | 280 | int (*get_aperf_mperf_shift)(void); |
fdfdb2b1 | 281 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 282 | void (*get_vid)(struct cpudata *); |
93f0822d DB |
283 | }; |
284 | ||
4a7cb7a9 | 285 | static struct pstate_funcs pstate_funcs __read_mostly; |
5c439053 | 286 | |
4a7cb7a9 | 287 | static int hwp_active __read_mostly; |
8da0f2d9 | 288 | static int hwp_mode_bdw __read_mostly; |
eae48f04 | 289 | static bool per_cpu_limits __read_mostly; |
016c8150 | 290 | |
ee8df89a | 291 | static struct cpufreq_driver *intel_pstate_driver __read_mostly; |
0c30b65b | 292 | |
9522a2ff SP |
293 | #ifdef CONFIG_ACPI |
294 | static bool acpi_ppc; | |
295 | #endif | |
13ad7701 | 296 | |
c5a2ee7d | 297 | static struct global_params global; |
93f0822d | 298 | |
0c30b65b | 299 | static DEFINE_MUTEX(intel_pstate_driver_lock); |
a410c03d SP |
300 | static DEFINE_MUTEX(intel_pstate_limits_lock); |
301 | ||
9522a2ff | 302 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
303 | |
304 | static bool intel_pstate_get_ppc_enable_status(void) | |
305 | { | |
306 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
307 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
308 | return true; | |
309 | ||
310 | return acpi_ppc; | |
311 | } | |
312 | ||
17669006 RW |
313 | #ifdef CONFIG_ACPI_CPPC_LIB |
314 | ||
315 | /* The work item is needed to avoid CPU hotplug locking issues */ | |
316 | static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) | |
317 | { | |
318 | sched_set_itmt_support(); | |
319 | } | |
320 | ||
321 | static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); | |
322 | ||
323 | static void intel_pstate_set_itmt_prio(int cpu) | |
324 | { | |
325 | struct cppc_perf_caps cppc_perf; | |
326 | static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; | |
327 | int ret; | |
328 | ||
329 | ret = cppc_get_perf_caps(cpu, &cppc_perf); | |
330 | if (ret) | |
331 | return; | |
332 | ||
333 | /* | |
334 | * The priorities can be set regardless of whether or not | |
335 | * sched_set_itmt_support(true) has been called and it is valid to | |
336 | * update them at any time after it has been called. | |
337 | */ | |
338 | sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); | |
339 | ||
340 | if (max_highest_perf <= min_highest_perf) { | |
341 | if (cppc_perf.highest_perf > max_highest_perf) | |
342 | max_highest_perf = cppc_perf.highest_perf; | |
343 | ||
344 | if (cppc_perf.highest_perf < min_highest_perf) | |
345 | min_highest_perf = cppc_perf.highest_perf; | |
346 | ||
347 | if (max_highest_perf > min_highest_perf) { | |
348 | /* | |
349 | * This code can be run during CPU online under the | |
350 | * CPU hotplug locks, so sched_set_itmt_support() | |
351 | * cannot be called from here. Queue up a work item | |
352 | * to invoke it. | |
353 | */ | |
354 | schedule_work(&sched_itmt_work); | |
355 | } | |
356 | } | |
357 | } | |
358 | #else | |
359 | static void intel_pstate_set_itmt_prio(int cpu) | |
360 | { | |
361 | } | |
362 | #endif | |
363 | ||
9522a2ff SP |
364 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
365 | { | |
366 | struct cpudata *cpu; | |
9522a2ff SP |
367 | int ret; |
368 | int i; | |
369 | ||
17669006 RW |
370 | if (hwp_active) { |
371 | intel_pstate_set_itmt_prio(policy->cpu); | |
e59a8f7f | 372 | return; |
17669006 | 373 | } |
e59a8f7f | 374 | |
2b3ec765 | 375 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
376 | return; |
377 | ||
378 | cpu = all_cpu_data[policy->cpu]; | |
379 | ||
380 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
381 | policy->cpu); | |
382 | if (ret) | |
383 | return; | |
384 | ||
385 | /* | |
386 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
387 | * guarantee that the states returned by it map to the states in our | |
388 | * list directly. | |
389 | */ | |
390 | if (cpu->acpi_perf_data.control_register.space_id != | |
391 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
392 | goto err; | |
393 | ||
394 | /* | |
395 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
396 | * usual without taking _PSS into account | |
397 | */ | |
398 | if (cpu->acpi_perf_data.state_count < 2) | |
399 | goto err; | |
400 | ||
401 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
402 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
403 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
404 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
405 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
406 | (u32) cpu->acpi_perf_data.states[i].power, | |
407 | (u32) cpu->acpi_perf_data.states[i].control); | |
408 | } | |
409 | ||
410 | /* | |
411 | * The _PSS table doesn't contain whole turbo frequency range. | |
412 | * This just contains +1 MHZ above the max non turbo frequency, | |
413 | * with control value corresponding to max turbo ratio. But | |
414 | * when cpufreq set policy is called, it will call with this | |
415 | * max frequency, which will cause a reduced performance as | |
416 | * this driver uses real max turbo frequency as the max | |
417 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 418 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
419 | * Also need to convert to MHz as _PSS freq is in MHz. |
420 | */ | |
7de32556 | 421 | if (!global.turbo_disabled) |
9522a2ff SP |
422 | cpu->acpi_perf_data.states[0].core_frequency = |
423 | policy->cpuinfo.max_freq / 1000; | |
424 | cpu->valid_pss_table = true; | |
6cacd115 | 425 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
426 | |
427 | return; | |
428 | ||
429 | err: | |
430 | cpu->valid_pss_table = false; | |
431 | acpi_processor_unregister_performance(policy->cpu); | |
432 | } | |
433 | ||
434 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
435 | { | |
436 | struct cpudata *cpu; | |
437 | ||
438 | cpu = all_cpu_data[policy->cpu]; | |
439 | if (!cpu->valid_pss_table) | |
440 | return; | |
441 | ||
442 | acpi_processor_unregister_performance(policy->cpu); | |
443 | } | |
9522a2ff | 444 | #else |
7a3ba767 | 445 | static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
446 | { |
447 | } | |
448 | ||
7a3ba767 | 449 | static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
450 | { |
451 | } | |
452 | #endif | |
453 | ||
4521e1a0 GM |
454 | static inline void update_turbo_state(void) |
455 | { | |
456 | u64 misc_en; | |
457 | struct cpudata *cpu; | |
458 | ||
459 | cpu = all_cpu_data[0]; | |
460 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
7de32556 | 461 | global.turbo_disabled = |
4521e1a0 GM |
462 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
463 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
464 | } | |
465 | ||
c5a2ee7d RW |
466 | static int min_perf_pct_min(void) |
467 | { | |
468 | struct cpudata *cpu = all_cpu_data[0]; | |
57caf4ec | 469 | int turbo_pstate = cpu->pstate.turbo_pstate; |
c5a2ee7d | 470 | |
57caf4ec | 471 | return turbo_pstate ? |
d4436c0d | 472 | (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0; |
c5a2ee7d RW |
473 | } |
474 | ||
8442885f SP |
475 | static s16 intel_pstate_get_epb(struct cpudata *cpu_data) |
476 | { | |
477 | u64 epb; | |
478 | int ret; | |
479 | ||
480 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
481 | return -ENXIO; | |
482 | ||
483 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); | |
484 | if (ret) | |
485 | return (s16)ret; | |
486 | ||
487 | return (s16)(epb & 0x0f); | |
488 | } | |
489 | ||
490 | static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) | |
491 | { | |
492 | s16 epp; | |
493 | ||
984edbdc SP |
494 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
495 | /* | |
496 | * When hwp_req_data is 0, means that caller didn't read | |
497 | * MSR_HWP_REQUEST, so need to read and get EPP. | |
498 | */ | |
499 | if (!hwp_req_data) { | |
500 | epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, | |
501 | &hwp_req_data); | |
502 | if (epp) | |
503 | return epp; | |
504 | } | |
8442885f | 505 | epp = (hwp_req_data >> 24) & 0xff; |
984edbdc | 506 | } else { |
8442885f SP |
507 | /* When there is no EPP present, HWP uses EPB settings */ |
508 | epp = intel_pstate_get_epb(cpu_data); | |
984edbdc | 509 | } |
8442885f SP |
510 | |
511 | return epp; | |
512 | } | |
513 | ||
984edbdc | 514 | static int intel_pstate_set_epb(int cpu, s16 pref) |
8442885f SP |
515 | { |
516 | u64 epb; | |
984edbdc | 517 | int ret; |
8442885f SP |
518 | |
519 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
984edbdc | 520 | return -ENXIO; |
8442885f | 521 | |
984edbdc SP |
522 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); |
523 | if (ret) | |
524 | return ret; | |
8442885f SP |
525 | |
526 | epb = (epb & ~0x0f) | pref; | |
527 | wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); | |
984edbdc SP |
528 | |
529 | return 0; | |
8442885f SP |
530 | } |
531 | ||
984edbdc SP |
532 | /* |
533 | * EPP/EPB display strings corresponding to EPP index in the | |
534 | * energy_perf_strings[] | |
535 | * index String | |
536 | *------------------------------------- | |
537 | * 0 default | |
538 | * 1 performance | |
539 | * 2 balance_performance | |
540 | * 3 balance_power | |
541 | * 4 power | |
542 | */ | |
543 | static const char * const energy_perf_strings[] = { | |
544 | "default", | |
545 | "performance", | |
546 | "balance_performance", | |
547 | "balance_power", | |
548 | "power", | |
549 | NULL | |
550 | }; | |
3cedbc5a LB |
551 | static const unsigned int epp_values[] = { |
552 | HWP_EPP_PERFORMANCE, | |
553 | HWP_EPP_BALANCE_PERFORMANCE, | |
554 | HWP_EPP_BALANCE_POWERSAVE, | |
555 | HWP_EPP_POWERSAVE | |
556 | }; | |
984edbdc SP |
557 | |
558 | static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) | |
559 | { | |
560 | s16 epp; | |
561 | int index = -EINVAL; | |
562 | ||
563 | epp = intel_pstate_get_epp(cpu_data, 0); | |
564 | if (epp < 0) | |
565 | return epp; | |
566 | ||
567 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
3cedbc5a LB |
568 | if (epp == HWP_EPP_PERFORMANCE) |
569 | return 1; | |
570 | if (epp <= HWP_EPP_BALANCE_PERFORMANCE) | |
571 | return 2; | |
572 | if (epp <= HWP_EPP_BALANCE_POWERSAVE) | |
573 | return 3; | |
574 | else | |
575 | return 4; | |
984edbdc SP |
576 | } else if (static_cpu_has(X86_FEATURE_EPB)) { |
577 | /* | |
578 | * Range: | |
579 | * 0x00-0x03 : Performance | |
580 | * 0x04-0x07 : Balance performance | |
581 | * 0x08-0x0B : Balance power | |
582 | * 0x0C-0x0F : Power | |
583 | * The EPB is a 4 bit value, but our ranges restrict the | |
584 | * value which can be set. Here only using top two bits | |
585 | * effectively. | |
586 | */ | |
587 | index = (epp >> 2) + 1; | |
588 | } | |
589 | ||
590 | return index; | |
591 | } | |
592 | ||
593 | static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, | |
594 | int pref_index) | |
595 | { | |
596 | int epp = -EINVAL; | |
597 | int ret; | |
598 | ||
599 | if (!pref_index) | |
600 | epp = cpu_data->epp_default; | |
601 | ||
602 | mutex_lock(&intel_pstate_limits_lock); | |
603 | ||
604 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
605 | u64 value; | |
606 | ||
607 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); | |
608 | if (ret) | |
609 | goto return_pref; | |
610 | ||
611 | value &= ~GENMASK_ULL(31, 24); | |
612 | ||
984edbdc | 613 | if (epp == -EINVAL) |
3cedbc5a | 614 | epp = epp_values[pref_index - 1]; |
984edbdc SP |
615 | |
616 | value |= (u64)epp << 24; | |
617 | ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); | |
618 | } else { | |
619 | if (epp == -EINVAL) | |
620 | epp = (pref_index - 1) << 2; | |
621 | ret = intel_pstate_set_epb(cpu_data->cpu, epp); | |
622 | } | |
623 | return_pref: | |
624 | mutex_unlock(&intel_pstate_limits_lock); | |
625 | ||
626 | return ret; | |
627 | } | |
628 | ||
629 | static ssize_t show_energy_performance_available_preferences( | |
630 | struct cpufreq_policy *policy, char *buf) | |
631 | { | |
632 | int i = 0; | |
633 | int ret = 0; | |
634 | ||
635 | while (energy_perf_strings[i] != NULL) | |
636 | ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); | |
637 | ||
638 | ret += sprintf(&buf[ret], "\n"); | |
639 | ||
640 | return ret; | |
641 | } | |
642 | ||
643 | cpufreq_freq_attr_ro(energy_performance_available_preferences); | |
644 | ||
645 | static ssize_t store_energy_performance_preference( | |
646 | struct cpufreq_policy *policy, const char *buf, size_t count) | |
647 | { | |
648 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
649 | char str_preference[21]; | |
650 | int ret, i = 0; | |
651 | ||
652 | ret = sscanf(buf, "%20s", str_preference); | |
653 | if (ret != 1) | |
654 | return -EINVAL; | |
655 | ||
656 | while (energy_perf_strings[i] != NULL) { | |
657 | if (!strcmp(str_preference, energy_perf_strings[i])) { | |
658 | intel_pstate_set_energy_pref_index(cpu_data, i); | |
659 | return count; | |
660 | } | |
661 | ++i; | |
662 | } | |
663 | ||
664 | return -EINVAL; | |
665 | } | |
666 | ||
667 | static ssize_t show_energy_performance_preference( | |
668 | struct cpufreq_policy *policy, char *buf) | |
669 | { | |
670 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
671 | int preference; | |
672 | ||
673 | preference = intel_pstate_get_energy_pref_index(cpu_data); | |
674 | if (preference < 0) | |
675 | return preference; | |
676 | ||
677 | return sprintf(buf, "%s\n", energy_perf_strings[preference]); | |
678 | } | |
679 | ||
680 | cpufreq_freq_attr_rw(energy_performance_preference); | |
681 | ||
682 | static struct freq_attr *hwp_cpufreq_attrs[] = { | |
683 | &energy_performance_preference, | |
684 | &energy_performance_available_preferences, | |
685 | NULL, | |
686 | }; | |
687 | ||
1a4fe38a SP |
688 | static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max, |
689 | int *current_max) | |
2f86dc4c | 690 | { |
1a4fe38a | 691 | u64 cap; |
74da56ce | 692 | |
2bfc4cbb | 693 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
2bfc4cbb | 694 | if (global.no_turbo) |
1a4fe38a | 695 | *current_max = HWP_GUARANTEED_PERF(cap); |
2bfc4cbb | 696 | else |
1a4fe38a SP |
697 | *current_max = HWP_HIGHEST_PERF(cap); |
698 | ||
699 | *phy_max = HWP_HIGHEST_PERF(cap); | |
700 | } | |
701 | ||
702 | static void intel_pstate_hwp_set(unsigned int cpu) | |
703 | { | |
704 | struct cpudata *cpu_data = all_cpu_data[cpu]; | |
705 | int max, min; | |
706 | u64 value; | |
707 | s16 epp; | |
708 | ||
709 | max = cpu_data->max_perf_ratio; | |
710 | min = cpu_data->min_perf_ratio; | |
eae48f04 | 711 | |
2bfc4cbb RW |
712 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) |
713 | min = max; | |
3f8ed54a | 714 | |
2bfc4cbb | 715 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
2f86dc4c | 716 | |
2bfc4cbb RW |
717 | value &= ~HWP_MIN_PERF(~0L); |
718 | value |= HWP_MIN_PERF(min); | |
8442885f | 719 | |
2bfc4cbb RW |
720 | value &= ~HWP_MAX_PERF(~0L); |
721 | value |= HWP_MAX_PERF(max); | |
8442885f | 722 | |
2bfc4cbb RW |
723 | if (cpu_data->epp_policy == cpu_data->policy) |
724 | goto skip_epp; | |
8442885f | 725 | |
2bfc4cbb | 726 | cpu_data->epp_policy = cpu_data->policy; |
984edbdc | 727 | |
2bfc4cbb RW |
728 | if (cpu_data->epp_saved >= 0) { |
729 | epp = cpu_data->epp_saved; | |
730 | cpu_data->epp_saved = -EINVAL; | |
731 | goto update_epp; | |
732 | } | |
8442885f | 733 | |
2bfc4cbb RW |
734 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { |
735 | epp = intel_pstate_get_epp(cpu_data, value); | |
736 | cpu_data->epp_powersave = epp; | |
737 | /* If EPP read was failed, then don't try to write */ | |
738 | if (epp < 0) | |
739 | goto skip_epp; | |
8442885f | 740 | |
2bfc4cbb RW |
741 | epp = 0; |
742 | } else { | |
743 | /* skip setting EPP, when saved value is invalid */ | |
744 | if (cpu_data->epp_powersave < 0) | |
745 | goto skip_epp; | |
8442885f | 746 | |
2bfc4cbb RW |
747 | /* |
748 | * No need to restore EPP when it is not zero. This | |
749 | * means: | |
750 | * - Policy is not changed | |
751 | * - user has manually changed | |
752 | * - Error reading EPB | |
753 | */ | |
754 | epp = intel_pstate_get_epp(cpu_data, value); | |
755 | if (epp) | |
756 | goto skip_epp; | |
8442885f | 757 | |
2bfc4cbb RW |
758 | epp = cpu_data->epp_powersave; |
759 | } | |
984edbdc | 760 | update_epp: |
2bfc4cbb RW |
761 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
762 | value &= ~GENMASK_ULL(31, 24); | |
763 | value |= (u64)epp << 24; | |
764 | } else { | |
765 | intel_pstate_set_epb(cpu, epp); | |
2f86dc4c | 766 | } |
2bfc4cbb RW |
767 | skip_epp: |
768 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
41cfd64c | 769 | } |
2f86dc4c | 770 | |
984edbdc SP |
771 | static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) |
772 | { | |
773 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
774 | ||
775 | if (!hwp_active) | |
776 | return 0; | |
777 | ||
778 | cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
b672e570 CY |
783 | static void intel_pstate_hwp_enable(struct cpudata *cpudata); |
784 | ||
8442885f SP |
785 | static int intel_pstate_resume(struct cpufreq_policy *policy) |
786 | { | |
787 | if (!hwp_active) | |
788 | return 0; | |
789 | ||
aa439248 RW |
790 | mutex_lock(&intel_pstate_limits_lock); |
791 | ||
b672e570 CY |
792 | if (policy->cpu == 0) |
793 | intel_pstate_hwp_enable(all_cpu_data[policy->cpu]); | |
794 | ||
8442885f | 795 | all_cpu_data[policy->cpu]->epp_policy = 0; |
2bfc4cbb | 796 | intel_pstate_hwp_set(policy->cpu); |
aa439248 RW |
797 | |
798 | mutex_unlock(&intel_pstate_limits_lock); | |
799 | ||
5f98ced1 | 800 | return 0; |
8442885f SP |
801 | } |
802 | ||
111b8b3f | 803 | static void intel_pstate_update_policies(void) |
41cfd64c | 804 | { |
111b8b3f RW |
805 | int cpu; |
806 | ||
807 | for_each_possible_cpu(cpu) | |
808 | cpufreq_update_policy(cpu); | |
2f86dc4c DB |
809 | } |
810 | ||
93f0822d DB |
811 | /************************** sysfs begin ************************/ |
812 | #define show_one(file_name, object) \ | |
813 | static ssize_t show_##file_name \ | |
814 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
815 | { \ | |
7de32556 | 816 | return sprintf(buf, "%u\n", global.object); \ |
93f0822d DB |
817 | } |
818 | ||
fb1fe104 RW |
819 | static ssize_t intel_pstate_show_status(char *buf); |
820 | static int intel_pstate_update_status(const char *buf, size_t size); | |
821 | ||
822 | static ssize_t show_status(struct kobject *kobj, | |
823 | struct attribute *attr, char *buf) | |
824 | { | |
825 | ssize_t ret; | |
826 | ||
827 | mutex_lock(&intel_pstate_driver_lock); | |
828 | ret = intel_pstate_show_status(buf); | |
829 | mutex_unlock(&intel_pstate_driver_lock); | |
830 | ||
831 | return ret; | |
832 | } | |
833 | ||
834 | static ssize_t store_status(struct kobject *a, struct attribute *b, | |
835 | const char *buf, size_t count) | |
836 | { | |
837 | char *p = memchr(buf, '\n', count); | |
838 | int ret; | |
839 | ||
840 | mutex_lock(&intel_pstate_driver_lock); | |
841 | ret = intel_pstate_update_status(buf, p ? p - buf : count); | |
842 | mutex_unlock(&intel_pstate_driver_lock); | |
843 | ||
844 | return ret < 0 ? ret : count; | |
845 | } | |
846 | ||
d01b1f48 KCA |
847 | static ssize_t show_turbo_pct(struct kobject *kobj, |
848 | struct attribute *attr, char *buf) | |
849 | { | |
850 | struct cpudata *cpu; | |
851 | int total, no_turbo, turbo_pct; | |
852 | uint32_t turbo_fp; | |
853 | ||
0c30b65b RW |
854 | mutex_lock(&intel_pstate_driver_lock); |
855 | ||
ee8df89a | 856 | if (!intel_pstate_driver) { |
0c30b65b RW |
857 | mutex_unlock(&intel_pstate_driver_lock); |
858 | return -EAGAIN; | |
859 | } | |
860 | ||
d01b1f48 KCA |
861 | cpu = all_cpu_data[0]; |
862 | ||
863 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
864 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 865 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 | 866 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
0c30b65b RW |
867 | |
868 | mutex_unlock(&intel_pstate_driver_lock); | |
869 | ||
d01b1f48 KCA |
870 | return sprintf(buf, "%u\n", turbo_pct); |
871 | } | |
872 | ||
0522424e KCA |
873 | static ssize_t show_num_pstates(struct kobject *kobj, |
874 | struct attribute *attr, char *buf) | |
875 | { | |
876 | struct cpudata *cpu; | |
877 | int total; | |
878 | ||
0c30b65b RW |
879 | mutex_lock(&intel_pstate_driver_lock); |
880 | ||
ee8df89a | 881 | if (!intel_pstate_driver) { |
0c30b65b RW |
882 | mutex_unlock(&intel_pstate_driver_lock); |
883 | return -EAGAIN; | |
884 | } | |
885 | ||
0522424e KCA |
886 | cpu = all_cpu_data[0]; |
887 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
0c30b65b RW |
888 | |
889 | mutex_unlock(&intel_pstate_driver_lock); | |
890 | ||
0522424e KCA |
891 | return sprintf(buf, "%u\n", total); |
892 | } | |
893 | ||
4521e1a0 GM |
894 | static ssize_t show_no_turbo(struct kobject *kobj, |
895 | struct attribute *attr, char *buf) | |
896 | { | |
897 | ssize_t ret; | |
898 | ||
0c30b65b RW |
899 | mutex_lock(&intel_pstate_driver_lock); |
900 | ||
ee8df89a | 901 | if (!intel_pstate_driver) { |
0c30b65b RW |
902 | mutex_unlock(&intel_pstate_driver_lock); |
903 | return -EAGAIN; | |
904 | } | |
905 | ||
4521e1a0 | 906 | update_turbo_state(); |
7de32556 RW |
907 | if (global.turbo_disabled) |
908 | ret = sprintf(buf, "%u\n", global.turbo_disabled); | |
4521e1a0 | 909 | else |
7de32556 | 910 | ret = sprintf(buf, "%u\n", global.no_turbo); |
4521e1a0 | 911 | |
0c30b65b RW |
912 | mutex_unlock(&intel_pstate_driver_lock); |
913 | ||
4521e1a0 GM |
914 | return ret; |
915 | } | |
916 | ||
93f0822d | 917 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 918 | const char *buf, size_t count) |
93f0822d DB |
919 | { |
920 | unsigned int input; | |
921 | int ret; | |
845c1cbe | 922 | |
93f0822d DB |
923 | ret = sscanf(buf, "%u", &input); |
924 | if (ret != 1) | |
925 | return -EINVAL; | |
4521e1a0 | 926 | |
0c30b65b RW |
927 | mutex_lock(&intel_pstate_driver_lock); |
928 | ||
ee8df89a | 929 | if (!intel_pstate_driver) { |
0c30b65b RW |
930 | mutex_unlock(&intel_pstate_driver_lock); |
931 | return -EAGAIN; | |
932 | } | |
933 | ||
a410c03d SP |
934 | mutex_lock(&intel_pstate_limits_lock); |
935 | ||
4521e1a0 | 936 | update_turbo_state(); |
7de32556 | 937 | if (global.turbo_disabled) { |
4836df17 | 938 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
a410c03d | 939 | mutex_unlock(&intel_pstate_limits_lock); |
0c30b65b | 940 | mutex_unlock(&intel_pstate_driver_lock); |
4521e1a0 | 941 | return -EPERM; |
dd5fbf70 | 942 | } |
2f86dc4c | 943 | |
7de32556 | 944 | global.no_turbo = clamp_t(int, input, 0, 1); |
111b8b3f | 945 | |
c5a2ee7d RW |
946 | if (global.no_turbo) { |
947 | struct cpudata *cpu = all_cpu_data[0]; | |
948 | int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; | |
949 | ||
950 | /* Squash the global minimum into the permitted range. */ | |
951 | if (global.min_perf_pct > pct) | |
952 | global.min_perf_pct = pct; | |
953 | } | |
954 | ||
cd59b4be RW |
955 | mutex_unlock(&intel_pstate_limits_lock); |
956 | ||
7de32556 RW |
957 | intel_pstate_update_policies(); |
958 | ||
0c30b65b RW |
959 | mutex_unlock(&intel_pstate_driver_lock); |
960 | ||
93f0822d DB |
961 | return count; |
962 | } | |
963 | ||
964 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 965 | const char *buf, size_t count) |
93f0822d DB |
966 | { |
967 | unsigned int input; | |
968 | int ret; | |
845c1cbe | 969 | |
93f0822d DB |
970 | ret = sscanf(buf, "%u", &input); |
971 | if (ret != 1) | |
972 | return -EINVAL; | |
973 | ||
0c30b65b RW |
974 | mutex_lock(&intel_pstate_driver_lock); |
975 | ||
ee8df89a | 976 | if (!intel_pstate_driver) { |
0c30b65b RW |
977 | mutex_unlock(&intel_pstate_driver_lock); |
978 | return -EAGAIN; | |
979 | } | |
980 | ||
a410c03d SP |
981 | mutex_lock(&intel_pstate_limits_lock); |
982 | ||
c5a2ee7d | 983 | global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); |
111b8b3f | 984 | |
cd59b4be RW |
985 | mutex_unlock(&intel_pstate_limits_lock); |
986 | ||
7de32556 RW |
987 | intel_pstate_update_policies(); |
988 | ||
0c30b65b RW |
989 | mutex_unlock(&intel_pstate_driver_lock); |
990 | ||
93f0822d DB |
991 | return count; |
992 | } | |
993 | ||
994 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 995 | const char *buf, size_t count) |
93f0822d DB |
996 | { |
997 | unsigned int input; | |
998 | int ret; | |
845c1cbe | 999 | |
93f0822d DB |
1000 | ret = sscanf(buf, "%u", &input); |
1001 | if (ret != 1) | |
1002 | return -EINVAL; | |
a0475992 | 1003 | |
0c30b65b RW |
1004 | mutex_lock(&intel_pstate_driver_lock); |
1005 | ||
ee8df89a | 1006 | if (!intel_pstate_driver) { |
0c30b65b RW |
1007 | mutex_unlock(&intel_pstate_driver_lock); |
1008 | return -EAGAIN; | |
1009 | } | |
1010 | ||
a410c03d SP |
1011 | mutex_lock(&intel_pstate_limits_lock); |
1012 | ||
c5a2ee7d RW |
1013 | global.min_perf_pct = clamp_t(int, input, |
1014 | min_perf_pct_min(), global.max_perf_pct); | |
111b8b3f | 1015 | |
cd59b4be RW |
1016 | mutex_unlock(&intel_pstate_limits_lock); |
1017 | ||
7de32556 RW |
1018 | intel_pstate_update_policies(); |
1019 | ||
0c30b65b RW |
1020 | mutex_unlock(&intel_pstate_driver_lock); |
1021 | ||
93f0822d DB |
1022 | return count; |
1023 | } | |
1024 | ||
93f0822d DB |
1025 | show_one(max_perf_pct, max_perf_pct); |
1026 | show_one(min_perf_pct, min_perf_pct); | |
1027 | ||
fb1fe104 | 1028 | define_one_global_rw(status); |
93f0822d DB |
1029 | define_one_global_rw(no_turbo); |
1030 | define_one_global_rw(max_perf_pct); | |
1031 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 1032 | define_one_global_ro(turbo_pct); |
0522424e | 1033 | define_one_global_ro(num_pstates); |
93f0822d DB |
1034 | |
1035 | static struct attribute *intel_pstate_attributes[] = { | |
fb1fe104 | 1036 | &status.attr, |
93f0822d | 1037 | &no_turbo.attr, |
d01b1f48 | 1038 | &turbo_pct.attr, |
0522424e | 1039 | &num_pstates.attr, |
93f0822d DB |
1040 | NULL |
1041 | }; | |
1042 | ||
106c9c77 | 1043 | static const struct attribute_group intel_pstate_attr_group = { |
93f0822d DB |
1044 | .attrs = intel_pstate_attributes, |
1045 | }; | |
93f0822d | 1046 | |
317dd50e | 1047 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 1048 | { |
317dd50e | 1049 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
1050 | int rc; |
1051 | ||
1052 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
1053 | &cpu_subsys.dev_root->kobj); | |
eae48f04 SP |
1054 | if (WARN_ON(!intel_pstate_kobject)) |
1055 | return; | |
1056 | ||
2d8d1f18 | 1057 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
eae48f04 SP |
1058 | if (WARN_ON(rc)) |
1059 | return; | |
1060 | ||
1061 | /* | |
1062 | * If per cpu limits are enforced there are no global limits, so | |
1063 | * return without creating max/min_perf_pct attributes | |
1064 | */ | |
1065 | if (per_cpu_limits) | |
1066 | return; | |
1067 | ||
1068 | rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); | |
1069 | WARN_ON(rc); | |
1070 | ||
1071 | rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); | |
1072 | WARN_ON(rc); | |
1073 | ||
93f0822d | 1074 | } |
93f0822d | 1075 | /************************** sysfs end ************************/ |
2f86dc4c | 1076 | |
ba88d433 | 1077 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 1078 | { |
f05c9665 | 1079 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
1080 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
1081 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 1082 | |
ba88d433 | 1083 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
8442885f | 1084 | cpudata->epp_policy = 0; |
984edbdc SP |
1085 | if (cpudata->epp_default == -EINVAL) |
1086 | cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); | |
2f86dc4c DB |
1087 | } |
1088 | ||
6e978b22 SP |
1089 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
1090 | ||
1091 | /* Disable energy efficiency optimization */ | |
1092 | static void intel_pstate_disable_ee(int cpu) | |
1093 | { | |
1094 | u64 power_ctl; | |
1095 | int ret; | |
1096 | ||
1097 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); | |
1098 | if (ret) | |
1099 | return; | |
1100 | ||
1101 | if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { | |
1102 | pr_info("Disabling energy efficiency optimization\n"); | |
1103 | power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); | |
1104 | wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); | |
1105 | } | |
1106 | } | |
1107 | ||
938d21a2 | 1108 | static int atom_get_min_pstate(void) |
19e77c28 DB |
1109 | { |
1110 | u64 value; | |
845c1cbe | 1111 | |
92134bdb | 1112 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1113 | return (value >> 8) & 0x7F; |
19e77c28 DB |
1114 | } |
1115 | ||
938d21a2 | 1116 | static int atom_get_max_pstate(void) |
19e77c28 DB |
1117 | { |
1118 | u64 value; | |
845c1cbe | 1119 | |
92134bdb | 1120 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1121 | return (value >> 16) & 0x7F; |
19e77c28 | 1122 | } |
93f0822d | 1123 | |
938d21a2 | 1124 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
1125 | { |
1126 | u64 value; | |
845c1cbe | 1127 | |
92134bdb | 1128 | rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); |
c16ed060 | 1129 | return value & 0x7F; |
61d8d2ab DB |
1130 | } |
1131 | ||
fdfdb2b1 | 1132 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
1133 | { |
1134 | u64 val; | |
1135 | int32_t vid_fp; | |
1136 | u32 vid; | |
1137 | ||
144c8e17 | 1138 | val = (u64)pstate << 8; |
7de32556 | 1139 | if (global.no_turbo && !global.turbo_disabled) |
007bea09 DB |
1140 | val |= (u64)1 << 32; |
1141 | ||
1142 | vid_fp = cpudata->vid.min + mul_fp( | |
1143 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
1144 | cpudata->vid.ratio); | |
1145 | ||
1146 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 1147 | vid = ceiling_fp(vid_fp); |
007bea09 | 1148 | |
21855ff5 DB |
1149 | if (pstate > cpudata->pstate.max_pstate) |
1150 | vid = cpudata->vid.turbo; | |
1151 | ||
fdfdb2b1 | 1152 | return val | vid; |
007bea09 DB |
1153 | } |
1154 | ||
1421df63 | 1155 | static int silvermont_get_scaling(void) |
b27580b0 DB |
1156 | { |
1157 | u64 value; | |
1158 | int i; | |
1421df63 PL |
1159 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
1160 | static int silvermont_freq_table[] = { | |
1161 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
1162 | |
1163 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
1164 | i = value & 0x7; |
1165 | WARN_ON(i > 4); | |
b27580b0 | 1166 | |
1421df63 PL |
1167 | return silvermont_freq_table[i]; |
1168 | } | |
b27580b0 | 1169 | |
1421df63 PL |
1170 | static int airmont_get_scaling(void) |
1171 | { | |
1172 | u64 value; | |
1173 | int i; | |
1174 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
1175 | static int airmont_freq_table[] = { | |
1176 | 83300, 100000, 133300, 116700, 80000, | |
1177 | 93300, 90000, 88900, 87500}; | |
1178 | ||
1179 | rdmsrl(MSR_FSB_FREQ, value); | |
1180 | i = value & 0xF; | |
1181 | WARN_ON(i > 8); | |
1182 | ||
1183 | return airmont_freq_table[i]; | |
b27580b0 DB |
1184 | } |
1185 | ||
938d21a2 | 1186 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
1187 | { |
1188 | u64 value; | |
1189 | ||
92134bdb | 1190 | rdmsrl(MSR_ATOM_CORE_VIDS, value); |
c16ed060 DB |
1191 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
1192 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
1193 | cpudata->vid.ratio = div_fp( |
1194 | cpudata->vid.max - cpudata->vid.min, | |
1195 | int_tofp(cpudata->pstate.max_pstate - | |
1196 | cpudata->pstate.min_pstate)); | |
21855ff5 | 1197 | |
92134bdb | 1198 | rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); |
21855ff5 | 1199 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
1200 | } |
1201 | ||
016c8150 | 1202 | static int core_get_min_pstate(void) |
93f0822d DB |
1203 | { |
1204 | u64 value; | |
845c1cbe | 1205 | |
05e99c8c | 1206 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1207 | return (value >> 40) & 0xFF; |
1208 | } | |
1209 | ||
3bcc6fa9 | 1210 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
1211 | { |
1212 | u64 value; | |
845c1cbe | 1213 | |
05e99c8c | 1214 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1215 | return (value >> 8) & 0xFF; |
1216 | } | |
1217 | ||
8fc7554a SP |
1218 | static int core_get_tdp_ratio(u64 plat_info) |
1219 | { | |
1220 | /* Check how many TDP levels present */ | |
1221 | if (plat_info & 0x600000000) { | |
1222 | u64 tdp_ctrl; | |
1223 | u64 tdp_ratio; | |
1224 | int tdp_msr; | |
1225 | int err; | |
1226 | ||
1227 | /* Get the TDP level (0, 1, 2) to get ratios */ | |
1228 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
1229 | if (err) | |
1230 | return err; | |
1231 | ||
1232 | /* TDP MSR are continuous starting at 0x648 */ | |
1233 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); | |
1234 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
1235 | if (err) | |
1236 | return err; | |
1237 | ||
1238 | /* For level 1 and 2, bits[23:16] contain the ratio */ | |
1239 | if (tdp_ctrl & 0x03) | |
1240 | tdp_ratio >>= 16; | |
1241 | ||
1242 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
1243 | pr_debug("tdp_ratio %x\n", (int)tdp_ratio); | |
1244 | ||
1245 | return (int)tdp_ratio; | |
1246 | } | |
1247 | ||
1248 | return -ENXIO; | |
1249 | } | |
1250 | ||
016c8150 | 1251 | static int core_get_max_pstate(void) |
93f0822d | 1252 | { |
6a35fc2d SP |
1253 | u64 tar; |
1254 | u64 plat_info; | |
1255 | int max_pstate; | |
8fc7554a | 1256 | int tdp_ratio; |
6a35fc2d SP |
1257 | int err; |
1258 | ||
1259 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
1260 | max_pstate = (plat_info >> 8) & 0xFF; | |
1261 | ||
8fc7554a SP |
1262 | tdp_ratio = core_get_tdp_ratio(plat_info); |
1263 | if (tdp_ratio <= 0) | |
1264 | return max_pstate; | |
1265 | ||
1266 | if (hwp_active) { | |
1267 | /* Turbo activation ratio is not used on HWP platforms */ | |
1268 | return tdp_ratio; | |
1269 | } | |
1270 | ||
6a35fc2d SP |
1271 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); |
1272 | if (!err) { | |
8fc7554a SP |
1273 | int tar_levels; |
1274 | ||
6a35fc2d | 1275 | /* Do some sanity checking for safety */ |
8fc7554a SP |
1276 | tar_levels = tar & 0xff; |
1277 | if (tdp_ratio - 1 == tar_levels) { | |
1278 | max_pstate = tar_levels; | |
1279 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
6a35fc2d SP |
1280 | } |
1281 | } | |
845c1cbe | 1282 | |
6a35fc2d | 1283 | return max_pstate; |
93f0822d DB |
1284 | } |
1285 | ||
016c8150 | 1286 | static int core_get_turbo_pstate(void) |
93f0822d DB |
1287 | { |
1288 | u64 value; | |
1289 | int nont, ret; | |
845c1cbe | 1290 | |
100cf6f2 | 1291 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 1292 | nont = core_get_max_pstate(); |
285cb990 | 1293 | ret = (value) & 255; |
93f0822d DB |
1294 | if (ret <= nont) |
1295 | ret = nont; | |
1296 | return ret; | |
1297 | } | |
1298 | ||
b27580b0 DB |
1299 | static inline int core_get_scaling(void) |
1300 | { | |
1301 | return 100000; | |
1302 | } | |
1303 | ||
fdfdb2b1 | 1304 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
1305 | { |
1306 | u64 val; | |
1307 | ||
144c8e17 | 1308 | val = (u64)pstate << 8; |
7de32556 | 1309 | if (global.no_turbo && !global.turbo_disabled) |
016c8150 DB |
1310 | val |= (u64)1 << 32; |
1311 | ||
fdfdb2b1 | 1312 | return val; |
016c8150 DB |
1313 | } |
1314 | ||
6e34e1f2 SP |
1315 | static int knl_get_aperf_mperf_shift(void) |
1316 | { | |
1317 | return 10; | |
1318 | } | |
1319 | ||
b34ef932 DC |
1320 | static int knl_get_turbo_pstate(void) |
1321 | { | |
1322 | u64 value; | |
1323 | int nont, ret; | |
1324 | ||
100cf6f2 | 1325 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1326 | nont = core_get_max_pstate(); |
1327 | ret = (((value) >> 8) & 0xFF); | |
1328 | if (ret <= nont) | |
1329 | ret = nont; | |
1330 | return ret; | |
1331 | } | |
1332 | ||
b02aabe8 | 1333 | static int intel_pstate_get_base_pstate(struct cpudata *cpu) |
93f0822d | 1334 | { |
b02aabe8 RW |
1335 | return global.no_turbo || global.turbo_disabled ? |
1336 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; | |
93f0822d DB |
1337 | } |
1338 | ||
a6c6ead1 | 1339 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1340 | { |
bc95a454 RW |
1341 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1342 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1343 | /* |
1344 | * Generally, there is no guarantee that this code will always run on | |
1345 | * the CPU being updated, so force the register update to run on the | |
1346 | * right CPU. | |
1347 | */ | |
1348 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1349 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1350 | } |
1351 | ||
a6c6ead1 RW |
1352 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1353 | { | |
1354 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); | |
1355 | } | |
1356 | ||
1357 | static void intel_pstate_max_within_limits(struct cpudata *cpu) | |
1358 | { | |
b02aabe8 | 1359 | int pstate; |
a6c6ead1 RW |
1360 | |
1361 | update_turbo_state(); | |
b02aabe8 | 1362 | pstate = intel_pstate_get_base_pstate(cpu); |
1a4fe38a | 1363 | pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio); |
b02aabe8 | 1364 | intel_pstate_set_pstate(cpu, pstate); |
a6c6ead1 RW |
1365 | } |
1366 | ||
93f0822d DB |
1367 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1368 | { | |
016c8150 DB |
1369 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1370 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1371 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1372 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1373 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
001c76f0 | 1374 | cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; |
8da0f2d9 SP |
1375 | |
1376 | if (hwp_active && !hwp_mode_bdw) { | |
1377 | unsigned int phy_max, current_max; | |
1378 | ||
1379 | intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max); | |
1380 | cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling; | |
1381 | } else { | |
1382 | cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
1383 | } | |
93f0822d | 1384 | |
6e34e1f2 SP |
1385 | if (pstate_funcs.get_aperf_mperf_shift) |
1386 | cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift(); | |
1387 | ||
007bea09 DB |
1388 | if (pstate_funcs.get_vid) |
1389 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1390 | |
1391 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1392 | } |
1393 | ||
a1c9787d | 1394 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1395 | { |
6b17ddb2 | 1396 | struct sample *sample = &cpu->sample; |
e66c1768 | 1397 | |
a1c9787d | 1398 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1399 | } |
1400 | ||
4fec7ad5 | 1401 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1402 | { |
93f0822d | 1403 | u64 aperf, mperf; |
4ab60c3f | 1404 | unsigned long flags; |
4055fad3 | 1405 | u64 tsc; |
93f0822d | 1406 | |
4ab60c3f | 1407 | local_irq_save(flags); |
93f0822d DB |
1408 | rdmsrl(MSR_IA32_APERF, aperf); |
1409 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1410 | tsc = rdtsc(); |
4fec7ad5 | 1411 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1412 | local_irq_restore(flags); |
4fec7ad5 | 1413 | return false; |
8e601a9f | 1414 | } |
4ab60c3f | 1415 | local_irq_restore(flags); |
b69880f9 | 1416 | |
c4ee841f | 1417 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1418 | cpu->sample.time = time; |
d37e2b76 DB |
1419 | cpu->sample.aperf = aperf; |
1420 | cpu->sample.mperf = mperf; | |
4055fad3 | 1421 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1422 | cpu->sample.aperf -= cpu->prev_aperf; |
1423 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1424 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1425 | |
93f0822d DB |
1426 | cpu->prev_aperf = aperf; |
1427 | cpu->prev_mperf = mperf; | |
4055fad3 | 1428 | cpu->prev_tsc = tsc; |
febce40f RW |
1429 | /* |
1430 | * First time this function is invoked in a given cycle, all of the | |
1431 | * previous sample data fields are equal to zero or stale and they must | |
1432 | * be populated with meaningful numbers for things to work, so assume | |
1433 | * that sample.time will always be reset before setting the utilization | |
1434 | * update hook and make the caller skip the sample then. | |
1435 | */ | |
eabd22c6 RW |
1436 | if (cpu->last_sample_time) { |
1437 | intel_pstate_calc_avg_perf(cpu); | |
1438 | return true; | |
1439 | } | |
1440 | return false; | |
93f0822d DB |
1441 | } |
1442 | ||
8fa520af PL |
1443 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1444 | { | |
c587c79f | 1445 | return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz); |
8fa520af PL |
1446 | } |
1447 | ||
bdcaa23f PL |
1448 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1449 | { | |
8edb0a6e RW |
1450 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1451 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1452 | } |
1453 | ||
d77d4888 | 1454 | static inline int32_t get_target_pstate(struct cpudata *cpu) |
e70eed2b PL |
1455 | { |
1456 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1457 | int32_t busy_frac, boost; |
0843e83c | 1458 | int target, avg_pstate; |
e70eed2b | 1459 | |
6e34e1f2 SP |
1460 | busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift, |
1461 | sample->tsc); | |
63d1d656 | 1462 | |
09c448d3 RW |
1463 | boost = cpu->iowait_boost; |
1464 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1465 | |
09c448d3 RW |
1466 | if (busy_frac < boost) |
1467 | busy_frac = boost; | |
63d1d656 | 1468 | |
09c448d3 | 1469 | sample->busy_scaled = busy_frac * 100; |
0843e83c | 1470 | |
7de32556 | 1471 | target = global.no_turbo || global.turbo_disabled ? |
0843e83c RW |
1472 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1473 | target += target >> 2; | |
1474 | target = mul_fp(target, busy_frac); | |
1475 | if (target < cpu->pstate.min_pstate) | |
1476 | target = cpu->pstate.min_pstate; | |
1477 | ||
1478 | /* | |
1479 | * If the average P-state during the previous cycle was higher than the | |
1480 | * current target, add 50% of the difference to the target to reduce | |
1481 | * possible performance oscillations and offset possible performance | |
1482 | * loss related to moving the workload from one CPU to another within | |
1483 | * a package/module. | |
1484 | */ | |
1485 | avg_pstate = get_avg_pstate(cpu); | |
1486 | if (avg_pstate > target) | |
1487 | target += (avg_pstate - target) >> 1; | |
1488 | ||
1489 | return target; | |
e70eed2b PL |
1490 | } |
1491 | ||
001c76f0 | 1492 | static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1493 | { |
b02aabe8 RW |
1494 | int max_pstate = intel_pstate_get_base_pstate(cpu); |
1495 | int min_pstate; | |
fdfdb2b1 | 1496 | |
1a4fe38a SP |
1497 | min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio); |
1498 | max_pstate = max(min_pstate, cpu->max_perf_ratio); | |
b02aabe8 | 1499 | return clamp_t(int, pstate, min_pstate, max_pstate); |
001c76f0 RW |
1500 | } |
1501 | ||
1502 | static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) | |
1503 | { | |
fdfdb2b1 RW |
1504 | if (pstate == cpu->pstate.current_pstate) |
1505 | return; | |
1506 | ||
bc95a454 | 1507 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1508 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1509 | } | |
1510 | ||
a891283e | 1511 | static void intel_pstate_adjust_pstate(struct cpudata *cpu) |
93f0822d | 1512 | { |
67dd9bf4 | 1513 | int from = cpu->pstate.current_pstate; |
4055fad3 | 1514 | struct sample *sample; |
a891283e | 1515 | int target_pstate; |
4055fad3 | 1516 | |
001c76f0 RW |
1517 | update_turbo_state(); |
1518 | ||
d77d4888 | 1519 | target_pstate = get_target_pstate(cpu); |
64078299 RW |
1520 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
1521 | trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); | |
fdfdb2b1 | 1522 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1523 | |
1524 | sample = &cpu->sample; | |
a1c9787d | 1525 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1526 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1527 | from, |
1528 | cpu->pstate.current_pstate, | |
1529 | sample->mperf, | |
1530 | sample->aperf, | |
1531 | sample->tsc, | |
3ba7bcaa SP |
1532 | get_avg_frequency(cpu), |
1533 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1534 | } |
1535 | ||
a4675fbc | 1536 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1537 | unsigned int flags) |
93f0822d | 1538 | { |
a4675fbc | 1539 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1540 | u64 delta_ns; |
1541 | ||
674e7541 VK |
1542 | /* Don't allow remote callbacks */ |
1543 | if (smp_processor_id() != cpu->cpu) | |
1544 | return; | |
1545 | ||
eabd22c6 RW |
1546 | if (flags & SCHED_CPUFREQ_IOWAIT) { |
1547 | cpu->iowait_boost = int_tofp(1); | |
7bde2d50 SP |
1548 | cpu->last_update = time; |
1549 | /* | |
1550 | * The last time the busy was 100% so P-state was max anyway | |
1551 | * so avoid overhead of computation. | |
1552 | */ | |
1553 | if (fp_toint(cpu->sample.busy_scaled) == 100) | |
1554 | return; | |
1555 | ||
1556 | goto set_pstate; | |
eabd22c6 RW |
1557 | } else if (cpu->iowait_boost) { |
1558 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1559 | delta_ns = time - cpu->last_update; | |
1560 | if (delta_ns > TICK_NSEC) | |
1561 | cpu->iowait_boost = 0; | |
09c448d3 | 1562 | } |
eabd22c6 | 1563 | cpu->last_update = time; |
09c448d3 | 1564 | delta_ns = time - cpu->sample.time; |
d77d4888 | 1565 | if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL) |
eabd22c6 | 1566 | return; |
4fec7ad5 | 1567 | |
7bde2d50 | 1568 | set_pstate: |
a891283e RW |
1569 | if (intel_pstate_sample(cpu, time)) |
1570 | intel_pstate_adjust_pstate(cpu); | |
67dd9bf4 | 1571 | } |
eabd22c6 | 1572 | |
2f49afc2 RW |
1573 | static struct pstate_funcs core_funcs = { |
1574 | .get_max = core_get_max_pstate, | |
1575 | .get_max_physical = core_get_max_pstate_physical, | |
1576 | .get_min = core_get_min_pstate, | |
1577 | .get_turbo = core_get_turbo_pstate, | |
1578 | .get_scaling = core_get_scaling, | |
1579 | .get_val = core_get_val, | |
de4a76cb RW |
1580 | }; |
1581 | ||
2f49afc2 RW |
1582 | static const struct pstate_funcs silvermont_funcs = { |
1583 | .get_max = atom_get_max_pstate, | |
1584 | .get_max_physical = atom_get_max_pstate, | |
1585 | .get_min = atom_get_min_pstate, | |
1586 | .get_turbo = atom_get_turbo_pstate, | |
1587 | .get_val = atom_get_val, | |
1588 | .get_scaling = silvermont_get_scaling, | |
1589 | .get_vid = atom_get_vid, | |
de4a76cb RW |
1590 | }; |
1591 | ||
2f49afc2 RW |
1592 | static const struct pstate_funcs airmont_funcs = { |
1593 | .get_max = atom_get_max_pstate, | |
1594 | .get_max_physical = atom_get_max_pstate, | |
1595 | .get_min = atom_get_min_pstate, | |
1596 | .get_turbo = atom_get_turbo_pstate, | |
1597 | .get_val = atom_get_val, | |
1598 | .get_scaling = airmont_get_scaling, | |
1599 | .get_vid = atom_get_vid, | |
de4a76cb RW |
1600 | }; |
1601 | ||
2f49afc2 RW |
1602 | static const struct pstate_funcs knl_funcs = { |
1603 | .get_max = core_get_max_pstate, | |
1604 | .get_max_physical = core_get_max_pstate_physical, | |
1605 | .get_min = core_get_min_pstate, | |
1606 | .get_turbo = knl_get_turbo_pstate, | |
6e34e1f2 | 1607 | .get_aperf_mperf_shift = knl_get_aperf_mperf_shift, |
2f49afc2 RW |
1608 | .get_scaling = core_get_scaling, |
1609 | .get_val = core_get_val, | |
de4a76cb RW |
1610 | }; |
1611 | ||
2f49afc2 RW |
1612 | static const struct pstate_funcs bxt_funcs = { |
1613 | .get_max = core_get_max_pstate, | |
1614 | .get_max_physical = core_get_max_pstate_physical, | |
1615 | .get_min = core_get_min_pstate, | |
1616 | .get_turbo = core_get_turbo_pstate, | |
1617 | .get_scaling = core_get_scaling, | |
1618 | .get_val = core_get_val, | |
de4a76cb RW |
1619 | }; |
1620 | ||
93f0822d | 1621 | #define ICPU(model, policy) \ |
6cbd7ee1 DB |
1622 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1623 | (unsigned long)&policy } | |
93f0822d DB |
1624 | |
1625 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
2f49afc2 RW |
1626 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs), |
1627 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs), | |
2811e5d5 | 1628 | ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs), |
2f49afc2 RW |
1629 | ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs), |
1630 | ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs), | |
1631 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs), | |
1632 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs), | |
1633 | ICPU(INTEL_FAM6_HASWELL_X, core_funcs), | |
1634 | ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs), | |
1635 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs), | |
1636 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs), | |
1637 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs), | |
1638 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs), | |
1639 | ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), | |
1640 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs), | |
1641 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), | |
1642 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs), | |
1643 | ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs), | |
1644 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs), | |
2811e5d5 | 1645 | ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, bxt_funcs), |
93f0822d DB |
1646 | {} |
1647 | }; | |
1648 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1649 | ||
29327c84 | 1650 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
2f49afc2 RW |
1651 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs), |
1652 | ICPU(INTEL_FAM6_BROADWELL_X, core_funcs), | |
1653 | ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs), | |
2f86dc4c DB |
1654 | {} |
1655 | }; | |
1656 | ||
6e978b22 | 1657 | static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { |
2f49afc2 | 1658 | ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs), |
6e978b22 SP |
1659 | {} |
1660 | }; | |
1661 | ||
93f0822d DB |
1662 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1663 | { | |
93f0822d DB |
1664 | struct cpudata *cpu; |
1665 | ||
eae48f04 SP |
1666 | cpu = all_cpu_data[cpunum]; |
1667 | ||
1668 | if (!cpu) { | |
c5a2ee7d | 1669 | cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); |
eae48f04 SP |
1670 | if (!cpu) |
1671 | return -ENOMEM; | |
1672 | ||
1673 | all_cpu_data[cpunum] = cpu; | |
eae48f04 | 1674 | |
984edbdc SP |
1675 | cpu->epp_default = -EINVAL; |
1676 | cpu->epp_powersave = -EINVAL; | |
1677 | cpu->epp_saved = -EINVAL; | |
eae48f04 | 1678 | } |
93f0822d DB |
1679 | |
1680 | cpu = all_cpu_data[cpunum]; | |
1681 | ||
93f0822d | 1682 | cpu->cpu = cpunum; |
ba88d433 | 1683 | |
a4675fbc | 1684 | if (hwp_active) { |
6e978b22 SP |
1685 | const struct x86_cpu_id *id; |
1686 | ||
1687 | id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); | |
1688 | if (id) | |
1689 | intel_pstate_disable_ee(cpunum); | |
1690 | ||
ba88d433 | 1691 | intel_pstate_hwp_enable(cpu); |
a4675fbc | 1692 | } |
ba88d433 | 1693 | |
179e8471 | 1694 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1695 | |
4836df17 | 1696 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
1697 | |
1698 | return 0; | |
1699 | } | |
1700 | ||
febce40f | 1701 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1702 | { |
febce40f RW |
1703 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1704 | ||
62611cb9 LB |
1705 | if (hwp_active) |
1706 | return; | |
1707 | ||
5ab666e0 RW |
1708 | if (cpu->update_util_set) |
1709 | return; | |
1710 | ||
febce40f RW |
1711 | /* Prevent intel_pstate_update_util() from using stale data. */ |
1712 | cpu->sample.time = 0; | |
67dd9bf4 | 1713 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
c4f3f70c | 1714 | intel_pstate_update_util); |
4578ee7e | 1715 | cpu->update_util_set = true; |
bb6ab52f RW |
1716 | } |
1717 | ||
1718 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1719 | { | |
4578ee7e CY |
1720 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
1721 | ||
1722 | if (!cpu_data->update_util_set) | |
1723 | return; | |
1724 | ||
0bed612b | 1725 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 1726 | cpu_data->update_util_set = false; |
bb6ab52f RW |
1727 | synchronize_sched(); |
1728 | } | |
1729 | ||
80b120ca RW |
1730 | static int intel_pstate_get_max_freq(struct cpudata *cpu) |
1731 | { | |
1732 | return global.turbo_disabled || global.no_turbo ? | |
1733 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; | |
1734 | } | |
1735 | ||
eae48f04 | 1736 | static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, |
c5a2ee7d | 1737 | struct cpudata *cpu) |
eae48f04 | 1738 | { |
80b120ca | 1739 | int max_freq = intel_pstate_get_max_freq(cpu); |
e4c204ce | 1740 | int32_t max_policy_perf, min_policy_perf; |
1a4fe38a | 1741 | int max_state, turbo_max; |
a410c03d | 1742 | |
1a4fe38a SP |
1743 | /* |
1744 | * HWP needs some special consideration, because on BDX the | |
1745 | * HWP_REQUEST uses abstract value to represent performance | |
1746 | * rather than pure ratios. | |
1747 | */ | |
1748 | if (hwp_active) { | |
1749 | intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state); | |
1750 | } else { | |
1751 | max_state = intel_pstate_get_base_pstate(cpu); | |
1752 | turbo_max = cpu->pstate.turbo_pstate; | |
1753 | } | |
1754 | ||
1755 | max_policy_perf = max_state * policy->max / max_freq; | |
5879f877 | 1756 | if (policy->max == policy->min) { |
e4c204ce | 1757 | min_policy_perf = max_policy_perf; |
5879f877 | 1758 | } else { |
1a4fe38a | 1759 | min_policy_perf = max_state * policy->min / max_freq; |
e4c204ce RW |
1760 | min_policy_perf = clamp_t(int32_t, min_policy_perf, |
1761 | 0, max_policy_perf); | |
5879f877 | 1762 | } |
eae48f04 | 1763 | |
1a4fe38a SP |
1764 | pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n", |
1765 | policy->cpu, max_state, | |
1766 | min_policy_perf, max_policy_perf); | |
1767 | ||
e4c204ce | 1768 | /* Normalize user input to [min_perf, max_perf] */ |
c5a2ee7d | 1769 | if (per_cpu_limits) { |
1a4fe38a SP |
1770 | cpu->min_perf_ratio = min_policy_perf; |
1771 | cpu->max_perf_ratio = max_policy_perf; | |
c5a2ee7d RW |
1772 | } else { |
1773 | int32_t global_min, global_max; | |
1774 | ||
1775 | /* Global limits are in percent of the maximum turbo P-state. */ | |
1a4fe38a SP |
1776 | global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100); |
1777 | global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100); | |
c5a2ee7d | 1778 | global_min = clamp_t(int32_t, global_min, 0, global_max); |
eae48f04 | 1779 | |
1a4fe38a SP |
1780 | pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu, |
1781 | global_min, global_max); | |
c5a2ee7d | 1782 | |
1a4fe38a SP |
1783 | cpu->min_perf_ratio = max(min_policy_perf, global_min); |
1784 | cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf); | |
1785 | cpu->max_perf_ratio = min(max_policy_perf, global_max); | |
1786 | cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio); | |
eae48f04 | 1787 | |
1a4fe38a SP |
1788 | /* Make sure min_perf <= max_perf */ |
1789 | cpu->min_perf_ratio = min(cpu->min_perf_ratio, | |
1790 | cpu->max_perf_ratio); | |
eae48f04 | 1791 | |
1a4fe38a SP |
1792 | } |
1793 | pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu, | |
1794 | cpu->max_perf_ratio, | |
1795 | cpu->min_perf_ratio); | |
eae48f04 SP |
1796 | } |
1797 | ||
93f0822d DB |
1798 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
1799 | { | |
3be9200d SP |
1800 | struct cpudata *cpu; |
1801 | ||
d3929b83 DB |
1802 | if (!policy->cpuinfo.max_freq) |
1803 | return -ENODEV; | |
1804 | ||
2c2c1af4 SP |
1805 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
1806 | policy->cpuinfo.max_freq, policy->max); | |
1807 | ||
a6c6ead1 | 1808 | cpu = all_cpu_data[policy->cpu]; |
2f1d407a RW |
1809 | cpu->policy = policy->policy; |
1810 | ||
b59fe540 SP |
1811 | mutex_lock(&intel_pstate_limits_lock); |
1812 | ||
c5a2ee7d | 1813 | intel_pstate_update_perf_limits(policy, cpu); |
a240c4aa | 1814 | |
2f1d407a | 1815 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { |
a6c6ead1 RW |
1816 | /* |
1817 | * NOHZ_FULL CPUs need this as the governor callback may not | |
1818 | * be invoked on them. | |
1819 | */ | |
1820 | intel_pstate_clear_update_util_hook(policy->cpu); | |
1821 | intel_pstate_max_within_limits(cpu); | |
82b4e03e LB |
1822 | } else { |
1823 | intel_pstate_set_update_util_hook(policy->cpu); | |
a6c6ead1 RW |
1824 | } |
1825 | ||
5f98ced1 | 1826 | if (hwp_active) |
2bfc4cbb | 1827 | intel_pstate_hwp_set(policy->cpu); |
2f86dc4c | 1828 | |
b59fe540 SP |
1829 | mutex_unlock(&intel_pstate_limits_lock); |
1830 | ||
93f0822d DB |
1831 | return 0; |
1832 | } | |
1833 | ||
80b120ca RW |
1834 | static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy, |
1835 | struct cpudata *cpu) | |
1836 | { | |
1837 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && | |
1838 | policy->max < policy->cpuinfo.max_freq && | |
1839 | policy->max > cpu->pstate.max_freq) { | |
1840 | pr_debug("policy->max > max non turbo frequency\n"); | |
1841 | policy->max = policy->cpuinfo.max_freq; | |
1842 | } | |
1843 | } | |
1844 | ||
93f0822d DB |
1845 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) |
1846 | { | |
7d9a8a9f | 1847 | struct cpudata *cpu = all_cpu_data[policy->cpu]; |
7d9a8a9f SP |
1848 | |
1849 | update_turbo_state(); | |
80b120ca RW |
1850 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
1851 | intel_pstate_get_max_freq(cpu)); | |
93f0822d | 1852 | |
285cb990 | 1853 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1854 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1855 | return -EINVAL; |
1856 | ||
80b120ca RW |
1857 | intel_pstate_adjust_policy_max(policy, cpu); |
1858 | ||
93f0822d DB |
1859 | return 0; |
1860 | } | |
1861 | ||
001c76f0 RW |
1862 | static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
1863 | { | |
1864 | intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); | |
1865 | } | |
1866 | ||
bb18008f | 1867 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1868 | { |
001c76f0 | 1869 | pr_debug("CPU %d exiting\n", policy->cpu); |
93f0822d | 1870 | |
001c76f0 | 1871 | intel_pstate_clear_update_util_hook(policy->cpu); |
984edbdc SP |
1872 | if (hwp_active) |
1873 | intel_pstate_hwp_save_state(policy); | |
1874 | else | |
001c76f0 RW |
1875 | intel_cpufreq_stop_cpu(policy); |
1876 | } | |
bb18008f | 1877 | |
001c76f0 RW |
1878 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
1879 | { | |
1880 | intel_pstate_exit_perf_limits(policy); | |
a4675fbc | 1881 | |
001c76f0 | 1882 | policy->fast_switch_possible = false; |
2f86dc4c | 1883 | |
001c76f0 | 1884 | return 0; |
93f0822d DB |
1885 | } |
1886 | ||
001c76f0 | 1887 | static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1888 | { |
93f0822d | 1889 | struct cpudata *cpu; |
52e0a509 | 1890 | int rc; |
93f0822d DB |
1891 | |
1892 | rc = intel_pstate_init_cpu(policy->cpu); | |
1893 | if (rc) | |
1894 | return rc; | |
1895 | ||
1896 | cpu = all_cpu_data[policy->cpu]; | |
1897 | ||
1a4fe38a SP |
1898 | cpu->max_perf_ratio = 0xFF; |
1899 | cpu->min_perf_ratio = 0; | |
93f0822d | 1900 | |
b27580b0 DB |
1901 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1902 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1903 | |
1904 | /* cpuinfo and default policy values */ | |
b27580b0 | 1905 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e | 1906 | update_turbo_state(); |
7de32556 | 1907 | policy->cpuinfo.max_freq = global.turbo_disabled ? |
983e600e SP |
1908 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1909 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
1910 | ||
9522a2ff | 1911 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d | 1912 | |
001c76f0 RW |
1913 | policy->fast_switch_possible = true; |
1914 | ||
93f0822d DB |
1915 | return 0; |
1916 | } | |
1917 | ||
001c76f0 | 1918 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
9522a2ff | 1919 | { |
001c76f0 RW |
1920 | int ret = __intel_pstate_cpu_init(policy); |
1921 | ||
1922 | if (ret) | |
1923 | return ret; | |
1924 | ||
7de32556 | 1925 | if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) |
001c76f0 RW |
1926 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1927 | else | |
1928 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
9522a2ff SP |
1929 | |
1930 | return 0; | |
1931 | } | |
1932 | ||
001c76f0 | 1933 | static struct cpufreq_driver intel_pstate = { |
93f0822d DB |
1934 | .flags = CPUFREQ_CONST_LOOPS, |
1935 | .verify = intel_pstate_verify_policy, | |
1936 | .setpolicy = intel_pstate_set_policy, | |
984edbdc | 1937 | .suspend = intel_pstate_hwp_save_state, |
8442885f | 1938 | .resume = intel_pstate_resume, |
93f0822d | 1939 | .init = intel_pstate_cpu_init, |
9522a2ff | 1940 | .exit = intel_pstate_cpu_exit, |
bb18008f | 1941 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1942 | .name = "intel_pstate", |
93f0822d DB |
1943 | }; |
1944 | ||
001c76f0 RW |
1945 | static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) |
1946 | { | |
1947 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
001c76f0 RW |
1948 | |
1949 | update_turbo_state(); | |
80b120ca RW |
1950 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
1951 | intel_pstate_get_max_freq(cpu)); | |
001c76f0 | 1952 | |
80b120ca | 1953 | intel_pstate_adjust_policy_max(policy, cpu); |
001c76f0 | 1954 | |
c5a2ee7d RW |
1955 | intel_pstate_update_perf_limits(policy, cpu); |
1956 | ||
001c76f0 RW |
1957 | return 0; |
1958 | } | |
1959 | ||
001c76f0 RW |
1960 | static int intel_cpufreq_target(struct cpufreq_policy *policy, |
1961 | unsigned int target_freq, | |
1962 | unsigned int relation) | |
1963 | { | |
1964 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
1965 | struct cpufreq_freqs freqs; | |
1966 | int target_pstate; | |
1967 | ||
64897b20 RW |
1968 | update_turbo_state(); |
1969 | ||
001c76f0 | 1970 | freqs.old = policy->cur; |
64897b20 | 1971 | freqs.new = target_freq; |
001c76f0 RW |
1972 | |
1973 | cpufreq_freq_transition_begin(policy, &freqs); | |
1974 | switch (relation) { | |
1975 | case CPUFREQ_RELATION_L: | |
1976 | target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
1977 | break; | |
1978 | case CPUFREQ_RELATION_H: | |
1979 | target_pstate = freqs.new / cpu->pstate.scaling; | |
1980 | break; | |
1981 | default: | |
1982 | target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
1983 | break; | |
1984 | } | |
1985 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); | |
1986 | if (target_pstate != cpu->pstate.current_pstate) { | |
1987 | cpu->pstate.current_pstate = target_pstate; | |
1988 | wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, | |
1989 | pstate_funcs.get_val(cpu, target_pstate)); | |
1990 | } | |
64078299 | 1991 | freqs.new = target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
1992 | cpufreq_freq_transition_end(policy, &freqs, false); |
1993 | ||
1994 | return 0; | |
1995 | } | |
1996 | ||
1997 | static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, | |
1998 | unsigned int target_freq) | |
1999 | { | |
2000 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2001 | int target_pstate; | |
2002 | ||
64897b20 RW |
2003 | update_turbo_state(); |
2004 | ||
001c76f0 | 2005 | target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); |
64078299 | 2006 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
001c76f0 | 2007 | intel_pstate_update_pstate(cpu, target_pstate); |
64078299 | 2008 | return target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2009 | } |
2010 | ||
2011 | static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
2012 | { | |
2013 | int ret = __intel_pstate_cpu_init(policy); | |
2014 | ||
2015 | if (ret) | |
2016 | return ret; | |
2017 | ||
2018 | policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; | |
1b72e7fd | 2019 | policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY; |
001c76f0 RW |
2020 | /* This reflects the intel_pstate_get_cpu_pstates() setting. */ |
2021 | policy->cur = policy->cpuinfo.min_freq; | |
2022 | ||
2023 | return 0; | |
2024 | } | |
2025 | ||
2026 | static struct cpufreq_driver intel_cpufreq = { | |
2027 | .flags = CPUFREQ_CONST_LOOPS, | |
2028 | .verify = intel_cpufreq_verify_policy, | |
2029 | .target = intel_cpufreq_target, | |
2030 | .fast_switch = intel_cpufreq_fast_switch, | |
2031 | .init = intel_cpufreq_cpu_init, | |
2032 | .exit = intel_pstate_cpu_exit, | |
2033 | .stop_cpu = intel_cpufreq_stop_cpu, | |
2034 | .name = "intel_cpufreq", | |
2035 | }; | |
2036 | ||
ee8df89a | 2037 | static struct cpufreq_driver *default_driver = &intel_pstate; |
001c76f0 | 2038 | |
fb1fe104 RW |
2039 | static void intel_pstate_driver_cleanup(void) |
2040 | { | |
2041 | unsigned int cpu; | |
2042 | ||
2043 | get_online_cpus(); | |
2044 | for_each_online_cpu(cpu) { | |
2045 | if (all_cpu_data[cpu]) { | |
2046 | if (intel_pstate_driver == &intel_pstate) | |
2047 | intel_pstate_clear_update_util_hook(cpu); | |
2048 | ||
2049 | kfree(all_cpu_data[cpu]); | |
2050 | all_cpu_data[cpu] = NULL; | |
2051 | } | |
2052 | } | |
2053 | put_online_cpus(); | |
ee8df89a | 2054 | intel_pstate_driver = NULL; |
fb1fe104 RW |
2055 | } |
2056 | ||
ee8df89a | 2057 | static int intel_pstate_register_driver(struct cpufreq_driver *driver) |
fb1fe104 RW |
2058 | { |
2059 | int ret; | |
2060 | ||
c5a2ee7d RW |
2061 | memset(&global, 0, sizeof(global)); |
2062 | global.max_perf_pct = 100; | |
c3a49c89 | 2063 | |
ee8df89a | 2064 | intel_pstate_driver = driver; |
fb1fe104 RW |
2065 | ret = cpufreq_register_driver(intel_pstate_driver); |
2066 | if (ret) { | |
2067 | intel_pstate_driver_cleanup(); | |
2068 | return ret; | |
2069 | } | |
2070 | ||
c5a2ee7d RW |
2071 | global.min_perf_pct = min_perf_pct_min(); |
2072 | ||
fb1fe104 RW |
2073 | return 0; |
2074 | } | |
2075 | ||
2076 | static int intel_pstate_unregister_driver(void) | |
2077 | { | |
2078 | if (hwp_active) | |
2079 | return -EBUSY; | |
2080 | ||
fb1fe104 RW |
2081 | cpufreq_unregister_driver(intel_pstate_driver); |
2082 | intel_pstate_driver_cleanup(); | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
2087 | static ssize_t intel_pstate_show_status(char *buf) | |
2088 | { | |
ee8df89a | 2089 | if (!intel_pstate_driver) |
fb1fe104 RW |
2090 | return sprintf(buf, "off\n"); |
2091 | ||
2092 | return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? | |
2093 | "active" : "passive"); | |
2094 | } | |
2095 | ||
2096 | static int intel_pstate_update_status(const char *buf, size_t size) | |
2097 | { | |
2098 | int ret; | |
2099 | ||
2100 | if (size == 3 && !strncmp(buf, "off", size)) | |
ee8df89a | 2101 | return intel_pstate_driver ? |
fb1fe104 RW |
2102 | intel_pstate_unregister_driver() : -EINVAL; |
2103 | ||
2104 | if (size == 6 && !strncmp(buf, "active", size)) { | |
ee8df89a | 2105 | if (intel_pstate_driver) { |
fb1fe104 RW |
2106 | if (intel_pstate_driver == &intel_pstate) |
2107 | return 0; | |
2108 | ||
2109 | ret = intel_pstate_unregister_driver(); | |
2110 | if (ret) | |
2111 | return ret; | |
2112 | } | |
2113 | ||
ee8df89a | 2114 | return intel_pstate_register_driver(&intel_pstate); |
fb1fe104 RW |
2115 | } |
2116 | ||
2117 | if (size == 7 && !strncmp(buf, "passive", size)) { | |
ee8df89a | 2118 | if (intel_pstate_driver) { |
0042b2c0 | 2119 | if (intel_pstate_driver == &intel_cpufreq) |
fb1fe104 RW |
2120 | return 0; |
2121 | ||
2122 | ret = intel_pstate_unregister_driver(); | |
2123 | if (ret) | |
2124 | return ret; | |
2125 | } | |
2126 | ||
ee8df89a | 2127 | return intel_pstate_register_driver(&intel_cpufreq); |
fb1fe104 RW |
2128 | } |
2129 | ||
2130 | return -EINVAL; | |
2131 | } | |
2132 | ||
eed43609 JZ |
2133 | static int no_load __initdata; |
2134 | static int no_hwp __initdata; | |
2135 | static int hwp_only __initdata; | |
29327c84 | 2136 | static unsigned int force_load __initdata; |
6be26498 | 2137 | |
29327c84 | 2138 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 2139 | { |
016c8150 | 2140 | if (!pstate_funcs.get_max() || |
c410833a SK |
2141 | !pstate_funcs.get_min() || |
2142 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
2143 | return -ENODEV; |
2144 | ||
b563b4e3 DB |
2145 | return 0; |
2146 | } | |
016c8150 | 2147 | |
29327c84 | 2148 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
2149 | { |
2150 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 2151 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
2152 | pstate_funcs.get_min = funcs->get_min; |
2153 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 2154 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 2155 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 2156 | pstate_funcs.get_vid = funcs->get_vid; |
6e34e1f2 | 2157 | pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift; |
016c8150 DB |
2158 | } |
2159 | ||
9522a2ff | 2160 | #ifdef CONFIG_ACPI |
fbbcdc07 | 2161 | |
29327c84 | 2162 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
2163 | { |
2164 | int i; | |
2165 | ||
2166 | for_each_possible_cpu(i) { | |
2167 | acpi_status status; | |
2168 | union acpi_object *pss; | |
2169 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
2170 | struct acpi_processor *pr = per_cpu(processors, i); | |
2171 | ||
2172 | if (!pr) | |
2173 | continue; | |
2174 | ||
2175 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
2176 | if (ACPI_FAILURE(status)) | |
2177 | continue; | |
2178 | ||
2179 | pss = buffer.pointer; | |
2180 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
2181 | kfree(pss); | |
2182 | return false; | |
2183 | } | |
2184 | ||
2185 | kfree(pss); | |
2186 | } | |
2187 | ||
2188 | return true; | |
2189 | } | |
2190 | ||
4bca0a23 RW |
2191 | static bool __init intel_pstate_no_acpi_pcch(void) |
2192 | { | |
2193 | acpi_status status; | |
2194 | acpi_handle handle; | |
2195 | ||
2196 | status = acpi_get_handle(NULL, "\\_SB", &handle); | |
2197 | if (ACPI_FAILURE(status)) | |
2198 | return true; | |
2199 | ||
2200 | return !acpi_has_method(handle, "PCCH"); | |
2201 | } | |
2202 | ||
29327c84 | 2203 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 2204 | { |
2205 | int i; | |
2206 | ||
2207 | for_each_possible_cpu(i) { | |
2208 | struct acpi_processor *pr = per_cpu(processors, i); | |
2209 | ||
2210 | if (!pr) | |
2211 | continue; | |
2212 | if (acpi_has_method(pr->handle, "_PPC")) | |
2213 | return true; | |
2214 | } | |
2215 | return false; | |
2216 | } | |
2217 | ||
2218 | enum { | |
2219 | PSS, | |
2220 | PPC, | |
2221 | }; | |
2222 | ||
fbbcdc07 | 2223 | /* Hardware vendor-specific info that has its own power management modes */ |
5e932321 TK |
2224 | static struct acpi_platform_list plat_info[] __initdata = { |
2225 | {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS}, | |
2226 | {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2227 | {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2228 | {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2229 | {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2230 | {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2231 | {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2232 | {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2233 | {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2234 | {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2235 | {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2236 | {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2237 | {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2238 | {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2239 | {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC}, | |
2240 | { } /* End */ | |
fbbcdc07 AH |
2241 | }; |
2242 | ||
29327c84 | 2243 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 | 2244 | { |
2f86dc4c DB |
2245 | const struct x86_cpu_id *id; |
2246 | u64 misc_pwr; | |
5e932321 | 2247 | int idx; |
2f86dc4c DB |
2248 | |
2249 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
2250 | if (id) { | |
2251 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
2252 | if ( misc_pwr & (1 << 8)) | |
2253 | return true; | |
2254 | } | |
fbbcdc07 | 2255 | |
5e932321 TK |
2256 | idx = acpi_match_platform_list(plat_info); |
2257 | if (idx < 0) | |
fbbcdc07 AH |
2258 | return false; |
2259 | ||
5e932321 TK |
2260 | switch (plat_info[idx].data) { |
2261 | case PSS: | |
4bca0a23 RW |
2262 | if (!intel_pstate_no_acpi_pss()) |
2263 | return false; | |
2264 | ||
2265 | return intel_pstate_no_acpi_pcch(); | |
5e932321 TK |
2266 | case PPC: |
2267 | return intel_pstate_has_acpi_ppc() && !force_load; | |
fbbcdc07 AH |
2268 | } |
2269 | ||
2270 | return false; | |
2271 | } | |
d0ea59e1 RW |
2272 | |
2273 | static void intel_pstate_request_control_from_smm(void) | |
2274 | { | |
2275 | /* | |
2276 | * It may be unsafe to request P-states control from SMM if _PPC support | |
2277 | * has not been enabled. | |
2278 | */ | |
2279 | if (acpi_ppc) | |
2280 | acpi_processor_pstate_control(); | |
2281 | } | |
fbbcdc07 AH |
2282 | #else /* CONFIG_ACPI not enabled */ |
2283 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 2284 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
d0ea59e1 | 2285 | static inline void intel_pstate_request_control_from_smm(void) {} |
fbbcdc07 AH |
2286 | #endif /* CONFIG_ACPI */ |
2287 | ||
8da0f2d9 SP |
2288 | #define INTEL_PSTATE_HWP_BROADWELL 0x01 |
2289 | ||
2290 | #define ICPU_HWP(model, hwp_mode) \ | |
2291 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode } | |
2292 | ||
7791e4aa | 2293 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
8da0f2d9 SP |
2294 | ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL), |
2295 | ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL), | |
2296 | ICPU_HWP(X86_MODEL_ANY, 0), | |
7791e4aa SP |
2297 | {} |
2298 | }; | |
2299 | ||
93f0822d DB |
2300 | static int __init intel_pstate_init(void) |
2301 | { | |
8da0f2d9 | 2302 | const struct x86_cpu_id *id; |
eb5139d1 | 2303 | int rc; |
93f0822d | 2304 | |
6be26498 DB |
2305 | if (no_load) |
2306 | return -ENODEV; | |
2307 | ||
8da0f2d9 SP |
2308 | id = x86_match_cpu(hwp_support_ids); |
2309 | if (id) { | |
2f49afc2 | 2310 | copy_cpu_funcs(&core_funcs); |
c4f3f70c | 2311 | if (!no_hwp) { |
eb5139d1 | 2312 | hwp_active++; |
8da0f2d9 | 2313 | hwp_mode_bdw = id->driver_data; |
eb5139d1 RW |
2314 | intel_pstate.attr = hwp_cpufreq_attrs; |
2315 | goto hwp_cpu_matched; | |
2316 | } | |
2317 | } else { | |
eb5139d1 RW |
2318 | id = x86_match_cpu(intel_pstate_cpu_ids); |
2319 | if (!id) | |
2320 | return -ENODEV; | |
93f0822d | 2321 | |
2f49afc2 | 2322 | copy_cpu_funcs((struct pstate_funcs *)id->driver_data); |
eb5139d1 | 2323 | } |
016c8150 | 2324 | |
b563b4e3 DB |
2325 | if (intel_pstate_msrs_not_valid()) |
2326 | return -ENODEV; | |
2327 | ||
7791e4aa SP |
2328 | hwp_cpu_matched: |
2329 | /* | |
2330 | * The Intel pstate driver will be ignored if the platform | |
2331 | * firmware has its own power management modes. | |
2332 | */ | |
2333 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
2334 | return -ENODEV; | |
2335 | ||
fb1fe104 RW |
2336 | if (!hwp_active && hwp_only) |
2337 | return -ENOTSUPP; | |
2338 | ||
4836df17 | 2339 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 2340 | |
b57ffac5 | 2341 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
2342 | if (!all_cpu_data) |
2343 | return -ENOMEM; | |
93f0822d | 2344 | |
d0ea59e1 RW |
2345 | intel_pstate_request_control_from_smm(); |
2346 | ||
93f0822d | 2347 | intel_pstate_sysfs_expose_params(); |
b69880f9 | 2348 | |
0c30b65b | 2349 | mutex_lock(&intel_pstate_driver_lock); |
ee8df89a | 2350 | rc = intel_pstate_register_driver(default_driver); |
0c30b65b | 2351 | mutex_unlock(&intel_pstate_driver_lock); |
fb1fe104 RW |
2352 | if (rc) |
2353 | return rc; | |
366430b5 | 2354 | |
7791e4aa | 2355 | if (hwp_active) |
4836df17 | 2356 | pr_info("HWP enabled\n"); |
7791e4aa | 2357 | |
fb1fe104 | 2358 | return 0; |
93f0822d DB |
2359 | } |
2360 | device_initcall(intel_pstate_init); | |
2361 | ||
6be26498 DB |
2362 | static int __init intel_pstate_setup(char *str) |
2363 | { | |
2364 | if (!str) | |
2365 | return -EINVAL; | |
2366 | ||
001c76f0 | 2367 | if (!strcmp(str, "disable")) { |
6be26498 | 2368 | no_load = 1; |
001c76f0 RW |
2369 | } else if (!strcmp(str, "passive")) { |
2370 | pr_info("Passive mode enabled\n"); | |
ee8df89a | 2371 | default_driver = &intel_cpufreq; |
001c76f0 RW |
2372 | no_hwp = 1; |
2373 | } | |
539342f6 | 2374 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 2375 | pr_info("HWP disabled\n"); |
2f86dc4c | 2376 | no_hwp = 1; |
539342f6 | 2377 | } |
aa4ea34d EZ |
2378 | if (!strcmp(str, "force")) |
2379 | force_load = 1; | |
d64c3b0b KCA |
2380 | if (!strcmp(str, "hwp_only")) |
2381 | hwp_only = 1; | |
eae48f04 SP |
2382 | if (!strcmp(str, "per_cpu_perf_limits")) |
2383 | per_cpu_limits = true; | |
9522a2ff SP |
2384 | |
2385 | #ifdef CONFIG_ACPI | |
2386 | if (!strcmp(str, "support_acpi_ppc")) | |
2387 | acpi_ppc = true; | |
2388 | #endif | |
2389 | ||
6be26498 DB |
2390 | return 0; |
2391 | } | |
2392 | early_param("intel_pstate", intel_pstate_setup); | |
2393 | ||
93f0822d DB |
2394 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
2395 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
2396 | MODULE_LICENSE("GPL"); |