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93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#include <linux/kernel.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/ktime.h>
17#include <linux/hrtimer.h>
18#include <linux/tick.h>
19#include <linux/slab.h>
20#include <linux/sched.h>
21#include <linux/list.h>
22#include <linux/cpu.h>
23#include <linux/cpufreq.h>
24#include <linux/sysfs.h>
25#include <linux/types.h>
26#include <linux/fs.h>
27#include <linux/debugfs.h>
fbbcdc07 28#include <linux/acpi.h>
93f0822d
DB
29#include <trace/events/power.h>
30
31#include <asm/div64.h>
32#include <asm/msr.h>
33#include <asm/cpu_device_id.h>
34
35#define SAMPLE_COUNT 3
36
61d8d2ab
DB
37#define BYT_RATIOS 0x66a
38#define BYT_VIDS 0x66b
39#define BYT_TURBO_RATIOS 0x66c
21855ff5 40#define BYT_TURBO_VIDS 0x66d
61d8d2ab 41
19e77c28 42
e66c1768 43#define FRAC_BITS 6
93f0822d
DB
44#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
45#define fp_toint(X) ((X) >> FRAC_BITS)
e66c1768 46#define FP_ROUNDUP(X) ((X) += 1 << FRAC_BITS)
93f0822d
DB
47
48static inline int32_t mul_fp(int32_t x, int32_t y)
49{
50 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
51}
52
53static inline int32_t div_fp(int32_t x, int32_t y)
54{
55 return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);
56}
57
58struct sample {
d253d2a5 59 int32_t core_pct_busy;
93f0822d
DB
60 u64 aperf;
61 u64 mperf;
fcb6a15c 62 unsigned long long tsc;
93f0822d
DB
63 int freq;
64};
65
66struct pstate_data {
67 int current_pstate;
68 int min_pstate;
69 int max_pstate;
70 int turbo_pstate;
71};
72
007bea09 73struct vid_data {
21855ff5
DB
74 int min;
75 int max;
76 int turbo;
007bea09
DB
77 int32_t ratio;
78};
79
93f0822d
DB
80struct _pid {
81 int setpoint;
82 int32_t integral;
83 int32_t p_gain;
84 int32_t i_gain;
85 int32_t d_gain;
86 int deadband;
d253d2a5 87 int32_t last_err;
93f0822d
DB
88};
89
90struct cpudata {
91 int cpu;
92
93 char name[64];
94
95 struct timer_list timer;
96
93f0822d 97 struct pstate_data pstate;
007bea09 98 struct vid_data vid;
93f0822d 99 struct _pid pid;
93f0822d 100
93f0822d
DB
101 u64 prev_aperf;
102 u64 prev_mperf;
fcb6a15c 103 unsigned long long prev_tsc;
d37e2b76 104 struct sample sample;
93f0822d
DB
105};
106
107static struct cpudata **all_cpu_data;
108struct pstate_adjust_policy {
109 int sample_rate_ms;
110 int deadband;
111 int setpoint;
112 int p_gain_pct;
113 int d_gain_pct;
114 int i_gain_pct;
115};
116
016c8150
DB
117struct pstate_funcs {
118 int (*get_max)(void);
119 int (*get_min)(void);
120 int (*get_turbo)(void);
007bea09
DB
121 void (*set)(struct cpudata*, int pstate);
122 void (*get_vid)(struct cpudata *);
93f0822d
DB
123};
124
016c8150
DB
125struct cpu_defaults {
126 struct pstate_adjust_policy pid_policy;
127 struct pstate_funcs funcs;
93f0822d
DB
128};
129
016c8150
DB
130static struct pstate_adjust_policy pid_params;
131static struct pstate_funcs pstate_funcs;
132
93f0822d
DB
133struct perf_limits {
134 int no_turbo;
135 int max_perf_pct;
136 int min_perf_pct;
137 int32_t max_perf;
138 int32_t min_perf;
d8f469e9
DB
139 int max_policy_pct;
140 int max_sysfs_pct;
93f0822d
DB
141};
142
143static struct perf_limits limits = {
144 .no_turbo = 0,
145 .max_perf_pct = 100,
146 .max_perf = int_tofp(1),
147 .min_perf_pct = 0,
148 .min_perf = 0,
d8f469e9
DB
149 .max_policy_pct = 100,
150 .max_sysfs_pct = 100,
93f0822d
DB
151};
152
153static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
154 int deadband, int integral) {
155 pid->setpoint = setpoint;
156 pid->deadband = deadband;
157 pid->integral = int_tofp(integral);
d98d099b 158 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB
159}
160
161static inline void pid_p_gain_set(struct _pid *pid, int percent)
162{
163 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
164}
165
166static inline void pid_i_gain_set(struct _pid *pid, int percent)
167{
168 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
169}
170
171static inline void pid_d_gain_set(struct _pid *pid, int percent)
172{
173
174 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
175}
176
d253d2a5 177static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 178{
d253d2a5 179 signed int result;
93f0822d
DB
180 int32_t pterm, dterm, fp_error;
181 int32_t integral_limit;
182
d253d2a5 183 fp_error = int_tofp(pid->setpoint) - busy;
93f0822d 184
d253d2a5 185 if (abs(fp_error) <= int_tofp(pid->deadband))
93f0822d
DB
186 return 0;
187
188 pterm = mul_fp(pid->p_gain, fp_error);
189
190 pid->integral += fp_error;
191
192 /* limit the integral term */
193 integral_limit = int_tofp(30);
194 if (pid->integral > integral_limit)
195 pid->integral = integral_limit;
196 if (pid->integral < -integral_limit)
197 pid->integral = -integral_limit;
198
d253d2a5
BS
199 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
200 pid->last_err = fp_error;
93f0822d
DB
201
202 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
203
204 return (signed int)fp_toint(result);
205}
206
207static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
208{
016c8150
DB
209 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
210 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
211 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d
DB
212
213 pid_reset(&cpu->pid,
016c8150 214 pid_params.setpoint,
93f0822d 215 100,
016c8150 216 pid_params.deadband,
93f0822d
DB
217 0);
218}
219
93f0822d
DB
220static inline void intel_pstate_reset_all_pid(void)
221{
222 unsigned int cpu;
223 for_each_online_cpu(cpu) {
224 if (all_cpu_data[cpu])
225 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
226 }
227}
228
229/************************** debugfs begin ************************/
230static int pid_param_set(void *data, u64 val)
231{
232 *(u32 *)data = val;
233 intel_pstate_reset_all_pid();
234 return 0;
235}
236static int pid_param_get(void *data, u64 *val)
237{
238 *val = *(u32 *)data;
239 return 0;
240}
241DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,
242 pid_param_set, "%llu\n");
243
244struct pid_param {
245 char *name;
246 void *value;
247};
248
249static struct pid_param pid_files[] = {
016c8150
DB
250 {"sample_rate_ms", &pid_params.sample_rate_ms},
251 {"d_gain_pct", &pid_params.d_gain_pct},
252 {"i_gain_pct", &pid_params.i_gain_pct},
253 {"deadband", &pid_params.deadband},
254 {"setpoint", &pid_params.setpoint},
255 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
DB
256 {NULL, NULL}
257};
258
259static struct dentry *debugfs_parent;
260static void intel_pstate_debug_expose_params(void)
261{
262 int i = 0;
263
264 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
265 if (IS_ERR_OR_NULL(debugfs_parent))
266 return;
267 while (pid_files[i].name) {
268 debugfs_create_file(pid_files[i].name, 0660,
269 debugfs_parent, pid_files[i].value,
270 &fops_pid_param);
271 i++;
272 }
273}
274
275/************************** debugfs end ************************/
276
277/************************** sysfs begin ************************/
278#define show_one(file_name, object) \
279 static ssize_t show_##file_name \
280 (struct kobject *kobj, struct attribute *attr, char *buf) \
281 { \
282 return sprintf(buf, "%u\n", limits.object); \
283 }
284
285static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
286 const char *buf, size_t count)
287{
288 unsigned int input;
289 int ret;
290 ret = sscanf(buf, "%u", &input);
291 if (ret != 1)
292 return -EINVAL;
293 limits.no_turbo = clamp_t(int, input, 0 , 1);
294
295 return count;
296}
297
298static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
299 const char *buf, size_t count)
300{
301 unsigned int input;
302 int ret;
303 ret = sscanf(buf, "%u", &input);
304 if (ret != 1)
305 return -EINVAL;
306
d8f469e9
DB
307 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
308 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
93f0822d
DB
309 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
310 return count;
311}
312
313static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
314 const char *buf, size_t count)
315{
316 unsigned int input;
317 int ret;
318 ret = sscanf(buf, "%u", &input);
319 if (ret != 1)
320 return -EINVAL;
321 limits.min_perf_pct = clamp_t(int, input, 0 , 100);
322 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
323
324 return count;
325}
326
327show_one(no_turbo, no_turbo);
328show_one(max_perf_pct, max_perf_pct);
329show_one(min_perf_pct, min_perf_pct);
330
331define_one_global_rw(no_turbo);
332define_one_global_rw(max_perf_pct);
333define_one_global_rw(min_perf_pct);
334
335static struct attribute *intel_pstate_attributes[] = {
336 &no_turbo.attr,
337 &max_perf_pct.attr,
338 &min_perf_pct.attr,
339 NULL
340};
341
342static struct attribute_group intel_pstate_attr_group = {
343 .attrs = intel_pstate_attributes,
344};
345static struct kobject *intel_pstate_kobject;
346
347static void intel_pstate_sysfs_expose_params(void)
348{
349 int rc;
350
351 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
352 &cpu_subsys.dev_root->kobj);
353 BUG_ON(!intel_pstate_kobject);
354 rc = sysfs_create_group(intel_pstate_kobject,
355 &intel_pstate_attr_group);
356 BUG_ON(rc);
357}
358
359/************************** sysfs end ************************/
19e77c28
DB
360static int byt_get_min_pstate(void)
361{
362 u64 value;
363 rdmsrl(BYT_RATIOS, value);
21855ff5 364 return (value >> 8) & 0x3F;
19e77c28
DB
365}
366
367static int byt_get_max_pstate(void)
368{
369 u64 value;
370 rdmsrl(BYT_RATIOS, value);
21855ff5 371 return (value >> 16) & 0x3F;
19e77c28 372}
93f0822d 373
61d8d2ab
DB
374static int byt_get_turbo_pstate(void)
375{
376 u64 value;
377 rdmsrl(BYT_TURBO_RATIOS, value);
378 return value & 0x3F;
379}
380
007bea09
DB
381static void byt_set_pstate(struct cpudata *cpudata, int pstate)
382{
383 u64 val;
384 int32_t vid_fp;
385 u32 vid;
386
387 val = pstate << 8;
388 if (limits.no_turbo)
389 val |= (u64)1 << 32;
390
391 vid_fp = cpudata->vid.min + mul_fp(
392 int_tofp(pstate - cpudata->pstate.min_pstate),
393 cpudata->vid.ratio);
394
395 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
396 vid = fp_toint(vid_fp);
397
21855ff5
DB
398 if (pstate > cpudata->pstate.max_pstate)
399 vid = cpudata->vid.turbo;
400
007bea09
DB
401 val |= vid;
402
403 wrmsrl(MSR_IA32_PERF_CTL, val);
404}
405
406static void byt_get_vid(struct cpudata *cpudata)
407{
408 u64 value;
409
21855ff5 410
007bea09 411 rdmsrl(BYT_VIDS, value);
21855ff5
DB
412 cpudata->vid.min = int_tofp((value >> 8) & 0x3f);
413 cpudata->vid.max = int_tofp((value >> 16) & 0x3f);
007bea09
DB
414 cpudata->vid.ratio = div_fp(
415 cpudata->vid.max - cpudata->vid.min,
416 int_tofp(cpudata->pstate.max_pstate -
417 cpudata->pstate.min_pstate));
21855ff5
DB
418
419 rdmsrl(BYT_TURBO_VIDS, value);
420 cpudata->vid.turbo = value & 0x7f;
007bea09
DB
421}
422
423
016c8150 424static int core_get_min_pstate(void)
93f0822d
DB
425{
426 u64 value;
05e99c8c 427 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
428 return (value >> 40) & 0xFF;
429}
430
016c8150 431static int core_get_max_pstate(void)
93f0822d
DB
432{
433 u64 value;
05e99c8c 434 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
435 return (value >> 8) & 0xFF;
436}
437
016c8150 438static int core_get_turbo_pstate(void)
93f0822d
DB
439{
440 u64 value;
441 int nont, ret;
05e99c8c 442 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
016c8150 443 nont = core_get_max_pstate();
93f0822d
DB
444 ret = ((value) & 255);
445 if (ret <= nont)
446 ret = nont;
447 return ret;
448}
449
007bea09 450static void core_set_pstate(struct cpudata *cpudata, int pstate)
016c8150
DB
451{
452 u64 val;
453
454 val = pstate << 8;
455 if (limits.no_turbo)
456 val |= (u64)1 << 32;
457
bb18008f 458 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
016c8150
DB
459}
460
461static struct cpu_defaults core_params = {
462 .pid_policy = {
463 .sample_rate_ms = 10,
464 .deadband = 0,
465 .setpoint = 97,
466 .p_gain_pct = 20,
467 .d_gain_pct = 0,
468 .i_gain_pct = 0,
469 },
470 .funcs = {
471 .get_max = core_get_max_pstate,
472 .get_min = core_get_min_pstate,
473 .get_turbo = core_get_turbo_pstate,
474 .set = core_set_pstate,
475 },
476};
477
19e77c28
DB
478static struct cpu_defaults byt_params = {
479 .pid_policy = {
480 .sample_rate_ms = 10,
481 .deadband = 0,
482 .setpoint = 97,
483 .p_gain_pct = 14,
484 .d_gain_pct = 0,
485 .i_gain_pct = 4,
486 },
487 .funcs = {
488 .get_max = byt_get_max_pstate,
489 .get_min = byt_get_min_pstate,
61d8d2ab 490 .get_turbo = byt_get_turbo_pstate,
007bea09
DB
491 .set = byt_set_pstate,
492 .get_vid = byt_get_vid,
19e77c28
DB
493 },
494};
495
496
93f0822d
DB
497static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
498{
499 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 500 int max_perf_adj;
93f0822d
DB
501 int min_perf;
502 if (limits.no_turbo)
503 max_perf = cpu->pstate.max_pstate;
504
7244cb62
DB
505 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
506 *max = clamp_t(int, max_perf_adj,
93f0822d
DB
507 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
508
509 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
510 *min = clamp_t(int, min_perf,
511 cpu->pstate.min_pstate, max_perf);
512}
513
514static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
515{
516 int max_perf, min_perf;
517
518 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
519
520 pstate = clamp_t(int, pstate, min_perf, max_perf);
521
522 if (pstate == cpu->pstate.current_pstate)
523 return;
524
93f0822d 525 trace_cpu_frequency(pstate * 100000, cpu->cpu);
35363e94 526
93f0822d 527 cpu->pstate.current_pstate = pstate;
93f0822d 528
007bea09 529 pstate_funcs.set(cpu, pstate);
93f0822d
DB
530}
531
532static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
533{
534 int target;
535 target = cpu->pstate.current_pstate + steps;
536
537 intel_pstate_set_pstate(cpu, target);
538}
539
540static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)
541{
542 int target;
543 target = cpu->pstate.current_pstate - steps;
544 intel_pstate_set_pstate(cpu, target);
545}
546
547static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
548{
549 sprintf(cpu->name, "Intel 2nd generation core");
550
016c8150
DB
551 cpu->pstate.min_pstate = pstate_funcs.get_min();
552 cpu->pstate.max_pstate = pstate_funcs.get_max();
553 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
93f0822d 554
007bea09
DB
555 if (pstate_funcs.get_vid)
556 pstate_funcs.get_vid(cpu);
d40a63c4 557 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
93f0822d
DB
558}
559
560static inline void intel_pstate_calc_busy(struct cpudata *cpu,
561 struct sample *sample)
562{
e66c1768
DB
563 int32_t core_pct;
564 int32_t c0_pct;
93f0822d 565
e66c1768
DB
566 core_pct = div_fp(int_tofp((sample->aperf)),
567 int_tofp((sample->mperf)));
568 core_pct = mul_fp(core_pct, int_tofp(100));
569 FP_ROUNDUP(core_pct);
570
571 c0_pct = div_fp(int_tofp(sample->mperf), int_tofp(sample->tsc));
fcb6a15c 572
fcb6a15c 573 sample->freq = fp_toint(
e66c1768 574 mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
fcb6a15c 575
e66c1768 576 sample->core_pct_busy = mul_fp(core_pct, c0_pct);
93f0822d
DB
577}
578
579static inline void intel_pstate_sample(struct cpudata *cpu)
580{
93f0822d 581 u64 aperf, mperf;
fcb6a15c 582 unsigned long long tsc;
93f0822d 583
93f0822d
DB
584 rdmsrl(MSR_IA32_APERF, aperf);
585 rdmsrl(MSR_IA32_MPERF, mperf);
fcb6a15c 586 tsc = native_read_tsc();
b69880f9 587
e66c1768
DB
588 aperf = aperf >> FRAC_BITS;
589 mperf = mperf >> FRAC_BITS;
590 tsc = tsc >> FRAC_BITS;
591
d37e2b76
DB
592 cpu->sample.aperf = aperf;
593 cpu->sample.mperf = mperf;
594 cpu->sample.tsc = tsc;
595 cpu->sample.aperf -= cpu->prev_aperf;
596 cpu->sample.mperf -= cpu->prev_mperf;
597 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 598
d37e2b76 599 intel_pstate_calc_busy(cpu, &cpu->sample);
93f0822d 600
93f0822d
DB
601 cpu->prev_aperf = aperf;
602 cpu->prev_mperf = mperf;
fcb6a15c 603 cpu->prev_tsc = tsc;
93f0822d
DB
604}
605
606static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
607{
608 int sample_time, delay;
609
016c8150 610 sample_time = pid_params.sample_rate_ms;
93f0822d 611 delay = msecs_to_jiffies(sample_time);
93f0822d
DB
612 mod_timer_pinned(&cpu->timer, jiffies + delay);
613}
614
d253d2a5 615static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
93f0822d 616{
2134ed4d 617 int32_t core_busy, max_pstate, current_pstate;
93f0822d 618
d37e2b76 619 core_busy = cpu->sample.core_pct_busy;
2134ed4d 620 max_pstate = int_tofp(cpu->pstate.max_pstate);
93f0822d 621 current_pstate = int_tofp(cpu->pstate.current_pstate);
e66c1768
DB
622 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
623 return FP_ROUNDUP(core_busy);
93f0822d
DB
624}
625
626static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
627{
d253d2a5 628 int32_t busy_scaled;
93f0822d
DB
629 struct _pid *pid;
630 signed int ctl = 0;
631 int steps;
632
633 pid = &cpu->pid;
634 busy_scaled = intel_pstate_get_scaled_busy(cpu);
635
636 ctl = pid_calc(pid, busy_scaled);
637
638 steps = abs(ctl);
b69880f9 639
93f0822d
DB
640 if (ctl < 0)
641 intel_pstate_pstate_increase(cpu, steps);
642 else
643 intel_pstate_pstate_decrease(cpu, steps);
644}
645
93f0822d
DB
646static void intel_pstate_timer_func(unsigned long __data)
647{
648 struct cpudata *cpu = (struct cpudata *) __data;
b69880f9 649 struct sample *sample;
93f0822d
DB
650
651 intel_pstate_sample(cpu);
b69880f9 652
d37e2b76 653 sample = &cpu->sample;
b69880f9 654
ca182aee 655 intel_pstate_adjust_busy_pstate(cpu);
b69880f9
DB
656
657 trace_pstate_sample(fp_toint(sample->core_pct_busy),
658 fp_toint(intel_pstate_get_scaled_busy(cpu)),
659 cpu->pstate.current_pstate,
660 sample->mperf,
661 sample->aperf,
b69880f9
DB
662 sample->freq);
663
93f0822d
DB
664 intel_pstate_set_sample_time(cpu);
665}
666
667#define ICPU(model, policy) \
6cbd7ee1
DB
668 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
669 (unsigned long)&policy }
93f0822d
DB
670
671static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
016c8150
DB
672 ICPU(0x2a, core_params),
673 ICPU(0x2d, core_params),
19e77c28 674 ICPU(0x37, byt_params),
016c8150
DB
675 ICPU(0x3a, core_params),
676 ICPU(0x3c, core_params),
677 ICPU(0x3e, core_params),
678 ICPU(0x3f, core_params),
679 ICPU(0x45, core_params),
680 ICPU(0x46, core_params),
93f0822d
DB
681 {}
682};
683MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
684
685static int intel_pstate_init_cpu(unsigned int cpunum)
686{
687
688 const struct x86_cpu_id *id;
689 struct cpudata *cpu;
690
691 id = x86_match_cpu(intel_pstate_cpu_ids);
692 if (!id)
693 return -ENODEV;
694
695 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
696 if (!all_cpu_data[cpunum])
697 return -ENOMEM;
698
699 cpu = all_cpu_data[cpunum];
700
701 intel_pstate_get_cpu_pstates(cpu);
702
703 cpu->cpu = cpunum;
016c8150 704
93f0822d
DB
705 init_timer_deferrable(&cpu->timer);
706 cpu->timer.function = intel_pstate_timer_func;
707 cpu->timer.data =
708 (unsigned long)cpu;
709 cpu->timer.expires = jiffies + HZ/100;
710 intel_pstate_busy_pid_reset(cpu);
93f0822d 711 intel_pstate_sample(cpu);
93f0822d
DB
712
713 add_timer_on(&cpu->timer, cpunum);
714
715 pr_info("Intel pstate controlling: cpu %d\n", cpunum);
716
717 return 0;
718}
719
720static unsigned int intel_pstate_get(unsigned int cpu_num)
721{
722 struct sample *sample;
723 struct cpudata *cpu;
724
725 cpu = all_cpu_data[cpu_num];
726 if (!cpu)
727 return 0;
d37e2b76 728 sample = &cpu->sample;
93f0822d
DB
729 return sample->freq;
730}
731
732static int intel_pstate_set_policy(struct cpufreq_policy *policy)
733{
734 struct cpudata *cpu;
93f0822d
DB
735
736 cpu = all_cpu_data[policy->cpu];
737
d3929b83
DB
738 if (!policy->cpuinfo.max_freq)
739 return -ENODEV;
740
93f0822d
DB
741 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
742 limits.min_perf_pct = 100;
743 limits.min_perf = int_tofp(1);
744 limits.max_perf_pct = 100;
745 limits.max_perf = int_tofp(1);
746 limits.no_turbo = 0;
d1b68485 747 return 0;
93f0822d 748 }
d1b68485
SP
749 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
750 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
751 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
752
d8f469e9
DB
753 limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;
754 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
755 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
d1b68485 756 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
93f0822d
DB
757
758 return 0;
759}
760
761static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
762{
be49e346 763 cpufreq_verify_within_cpu_limits(policy);
93f0822d
DB
764
765 if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
766 (policy->policy != CPUFREQ_POLICY_PERFORMANCE))
767 return -EINVAL;
768
769 return 0;
770}
771
bb18008f 772static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 773{
bb18008f
DB
774 int cpu_num = policy->cpu;
775 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 776
bb18008f
DB
777 pr_info("intel_pstate CPU %d exiting\n", cpu_num);
778
c2294a2f 779 del_timer_sync(&all_cpu_data[cpu_num]->timer);
bb18008f
DB
780 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
781 kfree(all_cpu_data[cpu_num]);
782 all_cpu_data[cpu_num] = NULL;
93f0822d
DB
783}
784
2760984f 785static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 786{
93f0822d 787 struct cpudata *cpu;
52e0a509 788 int rc;
93f0822d
DB
789
790 rc = intel_pstate_init_cpu(policy->cpu);
791 if (rc)
792 return rc;
793
794 cpu = all_cpu_data[policy->cpu];
795
796 if (!limits.no_turbo &&
797 limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
798 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
799 else
800 policy->policy = CPUFREQ_POLICY_POWERSAVE;
801
52e0a509
DB
802 policy->min = cpu->pstate.min_pstate * 100000;
803 policy->max = cpu->pstate.turbo_pstate * 100000;
93f0822d
DB
804
805 /* cpuinfo and default policy values */
806 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
807 policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
808 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
809 cpumask_set_cpu(policy->cpu, policy->cpus);
810
811 return 0;
812}
813
814static struct cpufreq_driver intel_pstate_driver = {
815 .flags = CPUFREQ_CONST_LOOPS,
816 .verify = intel_pstate_verify_policy,
817 .setpolicy = intel_pstate_set_policy,
818 .get = intel_pstate_get,
819 .init = intel_pstate_cpu_init,
bb18008f 820 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 821 .name = "intel_pstate",
93f0822d
DB
822};
823
6be26498
DB
824static int __initdata no_load;
825
b563b4e3
DB
826static int intel_pstate_msrs_not_valid(void)
827{
828 /* Check that all the msr's we are using are valid. */
829 u64 aperf, mperf, tmp;
830
831 rdmsrl(MSR_IA32_APERF, aperf);
832 rdmsrl(MSR_IA32_MPERF, mperf);
833
016c8150
DB
834 if (!pstate_funcs.get_max() ||
835 !pstate_funcs.get_min() ||
836 !pstate_funcs.get_turbo())
b563b4e3
DB
837 return -ENODEV;
838
839 rdmsrl(MSR_IA32_APERF, tmp);
840 if (!(tmp - aperf))
841 return -ENODEV;
842
843 rdmsrl(MSR_IA32_MPERF, tmp);
844 if (!(tmp - mperf))
845 return -ENODEV;
846
847 return 0;
848}
016c8150 849
e0a261a2 850static void copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB
851{
852 pid_params.sample_rate_ms = policy->sample_rate_ms;
853 pid_params.p_gain_pct = policy->p_gain_pct;
854 pid_params.i_gain_pct = policy->i_gain_pct;
855 pid_params.d_gain_pct = policy->d_gain_pct;
856 pid_params.deadband = policy->deadband;
857 pid_params.setpoint = policy->setpoint;
858}
859
e0a261a2 860static void copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB
861{
862 pstate_funcs.get_max = funcs->get_max;
863 pstate_funcs.get_min = funcs->get_min;
864 pstate_funcs.get_turbo = funcs->get_turbo;
865 pstate_funcs.set = funcs->set;
007bea09 866 pstate_funcs.get_vid = funcs->get_vid;
016c8150
DB
867}
868
fbbcdc07
AH
869#if IS_ENABLED(CONFIG_ACPI)
870#include <acpi/processor.h>
871
872static bool intel_pstate_no_acpi_pss(void)
873{
874 int i;
875
876 for_each_possible_cpu(i) {
877 acpi_status status;
878 union acpi_object *pss;
879 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
880 struct acpi_processor *pr = per_cpu(processors, i);
881
882 if (!pr)
883 continue;
884
885 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
886 if (ACPI_FAILURE(status))
887 continue;
888
889 pss = buffer.pointer;
890 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
891 kfree(pss);
892 return false;
893 }
894
895 kfree(pss);
896 }
897
898 return true;
899}
900
901struct hw_vendor_info {
902 u16 valid;
903 char oem_id[ACPI_OEM_ID_SIZE];
904 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
905};
906
907/* Hardware vendor-specific info that has its own power management modes */
908static struct hw_vendor_info vendor_info[] = {
909 {1, "HP ", "ProLiant"},
910 {0, "", ""},
911};
912
913static bool intel_pstate_platform_pwr_mgmt_exists(void)
914{
915 struct acpi_table_header hdr;
916 struct hw_vendor_info *v_info;
917
918 if (acpi_disabled
919 || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
920 return false;
921
922 for (v_info = vendor_info; v_info->valid; v_info++) {
923 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)
924 && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)
925 && intel_pstate_no_acpi_pss())
926 return true;
927 }
928
929 return false;
930}
931#else /* CONFIG_ACPI not enabled */
932static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
933#endif /* CONFIG_ACPI */
934
93f0822d
DB
935static int __init intel_pstate_init(void)
936{
907cc908 937 int cpu, rc = 0;
93f0822d 938 const struct x86_cpu_id *id;
016c8150 939 struct cpu_defaults *cpu_info;
93f0822d 940
6be26498
DB
941 if (no_load)
942 return -ENODEV;
943
93f0822d
DB
944 id = x86_match_cpu(intel_pstate_cpu_ids);
945 if (!id)
946 return -ENODEV;
947
fbbcdc07
AH
948 /*
949 * The Intel pstate driver will be ignored if the platform
950 * firmware has its own power management modes.
951 */
952 if (intel_pstate_platform_pwr_mgmt_exists())
953 return -ENODEV;
954
016c8150
DB
955 cpu_info = (struct cpu_defaults *)id->driver_data;
956
957 copy_pid_params(&cpu_info->pid_policy);
958 copy_cpu_funcs(&cpu_info->funcs);
959
b563b4e3
DB
960 if (intel_pstate_msrs_not_valid())
961 return -ENODEV;
962
93f0822d
DB
963 pr_info("Intel P-state driver initializing.\n");
964
b57ffac5 965 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB
966 if (!all_cpu_data)
967 return -ENOMEM;
93f0822d
DB
968
969 rc = cpufreq_register_driver(&intel_pstate_driver);
970 if (rc)
971 goto out;
972
973 intel_pstate_debug_expose_params();
974 intel_pstate_sysfs_expose_params();
b69880f9 975
93f0822d
DB
976 return rc;
977out:
907cc908
DB
978 get_online_cpus();
979 for_each_online_cpu(cpu) {
980 if (all_cpu_data[cpu]) {
981 del_timer_sync(&all_cpu_data[cpu]->timer);
982 kfree(all_cpu_data[cpu]);
983 }
984 }
985
986 put_online_cpus();
987 vfree(all_cpu_data);
93f0822d
DB
988 return -ENODEV;
989}
990device_initcall(intel_pstate_init);
991
6be26498
DB
992static int __init intel_pstate_setup(char *str)
993{
994 if (!str)
995 return -EINVAL;
996
997 if (!strcmp(str, "disable"))
998 no_load = 1;
999 return 0;
1000}
1001early_param("intel_pstate", intel_pstate_setup);
1002
93f0822d
DB
1003MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1004MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1005MODULE_LICENSE("GPL");