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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
d6472302 | 29 | #include <linux/vmalloc.h> |
93f0822d DB |
30 | #include <trace/events/power.h> |
31 | ||
32 | #include <asm/div64.h> | |
33 | #include <asm/msr.h> | |
34 | #include <asm/cpu_device_id.h> | |
64df1fdf | 35 | #include <asm/cpufeature.h> |
93f0822d | 36 | |
938d21a2 PL |
37 | #define ATOM_RATIOS 0x66a |
38 | #define ATOM_VIDS 0x66b | |
39 | #define ATOM_TURBO_RATIOS 0x66c | |
40 | #define ATOM_TURBO_VIDS 0x66d | |
61d8d2ab | 41 | |
f0fe3cd7 | 42 | #define FRAC_BITS 8 |
93f0822d DB |
43 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
44 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 45 | |
93f0822d DB |
46 | static inline int32_t mul_fp(int32_t x, int32_t y) |
47 | { | |
48 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
49 | } | |
50 | ||
7180dddf | 51 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 52 | { |
7180dddf | 53 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
54 | } |
55 | ||
d022a65e DB |
56 | static inline int ceiling_fp(int32_t x) |
57 | { | |
58 | int mask, ret; | |
59 | ||
60 | ret = fp_toint(x); | |
61 | mask = (1 << FRAC_BITS) - 1; | |
62 | if (x & mask) | |
63 | ret += 1; | |
64 | return ret; | |
65 | } | |
66 | ||
93f0822d | 67 | struct sample { |
d253d2a5 | 68 | int32_t core_pct_busy; |
157386b6 | 69 | int32_t busy_scaled; |
93f0822d DB |
70 | u64 aperf; |
71 | u64 mperf; | |
4055fad3 | 72 | u64 tsc; |
93f0822d | 73 | int freq; |
c4ee841f | 74 | ktime_t time; |
93f0822d DB |
75 | }; |
76 | ||
77 | struct pstate_data { | |
78 | int current_pstate; | |
79 | int min_pstate; | |
80 | int max_pstate; | |
3bcc6fa9 | 81 | int max_pstate_physical; |
b27580b0 | 82 | int scaling; |
93f0822d DB |
83 | int turbo_pstate; |
84 | }; | |
85 | ||
007bea09 | 86 | struct vid_data { |
21855ff5 DB |
87 | int min; |
88 | int max; | |
89 | int turbo; | |
007bea09 DB |
90 | int32_t ratio; |
91 | }; | |
92 | ||
93f0822d DB |
93 | struct _pid { |
94 | int setpoint; | |
95 | int32_t integral; | |
96 | int32_t p_gain; | |
97 | int32_t i_gain; | |
98 | int32_t d_gain; | |
99 | int deadband; | |
d253d2a5 | 100 | int32_t last_err; |
93f0822d DB |
101 | }; |
102 | ||
103 | struct cpudata { | |
104 | int cpu; | |
105 | ||
93f0822d DB |
106 | struct timer_list timer; |
107 | ||
93f0822d | 108 | struct pstate_data pstate; |
007bea09 | 109 | struct vid_data vid; |
93f0822d | 110 | struct _pid pid; |
93f0822d | 111 | |
c4ee841f | 112 | ktime_t last_sample_time; |
93f0822d DB |
113 | u64 prev_aperf; |
114 | u64 prev_mperf; | |
4055fad3 | 115 | u64 prev_tsc; |
d37e2b76 | 116 | struct sample sample; |
93f0822d DB |
117 | }; |
118 | ||
119 | static struct cpudata **all_cpu_data; | |
120 | struct pstate_adjust_policy { | |
121 | int sample_rate_ms; | |
122 | int deadband; | |
123 | int setpoint; | |
124 | int p_gain_pct; | |
125 | int d_gain_pct; | |
126 | int i_gain_pct; | |
127 | }; | |
128 | ||
016c8150 DB |
129 | struct pstate_funcs { |
130 | int (*get_max)(void); | |
3bcc6fa9 | 131 | int (*get_max_physical)(void); |
016c8150 DB |
132 | int (*get_min)(void); |
133 | int (*get_turbo)(void); | |
b27580b0 | 134 | int (*get_scaling)(void); |
007bea09 DB |
135 | void (*set)(struct cpudata*, int pstate); |
136 | void (*get_vid)(struct cpudata *); | |
157386b6 | 137 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
138 | }; |
139 | ||
016c8150 DB |
140 | struct cpu_defaults { |
141 | struct pstate_adjust_policy pid_policy; | |
142 | struct pstate_funcs funcs; | |
93f0822d DB |
143 | }; |
144 | ||
157386b6 PL |
145 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
146 | ||
016c8150 DB |
147 | static struct pstate_adjust_policy pid_params; |
148 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 149 | static int hwp_active; |
016c8150 | 150 | |
93f0822d DB |
151 | struct perf_limits { |
152 | int no_turbo; | |
dd5fbf70 | 153 | int turbo_disabled; |
93f0822d DB |
154 | int max_perf_pct; |
155 | int min_perf_pct; | |
156 | int32_t max_perf; | |
157 | int32_t min_perf; | |
d8f469e9 DB |
158 | int max_policy_pct; |
159 | int max_sysfs_pct; | |
a0475992 KCA |
160 | int min_policy_pct; |
161 | int min_sysfs_pct; | |
93f0822d DB |
162 | }; |
163 | ||
51443fbf PB |
164 | static struct perf_limits performance_limits = { |
165 | .no_turbo = 0, | |
166 | .turbo_disabled = 0, | |
167 | .max_perf_pct = 100, | |
168 | .max_perf = int_tofp(1), | |
169 | .min_perf_pct = 100, | |
170 | .min_perf = int_tofp(1), | |
171 | .max_policy_pct = 100, | |
172 | .max_sysfs_pct = 100, | |
173 | .min_policy_pct = 0, | |
174 | .min_sysfs_pct = 0, | |
175 | }; | |
176 | ||
177 | static struct perf_limits powersave_limits = { | |
93f0822d | 178 | .no_turbo = 0, |
4521e1a0 | 179 | .turbo_disabled = 0, |
93f0822d DB |
180 | .max_perf_pct = 100, |
181 | .max_perf = int_tofp(1), | |
182 | .min_perf_pct = 0, | |
183 | .min_perf = 0, | |
d8f469e9 DB |
184 | .max_policy_pct = 100, |
185 | .max_sysfs_pct = 100, | |
a0475992 KCA |
186 | .min_policy_pct = 0, |
187 | .min_sysfs_pct = 0, | |
93f0822d DB |
188 | }; |
189 | ||
51443fbf PB |
190 | #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE |
191 | static struct perf_limits *limits = &performance_limits; | |
192 | #else | |
193 | static struct perf_limits *limits = &powersave_limits; | |
194 | #endif | |
195 | ||
93f0822d | 196 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 197 | int deadband, int integral) { |
93f0822d DB |
198 | pid->setpoint = setpoint; |
199 | pid->deadband = deadband; | |
200 | pid->integral = int_tofp(integral); | |
d98d099b | 201 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
202 | } |
203 | ||
204 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
205 | { | |
206 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
207 | } | |
208 | ||
209 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
210 | { | |
211 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
212 | } | |
213 | ||
214 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
215 | { | |
93f0822d DB |
216 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
217 | } | |
218 | ||
d253d2a5 | 219 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 220 | { |
d253d2a5 | 221 | signed int result; |
93f0822d DB |
222 | int32_t pterm, dterm, fp_error; |
223 | int32_t integral_limit; | |
224 | ||
d253d2a5 | 225 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 226 | |
d253d2a5 | 227 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
228 | return 0; |
229 | ||
230 | pterm = mul_fp(pid->p_gain, fp_error); | |
231 | ||
232 | pid->integral += fp_error; | |
233 | ||
e0d4c8f8 KCA |
234 | /* |
235 | * We limit the integral here so that it will never | |
236 | * get higher than 30. This prevents it from becoming | |
237 | * too large an input over long periods of time and allows | |
238 | * it to get factored out sooner. | |
239 | * | |
240 | * The value of 30 was chosen through experimentation. | |
241 | */ | |
93f0822d DB |
242 | integral_limit = int_tofp(30); |
243 | if (pid->integral > integral_limit) | |
244 | pid->integral = integral_limit; | |
245 | if (pid->integral < -integral_limit) | |
246 | pid->integral = -integral_limit; | |
247 | ||
d253d2a5 BS |
248 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
249 | pid->last_err = fp_error; | |
93f0822d DB |
250 | |
251 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 252 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
253 | return (signed int)fp_toint(result); |
254 | } | |
255 | ||
256 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
257 | { | |
016c8150 DB |
258 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
259 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
260 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 261 | |
2d8d1f18 | 262 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
263 | } |
264 | ||
93f0822d DB |
265 | static inline void intel_pstate_reset_all_pid(void) |
266 | { | |
267 | unsigned int cpu; | |
845c1cbe | 268 | |
93f0822d DB |
269 | for_each_online_cpu(cpu) { |
270 | if (all_cpu_data[cpu]) | |
271 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
272 | } | |
273 | } | |
274 | ||
4521e1a0 GM |
275 | static inline void update_turbo_state(void) |
276 | { | |
277 | u64 misc_en; | |
278 | struct cpudata *cpu; | |
279 | ||
280 | cpu = all_cpu_data[0]; | |
281 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
51443fbf | 282 | limits->turbo_disabled = |
4521e1a0 GM |
283 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
284 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
285 | } | |
286 | ||
2f86dc4c DB |
287 | static void intel_pstate_hwp_set(void) |
288 | { | |
74da56ce KCA |
289 | int min, hw_min, max, hw_max, cpu, range, adj_range; |
290 | u64 value, cap; | |
291 | ||
292 | rdmsrl(MSR_HWP_CAPABILITIES, cap); | |
293 | hw_min = HWP_LOWEST_PERF(cap); | |
294 | hw_max = HWP_HIGHEST_PERF(cap); | |
295 | range = hw_max - hw_min; | |
2f86dc4c DB |
296 | |
297 | get_online_cpus(); | |
298 | ||
299 | for_each_online_cpu(cpu) { | |
300 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
51443fbf | 301 | adj_range = limits->min_perf_pct * range / 100; |
74da56ce | 302 | min = hw_min + adj_range; |
2f86dc4c DB |
303 | value &= ~HWP_MIN_PERF(~0L); |
304 | value |= HWP_MIN_PERF(min); | |
305 | ||
51443fbf | 306 | adj_range = limits->max_perf_pct * range / 100; |
74da56ce | 307 | max = hw_min + adj_range; |
51443fbf | 308 | if (limits->no_turbo) { |
74da56ce KCA |
309 | hw_max = HWP_GUARANTEED_PERF(cap); |
310 | if (hw_max < max) | |
311 | max = hw_max; | |
2f86dc4c DB |
312 | } |
313 | ||
314 | value &= ~HWP_MAX_PERF(~0L); | |
315 | value |= HWP_MAX_PERF(max); | |
316 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
317 | } | |
318 | ||
319 | put_online_cpus(); | |
320 | } | |
321 | ||
93f0822d DB |
322 | /************************** debugfs begin ************************/ |
323 | static int pid_param_set(void *data, u64 val) | |
324 | { | |
325 | *(u32 *)data = val; | |
326 | intel_pstate_reset_all_pid(); | |
327 | return 0; | |
328 | } | |
845c1cbe | 329 | |
93f0822d DB |
330 | static int pid_param_get(void *data, u64 *val) |
331 | { | |
332 | *val = *(u32 *)data; | |
333 | return 0; | |
334 | } | |
2d8d1f18 | 335 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
336 | |
337 | struct pid_param { | |
338 | char *name; | |
339 | void *value; | |
340 | }; | |
341 | ||
342 | static struct pid_param pid_files[] = { | |
016c8150 DB |
343 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
344 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
345 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
346 | {"deadband", &pid_params.deadband}, | |
347 | {"setpoint", &pid_params.setpoint}, | |
348 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
349 | {NULL, NULL} |
350 | }; | |
351 | ||
317dd50e | 352 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 353 | { |
317dd50e | 354 | struct dentry *debugfs_parent; |
93f0822d DB |
355 | int i = 0; |
356 | ||
2f86dc4c DB |
357 | if (hwp_active) |
358 | return; | |
93f0822d DB |
359 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
360 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
361 | return; | |
362 | while (pid_files[i].name) { | |
363 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
364 | debugfs_parent, pid_files[i].value, |
365 | &fops_pid_param); | |
93f0822d DB |
366 | i++; |
367 | } | |
368 | } | |
369 | ||
370 | /************************** debugfs end ************************/ | |
371 | ||
372 | /************************** sysfs begin ************************/ | |
373 | #define show_one(file_name, object) \ | |
374 | static ssize_t show_##file_name \ | |
375 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
376 | { \ | |
51443fbf | 377 | return sprintf(buf, "%u\n", limits->object); \ |
93f0822d DB |
378 | } |
379 | ||
d01b1f48 KCA |
380 | static ssize_t show_turbo_pct(struct kobject *kobj, |
381 | struct attribute *attr, char *buf) | |
382 | { | |
383 | struct cpudata *cpu; | |
384 | int total, no_turbo, turbo_pct; | |
385 | uint32_t turbo_fp; | |
386 | ||
387 | cpu = all_cpu_data[0]; | |
388 | ||
389 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
390 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
391 | turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); | |
392 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); | |
393 | return sprintf(buf, "%u\n", turbo_pct); | |
394 | } | |
395 | ||
0522424e KCA |
396 | static ssize_t show_num_pstates(struct kobject *kobj, |
397 | struct attribute *attr, char *buf) | |
398 | { | |
399 | struct cpudata *cpu; | |
400 | int total; | |
401 | ||
402 | cpu = all_cpu_data[0]; | |
403 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
404 | return sprintf(buf, "%u\n", total); | |
405 | } | |
406 | ||
4521e1a0 GM |
407 | static ssize_t show_no_turbo(struct kobject *kobj, |
408 | struct attribute *attr, char *buf) | |
409 | { | |
410 | ssize_t ret; | |
411 | ||
412 | update_turbo_state(); | |
51443fbf PB |
413 | if (limits->turbo_disabled) |
414 | ret = sprintf(buf, "%u\n", limits->turbo_disabled); | |
4521e1a0 | 415 | else |
51443fbf | 416 | ret = sprintf(buf, "%u\n", limits->no_turbo); |
4521e1a0 GM |
417 | |
418 | return ret; | |
419 | } | |
420 | ||
93f0822d | 421 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 422 | const char *buf, size_t count) |
93f0822d DB |
423 | { |
424 | unsigned int input; | |
425 | int ret; | |
845c1cbe | 426 | |
93f0822d DB |
427 | ret = sscanf(buf, "%u", &input); |
428 | if (ret != 1) | |
429 | return -EINVAL; | |
4521e1a0 GM |
430 | |
431 | update_turbo_state(); | |
51443fbf | 432 | if (limits->turbo_disabled) { |
f16255eb | 433 | pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n"); |
4521e1a0 | 434 | return -EPERM; |
dd5fbf70 | 435 | } |
2f86dc4c | 436 | |
51443fbf | 437 | limits->no_turbo = clamp_t(int, input, 0, 1); |
4521e1a0 | 438 | |
2f86dc4c DB |
439 | if (hwp_active) |
440 | intel_pstate_hwp_set(); | |
441 | ||
93f0822d DB |
442 | return count; |
443 | } | |
444 | ||
445 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 446 | const char *buf, size_t count) |
93f0822d DB |
447 | { |
448 | unsigned int input; | |
449 | int ret; | |
845c1cbe | 450 | |
93f0822d DB |
451 | ret = sscanf(buf, "%u", &input); |
452 | if (ret != 1) | |
453 | return -EINVAL; | |
454 | ||
51443fbf PB |
455 | limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); |
456 | limits->max_perf_pct = min(limits->max_policy_pct, | |
457 | limits->max_sysfs_pct); | |
458 | limits->max_perf_pct = max(limits->min_policy_pct, | |
459 | limits->max_perf_pct); | |
460 | limits->max_perf_pct = max(limits->min_perf_pct, | |
461 | limits->max_perf_pct); | |
462 | limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), | |
463 | int_tofp(100)); | |
845c1cbe | 464 | |
2f86dc4c DB |
465 | if (hwp_active) |
466 | intel_pstate_hwp_set(); | |
93f0822d DB |
467 | return count; |
468 | } | |
469 | ||
470 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 471 | const char *buf, size_t count) |
93f0822d DB |
472 | { |
473 | unsigned int input; | |
474 | int ret; | |
845c1cbe | 475 | |
93f0822d DB |
476 | ret = sscanf(buf, "%u", &input); |
477 | if (ret != 1) | |
478 | return -EINVAL; | |
a0475992 | 479 | |
51443fbf PB |
480 | limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); |
481 | limits->min_perf_pct = max(limits->min_policy_pct, | |
482 | limits->min_sysfs_pct); | |
483 | limits->min_perf_pct = min(limits->max_policy_pct, | |
484 | limits->min_perf_pct); | |
485 | limits->min_perf_pct = min(limits->max_perf_pct, | |
486 | limits->min_perf_pct); | |
487 | limits->min_perf = div_fp(int_tofp(limits->min_perf_pct), | |
488 | int_tofp(100)); | |
93f0822d | 489 | |
2f86dc4c DB |
490 | if (hwp_active) |
491 | intel_pstate_hwp_set(); | |
93f0822d DB |
492 | return count; |
493 | } | |
494 | ||
93f0822d DB |
495 | show_one(max_perf_pct, max_perf_pct); |
496 | show_one(min_perf_pct, min_perf_pct); | |
497 | ||
498 | define_one_global_rw(no_turbo); | |
499 | define_one_global_rw(max_perf_pct); | |
500 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 501 | define_one_global_ro(turbo_pct); |
0522424e | 502 | define_one_global_ro(num_pstates); |
93f0822d DB |
503 | |
504 | static struct attribute *intel_pstate_attributes[] = { | |
505 | &no_turbo.attr, | |
506 | &max_perf_pct.attr, | |
507 | &min_perf_pct.attr, | |
d01b1f48 | 508 | &turbo_pct.attr, |
0522424e | 509 | &num_pstates.attr, |
93f0822d DB |
510 | NULL |
511 | }; | |
512 | ||
513 | static struct attribute_group intel_pstate_attr_group = { | |
514 | .attrs = intel_pstate_attributes, | |
515 | }; | |
93f0822d | 516 | |
317dd50e | 517 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 518 | { |
317dd50e | 519 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
520 | int rc; |
521 | ||
522 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
523 | &cpu_subsys.dev_root->kobj); | |
524 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 525 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
526 | BUG_ON(rc); |
527 | } | |
93f0822d | 528 | /************************** sysfs end ************************/ |
2f86dc4c | 529 | |
ba88d433 | 530 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 531 | { |
ba88d433 | 532 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
533 | } |
534 | ||
938d21a2 | 535 | static int atom_get_min_pstate(void) |
19e77c28 DB |
536 | { |
537 | u64 value; | |
845c1cbe | 538 | |
938d21a2 | 539 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 540 | return (value >> 8) & 0x7F; |
19e77c28 DB |
541 | } |
542 | ||
938d21a2 | 543 | static int atom_get_max_pstate(void) |
19e77c28 DB |
544 | { |
545 | u64 value; | |
845c1cbe | 546 | |
938d21a2 | 547 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 548 | return (value >> 16) & 0x7F; |
19e77c28 | 549 | } |
93f0822d | 550 | |
938d21a2 | 551 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
552 | { |
553 | u64 value; | |
845c1cbe | 554 | |
938d21a2 | 555 | rdmsrl(ATOM_TURBO_RATIOS, value); |
c16ed060 | 556 | return value & 0x7F; |
61d8d2ab DB |
557 | } |
558 | ||
938d21a2 | 559 | static void atom_set_pstate(struct cpudata *cpudata, int pstate) |
007bea09 DB |
560 | { |
561 | u64 val; | |
562 | int32_t vid_fp; | |
563 | u32 vid; | |
564 | ||
144c8e17 | 565 | val = (u64)pstate << 8; |
51443fbf | 566 | if (limits->no_turbo && !limits->turbo_disabled) |
007bea09 DB |
567 | val |= (u64)1 << 32; |
568 | ||
569 | vid_fp = cpudata->vid.min + mul_fp( | |
570 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
571 | cpudata->vid.ratio); | |
572 | ||
573 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 574 | vid = ceiling_fp(vid_fp); |
007bea09 | 575 | |
21855ff5 DB |
576 | if (pstate > cpudata->pstate.max_pstate) |
577 | vid = cpudata->vid.turbo; | |
578 | ||
007bea09 DB |
579 | val |= vid; |
580 | ||
0dd23f94 | 581 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
007bea09 DB |
582 | } |
583 | ||
1421df63 | 584 | static int silvermont_get_scaling(void) |
b27580b0 DB |
585 | { |
586 | u64 value; | |
587 | int i; | |
1421df63 PL |
588 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
589 | static int silvermont_freq_table[] = { | |
590 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
591 | |
592 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
593 | i = value & 0x7; |
594 | WARN_ON(i > 4); | |
b27580b0 | 595 | |
1421df63 PL |
596 | return silvermont_freq_table[i]; |
597 | } | |
b27580b0 | 598 | |
1421df63 PL |
599 | static int airmont_get_scaling(void) |
600 | { | |
601 | u64 value; | |
602 | int i; | |
603 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
604 | static int airmont_freq_table[] = { | |
605 | 83300, 100000, 133300, 116700, 80000, | |
606 | 93300, 90000, 88900, 87500}; | |
607 | ||
608 | rdmsrl(MSR_FSB_FREQ, value); | |
609 | i = value & 0xF; | |
610 | WARN_ON(i > 8); | |
611 | ||
612 | return airmont_freq_table[i]; | |
b27580b0 DB |
613 | } |
614 | ||
938d21a2 | 615 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
616 | { |
617 | u64 value; | |
618 | ||
938d21a2 | 619 | rdmsrl(ATOM_VIDS, value); |
c16ed060 DB |
620 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
621 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
622 | cpudata->vid.ratio = div_fp( |
623 | cpudata->vid.max - cpudata->vid.min, | |
624 | int_tofp(cpudata->pstate.max_pstate - | |
625 | cpudata->pstate.min_pstate)); | |
21855ff5 | 626 | |
938d21a2 | 627 | rdmsrl(ATOM_TURBO_VIDS, value); |
21855ff5 | 628 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
629 | } |
630 | ||
016c8150 | 631 | static int core_get_min_pstate(void) |
93f0822d DB |
632 | { |
633 | u64 value; | |
845c1cbe | 634 | |
05e99c8c | 635 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
636 | return (value >> 40) & 0xFF; |
637 | } | |
638 | ||
3bcc6fa9 | 639 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
640 | { |
641 | u64 value; | |
845c1cbe | 642 | |
05e99c8c | 643 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
644 | return (value >> 8) & 0xFF; |
645 | } | |
646 | ||
016c8150 | 647 | static int core_get_max_pstate(void) |
93f0822d | 648 | { |
6a35fc2d SP |
649 | u64 tar; |
650 | u64 plat_info; | |
651 | int max_pstate; | |
652 | int err; | |
653 | ||
654 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
655 | max_pstate = (plat_info >> 8) & 0xFF; | |
656 | ||
657 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); | |
658 | if (!err) { | |
659 | /* Do some sanity checking for safety */ | |
660 | if (plat_info & 0x600000000) { | |
661 | u64 tdp_ctrl; | |
662 | u64 tdp_ratio; | |
663 | int tdp_msr; | |
664 | ||
665 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
666 | if (err) | |
667 | goto skip_tar; | |
668 | ||
669 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; | |
670 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
671 | if (err) | |
672 | goto skip_tar; | |
673 | ||
674 | if (tdp_ratio - 1 == tar) { | |
675 | max_pstate = tar; | |
676 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
677 | } else { | |
678 | goto skip_tar; | |
679 | } | |
680 | } | |
681 | } | |
845c1cbe | 682 | |
6a35fc2d SP |
683 | skip_tar: |
684 | return max_pstate; | |
93f0822d DB |
685 | } |
686 | ||
016c8150 | 687 | static int core_get_turbo_pstate(void) |
93f0822d DB |
688 | { |
689 | u64 value; | |
690 | int nont, ret; | |
845c1cbe | 691 | |
05e99c8c | 692 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 693 | nont = core_get_max_pstate(); |
285cb990 | 694 | ret = (value) & 255; |
93f0822d DB |
695 | if (ret <= nont) |
696 | ret = nont; | |
697 | return ret; | |
698 | } | |
699 | ||
b27580b0 DB |
700 | static inline int core_get_scaling(void) |
701 | { | |
702 | return 100000; | |
703 | } | |
704 | ||
007bea09 | 705 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
706 | { |
707 | u64 val; | |
708 | ||
144c8e17 | 709 | val = (u64)pstate << 8; |
51443fbf | 710 | if (limits->no_turbo && !limits->turbo_disabled) |
016c8150 DB |
711 | val |= (u64)1 << 32; |
712 | ||
bb18008f | 713 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
714 | } |
715 | ||
b34ef932 DC |
716 | static int knl_get_turbo_pstate(void) |
717 | { | |
718 | u64 value; | |
719 | int nont, ret; | |
720 | ||
721 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); | |
722 | nont = core_get_max_pstate(); | |
723 | ret = (((value) >> 8) & 0xFF); | |
724 | if (ret <= nont) | |
725 | ret = nont; | |
726 | return ret; | |
727 | } | |
728 | ||
016c8150 DB |
729 | static struct cpu_defaults core_params = { |
730 | .pid_policy = { | |
731 | .sample_rate_ms = 10, | |
732 | .deadband = 0, | |
733 | .setpoint = 97, | |
734 | .p_gain_pct = 20, | |
735 | .d_gain_pct = 0, | |
736 | .i_gain_pct = 0, | |
737 | }, | |
738 | .funcs = { | |
739 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 740 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
741 | .get_min = core_get_min_pstate, |
742 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 743 | .get_scaling = core_get_scaling, |
016c8150 | 744 | .set = core_set_pstate, |
157386b6 | 745 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
746 | }, |
747 | }; | |
748 | ||
1421df63 PL |
749 | static struct cpu_defaults silvermont_params = { |
750 | .pid_policy = { | |
751 | .sample_rate_ms = 10, | |
752 | .deadband = 0, | |
753 | .setpoint = 60, | |
754 | .p_gain_pct = 14, | |
755 | .d_gain_pct = 0, | |
756 | .i_gain_pct = 4, | |
757 | }, | |
758 | .funcs = { | |
759 | .get_max = atom_get_max_pstate, | |
760 | .get_max_physical = atom_get_max_pstate, | |
761 | .get_min = atom_get_min_pstate, | |
762 | .get_turbo = atom_get_turbo_pstate, | |
763 | .set = atom_set_pstate, | |
764 | .get_scaling = silvermont_get_scaling, | |
765 | .get_vid = atom_get_vid, | |
157386b6 | 766 | .get_target_pstate = get_target_pstate_use_performance, |
1421df63 PL |
767 | }, |
768 | }; | |
769 | ||
770 | static struct cpu_defaults airmont_params = { | |
19e77c28 DB |
771 | .pid_policy = { |
772 | .sample_rate_ms = 10, | |
773 | .deadband = 0, | |
6a82ba6d | 774 | .setpoint = 60, |
19e77c28 DB |
775 | .p_gain_pct = 14, |
776 | .d_gain_pct = 0, | |
777 | .i_gain_pct = 4, | |
778 | }, | |
779 | .funcs = { | |
938d21a2 PL |
780 | .get_max = atom_get_max_pstate, |
781 | .get_max_physical = atom_get_max_pstate, | |
782 | .get_min = atom_get_min_pstate, | |
783 | .get_turbo = atom_get_turbo_pstate, | |
784 | .set = atom_set_pstate, | |
1421df63 | 785 | .get_scaling = airmont_get_scaling, |
938d21a2 | 786 | .get_vid = atom_get_vid, |
157386b6 | 787 | .get_target_pstate = get_target_pstate_use_performance, |
19e77c28 DB |
788 | }, |
789 | }; | |
790 | ||
b34ef932 DC |
791 | static struct cpu_defaults knl_params = { |
792 | .pid_policy = { | |
793 | .sample_rate_ms = 10, | |
794 | .deadband = 0, | |
795 | .setpoint = 97, | |
796 | .p_gain_pct = 20, | |
797 | .d_gain_pct = 0, | |
798 | .i_gain_pct = 0, | |
799 | }, | |
800 | .funcs = { | |
801 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 802 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
803 | .get_min = core_get_min_pstate, |
804 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 805 | .get_scaling = core_get_scaling, |
b34ef932 | 806 | .set = core_set_pstate, |
157386b6 | 807 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
808 | }, |
809 | }; | |
810 | ||
93f0822d DB |
811 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
812 | { | |
813 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 814 | int max_perf_adj; |
93f0822d | 815 | int min_perf; |
845c1cbe | 816 | |
51443fbf | 817 | if (limits->no_turbo || limits->turbo_disabled) |
93f0822d DB |
818 | max_perf = cpu->pstate.max_pstate; |
819 | ||
e0d4c8f8 KCA |
820 | /* |
821 | * performance can be limited by user through sysfs, by cpufreq | |
822 | * policy, or by cpu specific default values determined through | |
823 | * experimentation. | |
824 | */ | |
799281a3 RW |
825 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits->max_perf)); |
826 | *max = clamp_t(int, max_perf_adj, | |
827 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 828 | |
799281a3 RW |
829 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits->min_perf)); |
830 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); | |
93f0822d DB |
831 | } |
832 | ||
6c1e4591 | 833 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate, bool force) |
93f0822d DB |
834 | { |
835 | int max_perf, min_perf; | |
836 | ||
6c1e4591 DS |
837 | if (force) { |
838 | update_turbo_state(); | |
93f0822d | 839 | |
6c1e4591 | 840 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
93f0822d | 841 | |
6c1e4591 | 842 | pstate = clamp_t(int, pstate, min_perf, max_perf); |
93f0822d | 843 | |
6c1e4591 DS |
844 | if (pstate == cpu->pstate.current_pstate) |
845 | return; | |
846 | } | |
b27580b0 | 847 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 848 | |
93f0822d | 849 | cpu->pstate.current_pstate = pstate; |
93f0822d | 850 | |
007bea09 | 851 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
852 | } |
853 | ||
93f0822d DB |
854 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
855 | { | |
016c8150 DB |
856 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
857 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 858 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 859 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 860 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 861 | |
007bea09 DB |
862 | if (pstate_funcs.get_vid) |
863 | pstate_funcs.get_vid(cpu); | |
6c1e4591 | 864 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
865 | } |
866 | ||
6b17ddb2 | 867 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 868 | { |
6b17ddb2 | 869 | struct sample *sample = &cpu->sample; |
bf810222 | 870 | int64_t core_pct; |
93f0822d | 871 | |
bf810222 | 872 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 873 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 874 | |
fcb6a15c | 875 | sample->freq = fp_toint( |
b27580b0 | 876 | mul_fp(int_tofp( |
3bcc6fa9 SP |
877 | cpu->pstate.max_pstate_physical * |
878 | cpu->pstate.scaling / 100), | |
b27580b0 | 879 | core_pct)); |
fcb6a15c | 880 | |
bf810222 | 881 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
882 | } |
883 | ||
884 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
885 | { | |
93f0822d | 886 | u64 aperf, mperf; |
4ab60c3f | 887 | unsigned long flags; |
4055fad3 | 888 | u64 tsc; |
93f0822d | 889 | |
4ab60c3f | 890 | local_irq_save(flags); |
93f0822d DB |
891 | rdmsrl(MSR_IA32_APERF, aperf); |
892 | rdmsrl(MSR_IA32_MPERF, mperf); | |
8e601a9f SP |
893 | if (cpu->prev_mperf == mperf) { |
894 | local_irq_restore(flags); | |
895 | return; | |
896 | } | |
897 | ||
4ea1636b | 898 | tsc = rdtsc(); |
4ab60c3f | 899 | local_irq_restore(flags); |
b69880f9 | 900 | |
c4ee841f DB |
901 | cpu->last_sample_time = cpu->sample.time; |
902 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
903 | cpu->sample.aperf = aperf; |
904 | cpu->sample.mperf = mperf; | |
4055fad3 | 905 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
906 | cpu->sample.aperf -= cpu->prev_aperf; |
907 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 908 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 909 | |
6b17ddb2 | 910 | intel_pstate_calc_busy(cpu); |
93f0822d | 911 | |
93f0822d DB |
912 | cpu->prev_aperf = aperf; |
913 | cpu->prev_mperf = mperf; | |
4055fad3 | 914 | cpu->prev_tsc = tsc; |
93f0822d DB |
915 | } |
916 | ||
2f86dc4c DB |
917 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
918 | { | |
919 | int delay; | |
920 | ||
921 | delay = msecs_to_jiffies(50); | |
922 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
923 | } | |
924 | ||
93f0822d DB |
925 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
926 | { | |
abf013bf | 927 | int delay; |
93f0822d | 928 | |
abf013bf | 929 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
930 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
931 | } | |
932 | ||
157386b6 | 933 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 934 | { |
c4ee841f | 935 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
7180dddf | 936 | s64 duration_us; |
c4ee841f | 937 | u32 sample_time; |
93f0822d | 938 | |
e0d4c8f8 KCA |
939 | /* |
940 | * core_busy is the ratio of actual performance to max | |
941 | * max_pstate is the max non turbo pstate available | |
942 | * current_pstate was the pstate that was requested during | |
943 | * the last sample period. | |
944 | * | |
945 | * We normalize core_busy, which was our actual percent | |
946 | * performance to what we requested during the last sample | |
947 | * period. The result will be a percentage of busy at a | |
948 | * specified pstate. | |
949 | */ | |
d37e2b76 | 950 | core_busy = cpu->sample.core_pct_busy; |
3bcc6fa9 | 951 | max_pstate = int_tofp(cpu->pstate.max_pstate_physical); |
93f0822d | 952 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 953 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 954 | |
e0d4c8f8 KCA |
955 | /* |
956 | * Since we have a deferred timer, it will not fire unless | |
957 | * we are in C0. So, determine if the actual elapsed time | |
958 | * is significantly greater (3x) than our sample interval. If it | |
959 | * is, then we were idle for a long enough period of time | |
960 | * to adjust our busyness. | |
961 | */ | |
285cb990 | 962 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
7180dddf PB |
963 | duration_us = ktime_us_delta(cpu->sample.time, |
964 | cpu->last_sample_time); | |
c4ee841f DB |
965 | if (duration_us > sample_time * 3) { |
966 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 967 | int_tofp(duration_us)); |
c4ee841f DB |
968 | core_busy = mul_fp(core_busy, sample_ratio); |
969 | } | |
970 | ||
157386b6 PL |
971 | cpu->sample.busy_scaled = core_busy; |
972 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, core_busy); | |
93f0822d DB |
973 | } |
974 | ||
975 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
976 | { | |
157386b6 | 977 | int from, target_pstate; |
4055fad3 DS |
978 | struct sample *sample; |
979 | ||
980 | from = cpu->pstate.current_pstate; | |
93f0822d | 981 | |
157386b6 | 982 | target_pstate = pstate_funcs.get_target_pstate(cpu); |
93f0822d | 983 | |
157386b6 | 984 | intel_pstate_set_pstate(cpu, target_pstate, true); |
4055fad3 DS |
985 | |
986 | sample = &cpu->sample; | |
987 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
157386b6 | 988 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
989 | from, |
990 | cpu->pstate.current_pstate, | |
991 | sample->mperf, | |
992 | sample->aperf, | |
993 | sample->tsc, | |
994 | sample->freq); | |
93f0822d DB |
995 | } |
996 | ||
2f86dc4c DB |
997 | static void intel_hwp_timer_func(unsigned long __data) |
998 | { | |
999 | struct cpudata *cpu = (struct cpudata *) __data; | |
1000 | ||
1001 | intel_pstate_sample(cpu); | |
1002 | intel_hwp_set_sample_time(cpu); | |
1003 | } | |
1004 | ||
93f0822d DB |
1005 | static void intel_pstate_timer_func(unsigned long __data) |
1006 | { | |
1007 | struct cpudata *cpu = (struct cpudata *) __data; | |
1008 | ||
1009 | intel_pstate_sample(cpu); | |
b69880f9 | 1010 | |
ca182aee | 1011 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 | 1012 | |
93f0822d DB |
1013 | intel_pstate_set_sample_time(cpu); |
1014 | } | |
1015 | ||
1016 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1017 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1018 | (unsigned long)&policy } | |
93f0822d DB |
1019 | |
1020 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
1021 | ICPU(0x2a, core_params), |
1022 | ICPU(0x2d, core_params), | |
1421df63 | 1023 | ICPU(0x37, silvermont_params), |
016c8150 DB |
1024 | ICPU(0x3a, core_params), |
1025 | ICPU(0x3c, core_params), | |
c7e241df | 1026 | ICPU(0x3d, core_params), |
016c8150 DB |
1027 | ICPU(0x3e, core_params), |
1028 | ICPU(0x3f, core_params), | |
1029 | ICPU(0x45, core_params), | |
1030 | ICPU(0x46, core_params), | |
43f8a966 | 1031 | ICPU(0x47, core_params), |
1421df63 | 1032 | ICPU(0x4c, airmont_params), |
7ab0256e | 1033 | ICPU(0x4e, core_params), |
c7e241df | 1034 | ICPU(0x4f, core_params), |
1c939123 | 1035 | ICPU(0x5e, core_params), |
c7e241df | 1036 | ICPU(0x56, core_params), |
b34ef932 | 1037 | ICPU(0x57, knl_params), |
93f0822d DB |
1038 | {} |
1039 | }; | |
1040 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1041 | ||
2f86dc4c DB |
1042 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
1043 | ICPU(0x56, core_params), | |
1044 | {} | |
1045 | }; | |
1046 | ||
93f0822d DB |
1047 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1048 | { | |
93f0822d DB |
1049 | struct cpudata *cpu; |
1050 | ||
c0348717 DB |
1051 | if (!all_cpu_data[cpunum]) |
1052 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
1053 | GFP_KERNEL); | |
93f0822d DB |
1054 | if (!all_cpu_data[cpunum]) |
1055 | return -ENOMEM; | |
1056 | ||
1057 | cpu = all_cpu_data[cpunum]; | |
1058 | ||
93f0822d | 1059 | cpu->cpu = cpunum; |
ba88d433 KCA |
1060 | |
1061 | if (hwp_active) | |
1062 | intel_pstate_hwp_enable(cpu); | |
1063 | ||
179e8471 | 1064 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1065 | |
93f0822d | 1066 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 1067 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 1068 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
1069 | |
1070 | if (!hwp_active) | |
1071 | cpu->timer.function = intel_pstate_timer_func; | |
1072 | else | |
1073 | cpu->timer.function = intel_hwp_timer_func; | |
1074 | ||
93f0822d | 1075 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 1076 | intel_pstate_sample(cpu); |
93f0822d DB |
1077 | |
1078 | add_timer_on(&cpu->timer, cpunum); | |
1079 | ||
f16255eb | 1080 | pr_debug("intel_pstate: controlling: cpu %d\n", cpunum); |
93f0822d DB |
1081 | |
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1086 | { | |
1087 | struct sample *sample; | |
1088 | struct cpudata *cpu; | |
1089 | ||
1090 | cpu = all_cpu_data[cpu_num]; | |
1091 | if (!cpu) | |
1092 | return 0; | |
d37e2b76 | 1093 | sample = &cpu->sample; |
93f0822d DB |
1094 | return sample->freq; |
1095 | } | |
1096 | ||
1097 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
1098 | { | |
d3929b83 DB |
1099 | if (!policy->cpuinfo.max_freq) |
1100 | return -ENODEV; | |
1101 | ||
630ec286 SP |
1102 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && |
1103 | policy->max >= policy->cpuinfo.max_freq) { | |
51443fbf PB |
1104 | pr_debug("intel_pstate: set performance\n"); |
1105 | limits = &performance_limits; | |
584ee3dc AY |
1106 | if (hwp_active) |
1107 | intel_pstate_hwp_set(); | |
d1b68485 | 1108 | return 0; |
93f0822d | 1109 | } |
2f86dc4c | 1110 | |
51443fbf PB |
1111 | pr_debug("intel_pstate: set powersave\n"); |
1112 | limits = &powersave_limits; | |
1113 | limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; | |
1114 | limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); | |
8478f539 PB |
1115 | limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, |
1116 | policy->cpuinfo.max_freq); | |
51443fbf | 1117 | limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); |
43717aad CY |
1118 | |
1119 | /* Normalize user input to [min_policy_pct, max_policy_pct] */ | |
51443fbf PB |
1120 | limits->min_perf_pct = max(limits->min_policy_pct, |
1121 | limits->min_sysfs_pct); | |
1122 | limits->min_perf_pct = min(limits->max_policy_pct, | |
1123 | limits->min_perf_pct); | |
1124 | limits->max_perf_pct = min(limits->max_policy_pct, | |
1125 | limits->max_sysfs_pct); | |
1126 | limits->max_perf_pct = max(limits->min_policy_pct, | |
1127 | limits->max_perf_pct); | |
785ee278 | 1128 | limits->max_perf = round_up(limits->max_perf, 8); |
43717aad CY |
1129 | |
1130 | /* Make sure min_perf_pct <= max_perf_pct */ | |
51443fbf | 1131 | limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); |
43717aad | 1132 | |
51443fbf PB |
1133 | limits->min_perf = div_fp(int_tofp(limits->min_perf_pct), |
1134 | int_tofp(100)); | |
1135 | limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), | |
1136 | int_tofp(100)); | |
93f0822d | 1137 | |
2f86dc4c DB |
1138 | if (hwp_active) |
1139 | intel_pstate_hwp_set(); | |
1140 | ||
93f0822d DB |
1141 | return 0; |
1142 | } | |
1143 | ||
1144 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1145 | { | |
be49e346 | 1146 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1147 | |
285cb990 | 1148 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1149 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1150 | return -EINVAL; |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
bb18008f | 1155 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1156 | { |
bb18008f DB |
1157 | int cpu_num = policy->cpu; |
1158 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1159 | |
f16255eb | 1160 | pr_debug("intel_pstate: CPU %d exiting\n", cpu_num); |
bb18008f | 1161 | |
c2294a2f | 1162 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
1163 | if (hwp_active) |
1164 | return; | |
1165 | ||
6c1e4591 | 1166 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
1167 | } |
1168 | ||
2760984f | 1169 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1170 | { |
93f0822d | 1171 | struct cpudata *cpu; |
52e0a509 | 1172 | int rc; |
93f0822d DB |
1173 | |
1174 | rc = intel_pstate_init_cpu(policy->cpu); | |
1175 | if (rc) | |
1176 | return rc; | |
1177 | ||
1178 | cpu = all_cpu_data[policy->cpu]; | |
1179 | ||
51443fbf | 1180 | if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) |
93f0822d DB |
1181 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1182 | else | |
1183 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1184 | ||
b27580b0 DB |
1185 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1186 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1187 | |
1188 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
1189 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1190 | policy->cpuinfo.max_freq = | |
1191 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1192 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1193 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1194 | ||
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | static struct cpufreq_driver intel_pstate_driver = { | |
1199 | .flags = CPUFREQ_CONST_LOOPS, | |
1200 | .verify = intel_pstate_verify_policy, | |
1201 | .setpolicy = intel_pstate_set_policy, | |
1202 | .get = intel_pstate_get, | |
1203 | .init = intel_pstate_cpu_init, | |
bb18008f | 1204 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1205 | .name = "intel_pstate", |
93f0822d DB |
1206 | }; |
1207 | ||
6be26498 | 1208 | static int __initdata no_load; |
2f86dc4c | 1209 | static int __initdata no_hwp; |
d64c3b0b | 1210 | static int __initdata hwp_only; |
aa4ea34d | 1211 | static unsigned int force_load; |
6be26498 | 1212 | |
b563b4e3 DB |
1213 | static int intel_pstate_msrs_not_valid(void) |
1214 | { | |
016c8150 | 1215 | if (!pstate_funcs.get_max() || |
c410833a SK |
1216 | !pstate_funcs.get_min() || |
1217 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1218 | return -ENODEV; |
1219 | ||
b563b4e3 DB |
1220 | return 0; |
1221 | } | |
016c8150 | 1222 | |
e0a261a2 | 1223 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1224 | { |
1225 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
1226 | pid_params.p_gain_pct = policy->p_gain_pct; | |
1227 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1228 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1229 | pid_params.deadband = policy->deadband; | |
1230 | pid_params.setpoint = policy->setpoint; | |
1231 | } | |
1232 | ||
e0a261a2 | 1233 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1234 | { |
1235 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 1236 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
1237 | pstate_funcs.get_min = funcs->get_min; |
1238 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1239 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 1240 | pstate_funcs.set = funcs->set; |
007bea09 | 1241 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
1242 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
1243 | ||
016c8150 DB |
1244 | } |
1245 | ||
fbbcdc07 | 1246 | #if IS_ENABLED(CONFIG_ACPI) |
6ee11e41 | 1247 | #include <acpi/processor.h> |
fbbcdc07 AH |
1248 | |
1249 | static bool intel_pstate_no_acpi_pss(void) | |
1250 | { | |
1251 | int i; | |
1252 | ||
1253 | for_each_possible_cpu(i) { | |
1254 | acpi_status status; | |
1255 | union acpi_object *pss; | |
1256 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1257 | struct acpi_processor *pr = per_cpu(processors, i); | |
1258 | ||
1259 | if (!pr) | |
1260 | continue; | |
1261 | ||
1262 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1263 | if (ACPI_FAILURE(status)) | |
1264 | continue; | |
1265 | ||
1266 | pss = buffer.pointer; | |
1267 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1268 | kfree(pss); | |
1269 | return false; | |
1270 | } | |
1271 | ||
1272 | kfree(pss); | |
1273 | } | |
1274 | ||
1275 | return true; | |
1276 | } | |
1277 | ||
966916ea | 1278 | static bool intel_pstate_has_acpi_ppc(void) |
1279 | { | |
1280 | int i; | |
1281 | ||
1282 | for_each_possible_cpu(i) { | |
1283 | struct acpi_processor *pr = per_cpu(processors, i); | |
1284 | ||
1285 | if (!pr) | |
1286 | continue; | |
1287 | if (acpi_has_method(pr->handle, "_PPC")) | |
1288 | return true; | |
1289 | } | |
1290 | return false; | |
1291 | } | |
1292 | ||
1293 | enum { | |
1294 | PSS, | |
1295 | PPC, | |
1296 | }; | |
1297 | ||
fbbcdc07 AH |
1298 | struct hw_vendor_info { |
1299 | u16 valid; | |
1300 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1301 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1302 | int oem_pwr_table; |
fbbcdc07 AH |
1303 | }; |
1304 | ||
1305 | /* Hardware vendor-specific info that has its own power management modes */ | |
1306 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1307 | {1, "HP ", "ProLiant", PSS}, |
1308 | {1, "ORACLE", "X4-2 ", PPC}, | |
1309 | {1, "ORACLE", "X4-2L ", PPC}, | |
1310 | {1, "ORACLE", "X4-2B ", PPC}, | |
1311 | {1, "ORACLE", "X3-2 ", PPC}, | |
1312 | {1, "ORACLE", "X3-2L ", PPC}, | |
1313 | {1, "ORACLE", "X3-2B ", PPC}, | |
1314 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1315 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1316 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1317 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
1318 | {1, "ORACLE", "X4170 M3", PPC}, |
1319 | {1, "ORACLE", "X4275 M3", PPC}, | |
1320 | {1, "ORACLE", "X6-2 ", PPC}, | |
1321 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
1322 | {0, "", ""}, |
1323 | }; | |
1324 | ||
1325 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1326 | { | |
1327 | struct acpi_table_header hdr; | |
1328 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1329 | const struct x86_cpu_id *id; |
1330 | u64 misc_pwr; | |
1331 | ||
1332 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1333 | if (id) { | |
1334 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1335 | if ( misc_pwr & (1 << 8)) | |
1336 | return true; | |
1337 | } | |
fbbcdc07 | 1338 | |
c410833a SK |
1339 | if (acpi_disabled || |
1340 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1341 | return false; |
1342 | ||
1343 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1344 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1345 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1346 | ACPI_OEM_TABLE_ID_SIZE)) | |
1347 | switch (v_info->oem_pwr_table) { | |
1348 | case PSS: | |
1349 | return intel_pstate_no_acpi_pss(); | |
1350 | case PPC: | |
aa4ea34d EZ |
1351 | return intel_pstate_has_acpi_ppc() && |
1352 | (!force_load); | |
966916ea | 1353 | } |
fbbcdc07 AH |
1354 | } |
1355 | ||
1356 | return false; | |
1357 | } | |
1358 | #else /* CONFIG_ACPI not enabled */ | |
1359 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1360 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1361 | #endif /* CONFIG_ACPI */ |
1362 | ||
93f0822d DB |
1363 | static int __init intel_pstate_init(void) |
1364 | { | |
907cc908 | 1365 | int cpu, rc = 0; |
93f0822d | 1366 | const struct x86_cpu_id *id; |
64df1fdf | 1367 | struct cpu_defaults *cpu_def; |
93f0822d | 1368 | |
6be26498 DB |
1369 | if (no_load) |
1370 | return -ENODEV; | |
1371 | ||
93f0822d DB |
1372 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1373 | if (!id) | |
1374 | return -ENODEV; | |
1375 | ||
fbbcdc07 AH |
1376 | /* |
1377 | * The Intel pstate driver will be ignored if the platform | |
1378 | * firmware has its own power management modes. | |
1379 | */ | |
1380 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1381 | return -ENODEV; | |
1382 | ||
64df1fdf | 1383 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1384 | |
64df1fdf BP |
1385 | copy_pid_params(&cpu_def->pid_policy); |
1386 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1387 | |
b563b4e3 DB |
1388 | if (intel_pstate_msrs_not_valid()) |
1389 | return -ENODEV; | |
1390 | ||
93f0822d DB |
1391 | pr_info("Intel P-state driver initializing.\n"); |
1392 | ||
b57ffac5 | 1393 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1394 | if (!all_cpu_data) |
1395 | return -ENOMEM; | |
93f0822d | 1396 | |
539342f6 PB |
1397 | if (static_cpu_has_safe(X86_FEATURE_HWP) && !no_hwp) { |
1398 | pr_info("intel_pstate: HWP enabled\n"); | |
ba88d433 | 1399 | hwp_active++; |
539342f6 | 1400 | } |
2f86dc4c | 1401 | |
d64c3b0b KCA |
1402 | if (!hwp_active && hwp_only) |
1403 | goto out; | |
1404 | ||
93f0822d DB |
1405 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1406 | if (rc) | |
1407 | goto out; | |
1408 | ||
1409 | intel_pstate_debug_expose_params(); | |
1410 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1411 | |
93f0822d DB |
1412 | return rc; |
1413 | out: | |
907cc908 DB |
1414 | get_online_cpus(); |
1415 | for_each_online_cpu(cpu) { | |
1416 | if (all_cpu_data[cpu]) { | |
1417 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1418 | kfree(all_cpu_data[cpu]); | |
1419 | } | |
1420 | } | |
1421 | ||
1422 | put_online_cpus(); | |
1423 | vfree(all_cpu_data); | |
93f0822d DB |
1424 | return -ENODEV; |
1425 | } | |
1426 | device_initcall(intel_pstate_init); | |
1427 | ||
6be26498 DB |
1428 | static int __init intel_pstate_setup(char *str) |
1429 | { | |
1430 | if (!str) | |
1431 | return -EINVAL; | |
1432 | ||
1433 | if (!strcmp(str, "disable")) | |
1434 | no_load = 1; | |
539342f6 PB |
1435 | if (!strcmp(str, "no_hwp")) { |
1436 | pr_info("intel_pstate: HWP disabled\n"); | |
2f86dc4c | 1437 | no_hwp = 1; |
539342f6 | 1438 | } |
aa4ea34d EZ |
1439 | if (!strcmp(str, "force")) |
1440 | force_load = 1; | |
d64c3b0b KCA |
1441 | if (!strcmp(str, "hwp_only")) |
1442 | hwp_only = 1; | |
6be26498 DB |
1443 | return 0; |
1444 | } | |
1445 | early_param("intel_pstate", intel_pstate_setup); | |
1446 | ||
93f0822d DB |
1447 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1448 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1449 | MODULE_LICENSE("GPL"); |