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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
93f0822d DB |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include <asm/div64.h> | |
32 | #include <asm/msr.h> | |
33 | #include <asm/cpu_device_id.h> | |
34 | ||
61d8d2ab DB |
35 | #define BYT_RATIOS 0x66a |
36 | #define BYT_VIDS 0x66b | |
37 | #define BYT_TURBO_RATIOS 0x66c | |
21855ff5 | 38 | #define BYT_TURBO_VIDS 0x66d |
61d8d2ab | 39 | |
f0fe3cd7 | 40 | #define FRAC_BITS 8 |
93f0822d DB |
41 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
42 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 43 | |
93f0822d DB |
44 | |
45 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
46 | { | |
47 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
48 | } | |
49 | ||
50 | static inline int32_t div_fp(int32_t x, int32_t y) | |
51 | { | |
fa30dff9 | 52 | return div_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
53 | } |
54 | ||
d022a65e DB |
55 | static inline int ceiling_fp(int32_t x) |
56 | { | |
57 | int mask, ret; | |
58 | ||
59 | ret = fp_toint(x); | |
60 | mask = (1 << FRAC_BITS) - 1; | |
61 | if (x & mask) | |
62 | ret += 1; | |
63 | return ret; | |
64 | } | |
65 | ||
93f0822d | 66 | struct sample { |
d253d2a5 | 67 | int32_t core_pct_busy; |
93f0822d DB |
68 | u64 aperf; |
69 | u64 mperf; | |
70 | int freq; | |
c4ee841f | 71 | ktime_t time; |
93f0822d DB |
72 | }; |
73 | ||
74 | struct pstate_data { | |
75 | int current_pstate; | |
76 | int min_pstate; | |
77 | int max_pstate; | |
b27580b0 | 78 | int scaling; |
93f0822d DB |
79 | int turbo_pstate; |
80 | }; | |
81 | ||
007bea09 | 82 | struct vid_data { |
21855ff5 DB |
83 | int min; |
84 | int max; | |
85 | int turbo; | |
007bea09 DB |
86 | int32_t ratio; |
87 | }; | |
88 | ||
93f0822d DB |
89 | struct _pid { |
90 | int setpoint; | |
91 | int32_t integral; | |
92 | int32_t p_gain; | |
93 | int32_t i_gain; | |
94 | int32_t d_gain; | |
95 | int deadband; | |
d253d2a5 | 96 | int32_t last_err; |
93f0822d DB |
97 | }; |
98 | ||
99 | struct cpudata { | |
100 | int cpu; | |
101 | ||
93f0822d DB |
102 | struct timer_list timer; |
103 | ||
93f0822d | 104 | struct pstate_data pstate; |
007bea09 | 105 | struct vid_data vid; |
93f0822d | 106 | struct _pid pid; |
93f0822d | 107 | |
c4ee841f | 108 | ktime_t last_sample_time; |
93f0822d DB |
109 | u64 prev_aperf; |
110 | u64 prev_mperf; | |
d37e2b76 | 111 | struct sample sample; |
93f0822d DB |
112 | }; |
113 | ||
114 | static struct cpudata **all_cpu_data; | |
115 | struct pstate_adjust_policy { | |
116 | int sample_rate_ms; | |
117 | int deadband; | |
118 | int setpoint; | |
119 | int p_gain_pct; | |
120 | int d_gain_pct; | |
121 | int i_gain_pct; | |
122 | }; | |
123 | ||
016c8150 DB |
124 | struct pstate_funcs { |
125 | int (*get_max)(void); | |
126 | int (*get_min)(void); | |
127 | int (*get_turbo)(void); | |
b27580b0 | 128 | int (*get_scaling)(void); |
007bea09 DB |
129 | void (*set)(struct cpudata*, int pstate); |
130 | void (*get_vid)(struct cpudata *); | |
93f0822d DB |
131 | }; |
132 | ||
016c8150 DB |
133 | struct cpu_defaults { |
134 | struct pstate_adjust_policy pid_policy; | |
135 | struct pstate_funcs funcs; | |
93f0822d DB |
136 | }; |
137 | ||
016c8150 DB |
138 | static struct pstate_adjust_policy pid_params; |
139 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 140 | static int hwp_active; |
016c8150 | 141 | |
93f0822d DB |
142 | struct perf_limits { |
143 | int no_turbo; | |
dd5fbf70 | 144 | int turbo_disabled; |
93f0822d DB |
145 | int max_perf_pct; |
146 | int min_perf_pct; | |
147 | int32_t max_perf; | |
148 | int32_t min_perf; | |
d8f469e9 DB |
149 | int max_policy_pct; |
150 | int max_sysfs_pct; | |
93f0822d DB |
151 | }; |
152 | ||
153 | static struct perf_limits limits = { | |
154 | .no_turbo = 0, | |
4521e1a0 | 155 | .turbo_disabled = 0, |
93f0822d DB |
156 | .max_perf_pct = 100, |
157 | .max_perf = int_tofp(1), | |
158 | .min_perf_pct = 0, | |
159 | .min_perf = 0, | |
d8f469e9 DB |
160 | .max_policy_pct = 100, |
161 | .max_sysfs_pct = 100, | |
93f0822d DB |
162 | }; |
163 | ||
164 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
c410833a | 165 | int deadband, int integral) { |
93f0822d DB |
166 | pid->setpoint = setpoint; |
167 | pid->deadband = deadband; | |
168 | pid->integral = int_tofp(integral); | |
d98d099b | 169 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
170 | } |
171 | ||
172 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
173 | { | |
174 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
175 | } | |
176 | ||
177 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
178 | { | |
179 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
180 | } | |
181 | ||
182 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
183 | { | |
93f0822d DB |
184 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
185 | } | |
186 | ||
d253d2a5 | 187 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 188 | { |
d253d2a5 | 189 | signed int result; |
93f0822d DB |
190 | int32_t pterm, dterm, fp_error; |
191 | int32_t integral_limit; | |
192 | ||
d253d2a5 | 193 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 194 | |
d253d2a5 | 195 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
196 | return 0; |
197 | ||
198 | pterm = mul_fp(pid->p_gain, fp_error); | |
199 | ||
200 | pid->integral += fp_error; | |
201 | ||
202 | /* limit the integral term */ | |
203 | integral_limit = int_tofp(30); | |
204 | if (pid->integral > integral_limit) | |
205 | pid->integral = integral_limit; | |
206 | if (pid->integral < -integral_limit) | |
207 | pid->integral = -integral_limit; | |
208 | ||
d253d2a5 BS |
209 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
210 | pid->last_err = fp_error; | |
93f0822d DB |
211 | |
212 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 213 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
214 | return (signed int)fp_toint(result); |
215 | } | |
216 | ||
217 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
218 | { | |
016c8150 DB |
219 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
220 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
221 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 222 | |
2d8d1f18 | 223 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
224 | } |
225 | ||
93f0822d DB |
226 | static inline void intel_pstate_reset_all_pid(void) |
227 | { | |
228 | unsigned int cpu; | |
845c1cbe | 229 | |
93f0822d DB |
230 | for_each_online_cpu(cpu) { |
231 | if (all_cpu_data[cpu]) | |
232 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
233 | } | |
234 | } | |
235 | ||
4521e1a0 GM |
236 | static inline void update_turbo_state(void) |
237 | { | |
238 | u64 misc_en; | |
239 | struct cpudata *cpu; | |
240 | ||
241 | cpu = all_cpu_data[0]; | |
242 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
243 | limits.turbo_disabled = | |
244 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || | |
245 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
246 | } | |
247 | ||
2f86dc4c DB |
248 | #define PCT_TO_HWP(x) (x * 255 / 100) |
249 | static void intel_pstate_hwp_set(void) | |
250 | { | |
251 | int min, max, cpu; | |
252 | u64 value, freq; | |
253 | ||
254 | get_online_cpus(); | |
255 | ||
256 | for_each_online_cpu(cpu) { | |
257 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
258 | min = PCT_TO_HWP(limits.min_perf_pct); | |
259 | value &= ~HWP_MIN_PERF(~0L); | |
260 | value |= HWP_MIN_PERF(min); | |
261 | ||
262 | max = PCT_TO_HWP(limits.max_perf_pct); | |
263 | if (limits.no_turbo) { | |
264 | rdmsrl( MSR_HWP_CAPABILITIES, freq); | |
265 | max = HWP_GUARANTEED_PERF(freq); | |
266 | } | |
267 | ||
268 | value &= ~HWP_MAX_PERF(~0L); | |
269 | value |= HWP_MAX_PERF(max); | |
270 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
271 | } | |
272 | ||
273 | put_online_cpus(); | |
274 | } | |
275 | ||
93f0822d DB |
276 | /************************** debugfs begin ************************/ |
277 | static int pid_param_set(void *data, u64 val) | |
278 | { | |
279 | *(u32 *)data = val; | |
280 | intel_pstate_reset_all_pid(); | |
281 | return 0; | |
282 | } | |
845c1cbe | 283 | |
93f0822d DB |
284 | static int pid_param_get(void *data, u64 *val) |
285 | { | |
286 | *val = *(u32 *)data; | |
287 | return 0; | |
288 | } | |
2d8d1f18 | 289 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
290 | |
291 | struct pid_param { | |
292 | char *name; | |
293 | void *value; | |
294 | }; | |
295 | ||
296 | static struct pid_param pid_files[] = { | |
016c8150 DB |
297 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
298 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
299 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
300 | {"deadband", &pid_params.deadband}, | |
301 | {"setpoint", &pid_params.setpoint}, | |
302 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
303 | {NULL, NULL} |
304 | }; | |
305 | ||
317dd50e | 306 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 307 | { |
317dd50e | 308 | struct dentry *debugfs_parent; |
93f0822d DB |
309 | int i = 0; |
310 | ||
2f86dc4c DB |
311 | if (hwp_active) |
312 | return; | |
93f0822d DB |
313 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
314 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
315 | return; | |
316 | while (pid_files[i].name) { | |
317 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
318 | debugfs_parent, pid_files[i].value, |
319 | &fops_pid_param); | |
93f0822d DB |
320 | i++; |
321 | } | |
322 | } | |
323 | ||
324 | /************************** debugfs end ************************/ | |
325 | ||
326 | /************************** sysfs begin ************************/ | |
327 | #define show_one(file_name, object) \ | |
328 | static ssize_t show_##file_name \ | |
329 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
330 | { \ | |
331 | return sprintf(buf, "%u\n", limits.object); \ | |
332 | } | |
333 | ||
4521e1a0 GM |
334 | static ssize_t show_no_turbo(struct kobject *kobj, |
335 | struct attribute *attr, char *buf) | |
336 | { | |
337 | ssize_t ret; | |
338 | ||
339 | update_turbo_state(); | |
340 | if (limits.turbo_disabled) | |
341 | ret = sprintf(buf, "%u\n", limits.turbo_disabled); | |
342 | else | |
343 | ret = sprintf(buf, "%u\n", limits.no_turbo); | |
344 | ||
345 | return ret; | |
346 | } | |
347 | ||
93f0822d | 348 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 349 | const char *buf, size_t count) |
93f0822d DB |
350 | { |
351 | unsigned int input; | |
352 | int ret; | |
845c1cbe | 353 | |
93f0822d DB |
354 | ret = sscanf(buf, "%u", &input); |
355 | if (ret != 1) | |
356 | return -EINVAL; | |
4521e1a0 GM |
357 | |
358 | update_turbo_state(); | |
dd5fbf70 DB |
359 | if (limits.turbo_disabled) { |
360 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); | |
4521e1a0 | 361 | return -EPERM; |
dd5fbf70 | 362 | } |
2f86dc4c | 363 | |
4521e1a0 GM |
364 | limits.no_turbo = clamp_t(int, input, 0, 1); |
365 | ||
2f86dc4c DB |
366 | if (hwp_active) |
367 | intel_pstate_hwp_set(); | |
368 | ||
93f0822d DB |
369 | return count; |
370 | } | |
371 | ||
372 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 373 | const char *buf, size_t count) |
93f0822d DB |
374 | { |
375 | unsigned int input; | |
376 | int ret; | |
845c1cbe | 377 | |
93f0822d DB |
378 | ret = sscanf(buf, "%u", &input); |
379 | if (ret != 1) | |
380 | return -EINVAL; | |
381 | ||
d8f469e9 DB |
382 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
383 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d | 384 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
845c1cbe | 385 | |
2f86dc4c DB |
386 | if (hwp_active) |
387 | intel_pstate_hwp_set(); | |
93f0822d DB |
388 | return count; |
389 | } | |
390 | ||
391 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 392 | const char *buf, size_t count) |
93f0822d DB |
393 | { |
394 | unsigned int input; | |
395 | int ret; | |
845c1cbe | 396 | |
93f0822d DB |
397 | ret = sscanf(buf, "%u", &input); |
398 | if (ret != 1) | |
399 | return -EINVAL; | |
400 | limits.min_perf_pct = clamp_t(int, input, 0 , 100); | |
401 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
402 | ||
2f86dc4c DB |
403 | if (hwp_active) |
404 | intel_pstate_hwp_set(); | |
93f0822d DB |
405 | return count; |
406 | } | |
407 | ||
93f0822d DB |
408 | show_one(max_perf_pct, max_perf_pct); |
409 | show_one(min_perf_pct, min_perf_pct); | |
410 | ||
411 | define_one_global_rw(no_turbo); | |
412 | define_one_global_rw(max_perf_pct); | |
413 | define_one_global_rw(min_perf_pct); | |
414 | ||
415 | static struct attribute *intel_pstate_attributes[] = { | |
416 | &no_turbo.attr, | |
417 | &max_perf_pct.attr, | |
418 | &min_perf_pct.attr, | |
419 | NULL | |
420 | }; | |
421 | ||
422 | static struct attribute_group intel_pstate_attr_group = { | |
423 | .attrs = intel_pstate_attributes, | |
424 | }; | |
93f0822d | 425 | |
317dd50e | 426 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 427 | { |
317dd50e | 428 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
429 | int rc; |
430 | ||
431 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
432 | &cpu_subsys.dev_root->kobj); | |
433 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 434 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
435 | BUG_ON(rc); |
436 | } | |
93f0822d | 437 | /************************** sysfs end ************************/ |
2f86dc4c DB |
438 | |
439 | static void intel_pstate_hwp_enable(void) | |
440 | { | |
441 | hwp_active++; | |
442 | pr_info("intel_pstate HWP enabled\n"); | |
443 | ||
444 | wrmsrl( MSR_PM_ENABLE, 0x1); | |
445 | } | |
446 | ||
19e77c28 DB |
447 | static int byt_get_min_pstate(void) |
448 | { | |
449 | u64 value; | |
845c1cbe | 450 | |
19e77c28 | 451 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 452 | return (value >> 8) & 0x7F; |
19e77c28 DB |
453 | } |
454 | ||
455 | static int byt_get_max_pstate(void) | |
456 | { | |
457 | u64 value; | |
845c1cbe | 458 | |
19e77c28 | 459 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 460 | return (value >> 16) & 0x7F; |
19e77c28 | 461 | } |
93f0822d | 462 | |
61d8d2ab DB |
463 | static int byt_get_turbo_pstate(void) |
464 | { | |
465 | u64 value; | |
845c1cbe | 466 | |
61d8d2ab | 467 | rdmsrl(BYT_TURBO_RATIOS, value); |
c16ed060 | 468 | return value & 0x7F; |
61d8d2ab DB |
469 | } |
470 | ||
007bea09 DB |
471 | static void byt_set_pstate(struct cpudata *cpudata, int pstate) |
472 | { | |
473 | u64 val; | |
474 | int32_t vid_fp; | |
475 | u32 vid; | |
476 | ||
477 | val = pstate << 8; | |
dd5fbf70 | 478 | if (limits.no_turbo && !limits.turbo_disabled) |
007bea09 DB |
479 | val |= (u64)1 << 32; |
480 | ||
481 | vid_fp = cpudata->vid.min + mul_fp( | |
482 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
483 | cpudata->vid.ratio); | |
484 | ||
485 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 486 | vid = ceiling_fp(vid_fp); |
007bea09 | 487 | |
21855ff5 DB |
488 | if (pstate > cpudata->pstate.max_pstate) |
489 | vid = cpudata->vid.turbo; | |
490 | ||
007bea09 DB |
491 | val |= vid; |
492 | ||
493 | wrmsrl(MSR_IA32_PERF_CTL, val); | |
494 | } | |
495 | ||
b27580b0 DB |
496 | #define BYT_BCLK_FREQS 5 |
497 | static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; | |
498 | ||
499 | static int byt_get_scaling(void) | |
500 | { | |
501 | u64 value; | |
502 | int i; | |
503 | ||
504 | rdmsrl(MSR_FSB_FREQ, value); | |
505 | i = value & 0x3; | |
506 | ||
507 | BUG_ON(i > BYT_BCLK_FREQS); | |
508 | ||
509 | return byt_freq_table[i] * 100; | |
510 | } | |
511 | ||
007bea09 DB |
512 | static void byt_get_vid(struct cpudata *cpudata) |
513 | { | |
514 | u64 value; | |
515 | ||
516 | rdmsrl(BYT_VIDS, value); | |
c16ed060 DB |
517 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
518 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
519 | cpudata->vid.ratio = div_fp( |
520 | cpudata->vid.max - cpudata->vid.min, | |
521 | int_tofp(cpudata->pstate.max_pstate - | |
522 | cpudata->pstate.min_pstate)); | |
21855ff5 DB |
523 | |
524 | rdmsrl(BYT_TURBO_VIDS, value); | |
525 | cpudata->vid.turbo = value & 0x7f; | |
007bea09 DB |
526 | } |
527 | ||
016c8150 | 528 | static int core_get_min_pstate(void) |
93f0822d DB |
529 | { |
530 | u64 value; | |
845c1cbe | 531 | |
05e99c8c | 532 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
533 | return (value >> 40) & 0xFF; |
534 | } | |
535 | ||
016c8150 | 536 | static int core_get_max_pstate(void) |
93f0822d DB |
537 | { |
538 | u64 value; | |
845c1cbe | 539 | |
05e99c8c | 540 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
541 | return (value >> 8) & 0xFF; |
542 | } | |
543 | ||
016c8150 | 544 | static int core_get_turbo_pstate(void) |
93f0822d DB |
545 | { |
546 | u64 value; | |
547 | int nont, ret; | |
845c1cbe | 548 | |
05e99c8c | 549 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 550 | nont = core_get_max_pstate(); |
285cb990 | 551 | ret = (value) & 255; |
93f0822d DB |
552 | if (ret <= nont) |
553 | ret = nont; | |
554 | return ret; | |
555 | } | |
556 | ||
b27580b0 DB |
557 | static inline int core_get_scaling(void) |
558 | { | |
559 | return 100000; | |
560 | } | |
561 | ||
007bea09 | 562 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
563 | { |
564 | u64 val; | |
565 | ||
566 | val = pstate << 8; | |
dd5fbf70 | 567 | if (limits.no_turbo && !limits.turbo_disabled) |
016c8150 DB |
568 | val |= (u64)1 << 32; |
569 | ||
bb18008f | 570 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
571 | } |
572 | ||
573 | static struct cpu_defaults core_params = { | |
574 | .pid_policy = { | |
575 | .sample_rate_ms = 10, | |
576 | .deadband = 0, | |
577 | .setpoint = 97, | |
578 | .p_gain_pct = 20, | |
579 | .d_gain_pct = 0, | |
580 | .i_gain_pct = 0, | |
581 | }, | |
582 | .funcs = { | |
583 | .get_max = core_get_max_pstate, | |
584 | .get_min = core_get_min_pstate, | |
585 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 586 | .get_scaling = core_get_scaling, |
016c8150 DB |
587 | .set = core_set_pstate, |
588 | }, | |
589 | }; | |
590 | ||
19e77c28 DB |
591 | static struct cpu_defaults byt_params = { |
592 | .pid_policy = { | |
593 | .sample_rate_ms = 10, | |
594 | .deadband = 0, | |
595 | .setpoint = 97, | |
596 | .p_gain_pct = 14, | |
597 | .d_gain_pct = 0, | |
598 | .i_gain_pct = 4, | |
599 | }, | |
600 | .funcs = { | |
601 | .get_max = byt_get_max_pstate, | |
602 | .get_min = byt_get_min_pstate, | |
61d8d2ab | 603 | .get_turbo = byt_get_turbo_pstate, |
007bea09 | 604 | .set = byt_set_pstate, |
b27580b0 | 605 | .get_scaling = byt_get_scaling, |
007bea09 | 606 | .get_vid = byt_get_vid, |
19e77c28 DB |
607 | }, |
608 | }; | |
609 | ||
93f0822d DB |
610 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
611 | { | |
612 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 613 | int max_perf_adj; |
93f0822d | 614 | int min_perf; |
845c1cbe | 615 | |
4521e1a0 | 616 | if (limits.no_turbo || limits.turbo_disabled) |
93f0822d DB |
617 | max_perf = cpu->pstate.max_pstate; |
618 | ||
7244cb62 DB |
619 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
620 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
621 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
622 | ||
623 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
2d8d1f18 | 624 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
625 | } |
626 | ||
627 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) | |
628 | { | |
629 | int max_perf, min_perf; | |
630 | ||
4521e1a0 GM |
631 | update_turbo_state(); |
632 | ||
93f0822d DB |
633 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
634 | ||
635 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
636 | ||
637 | if (pstate == cpu->pstate.current_pstate) | |
638 | return; | |
639 | ||
b27580b0 | 640 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 641 | |
93f0822d | 642 | cpu->pstate.current_pstate = pstate; |
93f0822d | 643 | |
007bea09 | 644 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
645 | } |
646 | ||
93f0822d DB |
647 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
648 | { | |
016c8150 DB |
649 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
650 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
651 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
b27580b0 | 652 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 653 | |
007bea09 DB |
654 | if (pstate_funcs.get_vid) |
655 | pstate_funcs.get_vid(cpu); | |
d40a63c4 | 656 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
657 | } |
658 | ||
6b17ddb2 | 659 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 660 | { |
6b17ddb2 | 661 | struct sample *sample = &cpu->sample; |
bf810222 | 662 | int64_t core_pct; |
93f0822d | 663 | |
bf810222 | 664 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 665 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 666 | |
fcb6a15c | 667 | sample->freq = fp_toint( |
b27580b0 DB |
668 | mul_fp(int_tofp( |
669 | cpu->pstate.max_pstate * cpu->pstate.scaling / 100), | |
670 | core_pct)); | |
fcb6a15c | 671 | |
bf810222 | 672 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
673 | } |
674 | ||
675 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
676 | { | |
93f0822d | 677 | u64 aperf, mperf; |
4ab60c3f | 678 | unsigned long flags; |
93f0822d | 679 | |
4ab60c3f | 680 | local_irq_save(flags); |
93f0822d DB |
681 | rdmsrl(MSR_IA32_APERF, aperf); |
682 | rdmsrl(MSR_IA32_MPERF, mperf); | |
4ab60c3f | 683 | local_irq_restore(flags); |
b69880f9 | 684 | |
c4ee841f DB |
685 | cpu->last_sample_time = cpu->sample.time; |
686 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
687 | cpu->sample.aperf = aperf; |
688 | cpu->sample.mperf = mperf; | |
d37e2b76 DB |
689 | cpu->sample.aperf -= cpu->prev_aperf; |
690 | cpu->sample.mperf -= cpu->prev_mperf; | |
1abc4b20 | 691 | |
6b17ddb2 | 692 | intel_pstate_calc_busy(cpu); |
93f0822d | 693 | |
93f0822d DB |
694 | cpu->prev_aperf = aperf; |
695 | cpu->prev_mperf = mperf; | |
696 | } | |
697 | ||
2f86dc4c DB |
698 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
699 | { | |
700 | int delay; | |
701 | ||
702 | delay = msecs_to_jiffies(50); | |
703 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
704 | } | |
705 | ||
93f0822d DB |
706 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
707 | { | |
abf013bf | 708 | int delay; |
93f0822d | 709 | |
abf013bf | 710 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
711 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
712 | } | |
713 | ||
d253d2a5 | 714 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 715 | { |
c4ee841f DB |
716 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
717 | u32 duration_us; | |
718 | u32 sample_time; | |
93f0822d | 719 | |
d37e2b76 | 720 | core_busy = cpu->sample.core_pct_busy; |
2134ed4d | 721 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 722 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 723 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 724 | |
285cb990 | 725 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
c4ee841f | 726 | duration_us = (u32) ktime_us_delta(cpu->sample.time, |
c410833a | 727 | cpu->last_sample_time); |
c4ee841f DB |
728 | if (duration_us > sample_time * 3) { |
729 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 730 | int_tofp(duration_us)); |
c4ee841f DB |
731 | core_busy = mul_fp(core_busy, sample_ratio); |
732 | } | |
733 | ||
f0fe3cd7 | 734 | return core_busy; |
93f0822d DB |
735 | } |
736 | ||
737 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
738 | { | |
d253d2a5 | 739 | int32_t busy_scaled; |
93f0822d | 740 | struct _pid *pid; |
4b707c89 | 741 | signed int ctl; |
93f0822d DB |
742 | |
743 | pid = &cpu->pid; | |
744 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
745 | ||
746 | ctl = pid_calc(pid, busy_scaled); | |
747 | ||
4b707c89 SK |
748 | /* Negative values of ctl increase the pstate and vice versa */ |
749 | intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl); | |
93f0822d DB |
750 | } |
751 | ||
2f86dc4c DB |
752 | static void intel_hwp_timer_func(unsigned long __data) |
753 | { | |
754 | struct cpudata *cpu = (struct cpudata *) __data; | |
755 | ||
756 | intel_pstate_sample(cpu); | |
757 | intel_hwp_set_sample_time(cpu); | |
758 | } | |
759 | ||
93f0822d DB |
760 | static void intel_pstate_timer_func(unsigned long __data) |
761 | { | |
762 | struct cpudata *cpu = (struct cpudata *) __data; | |
b69880f9 | 763 | struct sample *sample; |
93f0822d DB |
764 | |
765 | intel_pstate_sample(cpu); | |
b69880f9 | 766 | |
d37e2b76 | 767 | sample = &cpu->sample; |
b69880f9 | 768 | |
ca182aee | 769 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 DB |
770 | |
771 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
772 | fp_toint(intel_pstate_get_scaled_busy(cpu)), | |
773 | cpu->pstate.current_pstate, | |
774 | sample->mperf, | |
775 | sample->aperf, | |
b69880f9 DB |
776 | sample->freq); |
777 | ||
93f0822d DB |
778 | intel_pstate_set_sample_time(cpu); |
779 | } | |
780 | ||
781 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
782 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
783 | (unsigned long)&policy } | |
93f0822d DB |
784 | |
785 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
786 | ICPU(0x2a, core_params), |
787 | ICPU(0x2d, core_params), | |
19e77c28 | 788 | ICPU(0x37, byt_params), |
016c8150 DB |
789 | ICPU(0x3a, core_params), |
790 | ICPU(0x3c, core_params), | |
c7e241df | 791 | ICPU(0x3d, core_params), |
016c8150 DB |
792 | ICPU(0x3e, core_params), |
793 | ICPU(0x3f, core_params), | |
794 | ICPU(0x45, core_params), | |
795 | ICPU(0x46, core_params), | |
16405f98 | 796 | ICPU(0x4c, byt_params), |
c7e241df DB |
797 | ICPU(0x4f, core_params), |
798 | ICPU(0x56, core_params), | |
93f0822d DB |
799 | {} |
800 | }; | |
801 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
802 | ||
2f86dc4c DB |
803 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
804 | ICPU(0x56, core_params), | |
805 | {} | |
806 | }; | |
807 | ||
93f0822d DB |
808 | static int intel_pstate_init_cpu(unsigned int cpunum) |
809 | { | |
93f0822d DB |
810 | struct cpudata *cpu; |
811 | ||
c0348717 DB |
812 | if (!all_cpu_data[cpunum]) |
813 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
814 | GFP_KERNEL); | |
93f0822d DB |
815 | if (!all_cpu_data[cpunum]) |
816 | return -ENOMEM; | |
817 | ||
818 | cpu = all_cpu_data[cpunum]; | |
819 | ||
93f0822d | 820 | cpu->cpu = cpunum; |
179e8471 | 821 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 822 | |
93f0822d | 823 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 824 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 825 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
826 | |
827 | if (!hwp_active) | |
828 | cpu->timer.function = intel_pstate_timer_func; | |
829 | else | |
830 | cpu->timer.function = intel_hwp_timer_func; | |
831 | ||
93f0822d | 832 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 833 | intel_pstate_sample(cpu); |
93f0822d DB |
834 | |
835 | add_timer_on(&cpu->timer, cpunum); | |
836 | ||
ce717613 | 837 | pr_debug("Intel pstate controlling: cpu %d\n", cpunum); |
93f0822d DB |
838 | |
839 | return 0; | |
840 | } | |
841 | ||
842 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
843 | { | |
844 | struct sample *sample; | |
845 | struct cpudata *cpu; | |
846 | ||
847 | cpu = all_cpu_data[cpu_num]; | |
848 | if (!cpu) | |
849 | return 0; | |
d37e2b76 | 850 | sample = &cpu->sample; |
93f0822d DB |
851 | return sample->freq; |
852 | } | |
853 | ||
854 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
855 | { | |
d3929b83 DB |
856 | if (!policy->cpuinfo.max_freq) |
857 | return -ENODEV; | |
858 | ||
93f0822d DB |
859 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { |
860 | limits.min_perf_pct = 100; | |
861 | limits.min_perf = int_tofp(1); | |
36b4bed5 | 862 | limits.max_policy_pct = 100; |
93f0822d DB |
863 | limits.max_perf_pct = 100; |
864 | limits.max_perf = int_tofp(1); | |
4521e1a0 | 865 | limits.no_turbo = 0; |
d1b68485 | 866 | return 0; |
93f0822d | 867 | } |
2f86dc4c | 868 | |
d1b68485 SP |
869 | limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
870 | limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100); | |
871 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
872 | ||
285cb990 | 873 | limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; |
d8f469e9 DB |
874 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); |
875 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 876 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d | 877 | |
2f86dc4c DB |
878 | if (hwp_active) |
879 | intel_pstate_hwp_set(); | |
880 | ||
93f0822d DB |
881 | return 0; |
882 | } | |
883 | ||
884 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
885 | { | |
be49e346 | 886 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 887 | |
285cb990 | 888 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 889 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
890 | return -EINVAL; |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
bb18008f | 895 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 896 | { |
bb18008f DB |
897 | int cpu_num = policy->cpu; |
898 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 899 | |
bb18008f DB |
900 | pr_info("intel_pstate CPU %d exiting\n", cpu_num); |
901 | ||
c2294a2f | 902 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
903 | if (hwp_active) |
904 | return; | |
905 | ||
bb18008f | 906 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
907 | } |
908 | ||
2760984f | 909 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 910 | { |
93f0822d | 911 | struct cpudata *cpu; |
52e0a509 | 912 | int rc; |
93f0822d DB |
913 | |
914 | rc = intel_pstate_init_cpu(policy->cpu); | |
915 | if (rc) | |
916 | return rc; | |
917 | ||
918 | cpu = all_cpu_data[policy->cpu]; | |
919 | ||
dd5fbf70 | 920 | if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) |
93f0822d DB |
921 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
922 | else | |
923 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
924 | ||
b27580b0 DB |
925 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
926 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
927 | |
928 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
929 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
930 | policy->cpuinfo.max_freq = | |
931 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
932 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
933 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
934 | ||
935 | return 0; | |
936 | } | |
937 | ||
938 | static struct cpufreq_driver intel_pstate_driver = { | |
939 | .flags = CPUFREQ_CONST_LOOPS, | |
940 | .verify = intel_pstate_verify_policy, | |
941 | .setpolicy = intel_pstate_set_policy, | |
942 | .get = intel_pstate_get, | |
943 | .init = intel_pstate_cpu_init, | |
bb18008f | 944 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 945 | .name = "intel_pstate", |
93f0822d DB |
946 | }; |
947 | ||
6be26498 | 948 | static int __initdata no_load; |
2f86dc4c | 949 | static int __initdata no_hwp; |
6be26498 | 950 | |
b563b4e3 DB |
951 | static int intel_pstate_msrs_not_valid(void) |
952 | { | |
953 | /* Check that all the msr's we are using are valid. */ | |
954 | u64 aperf, mperf, tmp; | |
955 | ||
956 | rdmsrl(MSR_IA32_APERF, aperf); | |
957 | rdmsrl(MSR_IA32_MPERF, mperf); | |
958 | ||
016c8150 | 959 | if (!pstate_funcs.get_max() || |
c410833a SK |
960 | !pstate_funcs.get_min() || |
961 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
962 | return -ENODEV; |
963 | ||
964 | rdmsrl(MSR_IA32_APERF, tmp); | |
965 | if (!(tmp - aperf)) | |
966 | return -ENODEV; | |
967 | ||
968 | rdmsrl(MSR_IA32_MPERF, tmp); | |
969 | if (!(tmp - mperf)) | |
970 | return -ENODEV; | |
971 | ||
972 | return 0; | |
973 | } | |
016c8150 | 974 | |
e0a261a2 | 975 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
976 | { |
977 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
978 | pid_params.p_gain_pct = policy->p_gain_pct; | |
979 | pid_params.i_gain_pct = policy->i_gain_pct; | |
980 | pid_params.d_gain_pct = policy->d_gain_pct; | |
981 | pid_params.deadband = policy->deadband; | |
982 | pid_params.setpoint = policy->setpoint; | |
983 | } | |
984 | ||
e0a261a2 | 985 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
986 | { |
987 | pstate_funcs.get_max = funcs->get_max; | |
988 | pstate_funcs.get_min = funcs->get_min; | |
989 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 990 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 991 | pstate_funcs.set = funcs->set; |
007bea09 | 992 | pstate_funcs.get_vid = funcs->get_vid; |
016c8150 DB |
993 | } |
994 | ||
fbbcdc07 AH |
995 | #if IS_ENABLED(CONFIG_ACPI) |
996 | #include <acpi/processor.h> | |
997 | ||
998 | static bool intel_pstate_no_acpi_pss(void) | |
999 | { | |
1000 | int i; | |
1001 | ||
1002 | for_each_possible_cpu(i) { | |
1003 | acpi_status status; | |
1004 | union acpi_object *pss; | |
1005 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1006 | struct acpi_processor *pr = per_cpu(processors, i); | |
1007 | ||
1008 | if (!pr) | |
1009 | continue; | |
1010 | ||
1011 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1012 | if (ACPI_FAILURE(status)) | |
1013 | continue; | |
1014 | ||
1015 | pss = buffer.pointer; | |
1016 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1017 | kfree(pss); | |
1018 | return false; | |
1019 | } | |
1020 | ||
1021 | kfree(pss); | |
1022 | } | |
1023 | ||
1024 | return true; | |
1025 | } | |
1026 | ||
1027 | struct hw_vendor_info { | |
1028 | u16 valid; | |
1029 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1030 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
1031 | }; | |
1032 | ||
1033 | /* Hardware vendor-specific info that has its own power management modes */ | |
1034 | static struct hw_vendor_info vendor_info[] = { | |
1035 | {1, "HP ", "ProLiant"}, | |
1036 | {0, "", ""}, | |
1037 | }; | |
1038 | ||
1039 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1040 | { | |
1041 | struct acpi_table_header hdr; | |
1042 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1043 | const struct x86_cpu_id *id; |
1044 | u64 misc_pwr; | |
1045 | ||
1046 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1047 | if (id) { | |
1048 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1049 | if ( misc_pwr & (1 << 8)) | |
1050 | return true; | |
1051 | } | |
fbbcdc07 | 1052 | |
c410833a SK |
1053 | if (acpi_disabled || |
1054 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1055 | return false; |
1056 | ||
1057 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a SK |
1058 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
1059 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) && | |
1060 | intel_pstate_no_acpi_pss()) | |
fbbcdc07 AH |
1061 | return true; |
1062 | } | |
1063 | ||
1064 | return false; | |
1065 | } | |
1066 | #else /* CONFIG_ACPI not enabled */ | |
1067 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
1068 | #endif /* CONFIG_ACPI */ | |
1069 | ||
93f0822d DB |
1070 | static int __init intel_pstate_init(void) |
1071 | { | |
907cc908 | 1072 | int cpu, rc = 0; |
93f0822d | 1073 | const struct x86_cpu_id *id; |
016c8150 | 1074 | struct cpu_defaults *cpu_info; |
2f86dc4c | 1075 | struct cpuinfo_x86 *c = &boot_cpu_data; |
93f0822d | 1076 | |
6be26498 DB |
1077 | if (no_load) |
1078 | return -ENODEV; | |
1079 | ||
93f0822d DB |
1080 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1081 | if (!id) | |
1082 | return -ENODEV; | |
1083 | ||
fbbcdc07 AH |
1084 | /* |
1085 | * The Intel pstate driver will be ignored if the platform | |
1086 | * firmware has its own power management modes. | |
1087 | */ | |
1088 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1089 | return -ENODEV; | |
1090 | ||
016c8150 DB |
1091 | cpu_info = (struct cpu_defaults *)id->driver_data; |
1092 | ||
1093 | copy_pid_params(&cpu_info->pid_policy); | |
1094 | copy_cpu_funcs(&cpu_info->funcs); | |
1095 | ||
b563b4e3 DB |
1096 | if (intel_pstate_msrs_not_valid()) |
1097 | return -ENODEV; | |
1098 | ||
93f0822d DB |
1099 | pr_info("Intel P-state driver initializing.\n"); |
1100 | ||
b57ffac5 | 1101 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1102 | if (!all_cpu_data) |
1103 | return -ENOMEM; | |
93f0822d | 1104 | |
2f86dc4c DB |
1105 | if (cpu_has(c,X86_FEATURE_HWP) && !no_hwp) |
1106 | intel_pstate_hwp_enable(); | |
1107 | ||
93f0822d DB |
1108 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1109 | if (rc) | |
1110 | goto out; | |
1111 | ||
1112 | intel_pstate_debug_expose_params(); | |
1113 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1114 | |
93f0822d DB |
1115 | return rc; |
1116 | out: | |
907cc908 DB |
1117 | get_online_cpus(); |
1118 | for_each_online_cpu(cpu) { | |
1119 | if (all_cpu_data[cpu]) { | |
1120 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1121 | kfree(all_cpu_data[cpu]); | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | put_online_cpus(); | |
1126 | vfree(all_cpu_data); | |
93f0822d DB |
1127 | return -ENODEV; |
1128 | } | |
1129 | device_initcall(intel_pstate_init); | |
1130 | ||
6be26498 DB |
1131 | static int __init intel_pstate_setup(char *str) |
1132 | { | |
1133 | if (!str) | |
1134 | return -EINVAL; | |
1135 | ||
1136 | if (!strcmp(str, "disable")) | |
1137 | no_load = 1; | |
2f86dc4c DB |
1138 | if (!strcmp(str, "no_hwp")) |
1139 | no_hwp = 1; | |
6be26498 DB |
1140 | return 0; |
1141 | } | |
1142 | early_param("intel_pstate", intel_pstate_setup); | |
1143 | ||
93f0822d DB |
1144 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1145 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1146 | MODULE_LICENSE("GPL"); |