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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
001c76f0 RW |
40 | #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 |
41 | ||
938d21a2 PL |
42 | #define ATOM_RATIOS 0x66a |
43 | #define ATOM_VIDS 0x66b | |
44 | #define ATOM_TURBO_RATIOS 0x66c | |
45 | #define ATOM_TURBO_VIDS 0x66d | |
61d8d2ab | 46 | |
9522a2ff SP |
47 | #ifdef CONFIG_ACPI |
48 | #include <acpi/processor.h> | |
49 | #endif | |
50 | ||
f0fe3cd7 | 51 | #define FRAC_BITS 8 |
93f0822d DB |
52 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
53 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 54 | |
a1c9787d RW |
55 | #define EXT_BITS 6 |
56 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
57 | ||
93f0822d DB |
58 | static inline int32_t mul_fp(int32_t x, int32_t y) |
59 | { | |
60 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
61 | } | |
62 | ||
7180dddf | 63 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 64 | { |
7180dddf | 65 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
66 | } |
67 | ||
d022a65e DB |
68 | static inline int ceiling_fp(int32_t x) |
69 | { | |
70 | int mask, ret; | |
71 | ||
72 | ret = fp_toint(x); | |
73 | mask = (1 << FRAC_BITS) - 1; | |
74 | if (x & mask) | |
75 | ret += 1; | |
76 | return ret; | |
77 | } | |
78 | ||
a1c9787d RW |
79 | static inline u64 mul_ext_fp(u64 x, u64 y) |
80 | { | |
81 | return (x * y) >> EXT_FRAC_BITS; | |
82 | } | |
83 | ||
84 | static inline u64 div_ext_fp(u64 x, u64 y) | |
85 | { | |
86 | return div64_u64(x << EXT_FRAC_BITS, y); | |
87 | } | |
88 | ||
13ad7701 SP |
89 | /** |
90 | * struct sample - Store performance sample | |
a1c9787d | 91 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
92 | * performance during last sample period |
93 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 94 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
95 | * to account for cpu idle period |
96 | * @aperf: Difference of actual performance frequency clock count | |
97 | * read from APERF MSR between last and current sample | |
98 | * @mperf: Difference of maximum performance frequency clock count | |
99 | * read from MPERF MSR between last and current sample | |
100 | * @tsc: Difference of time stamp counter between last and | |
101 | * current sample | |
13ad7701 SP |
102 | * @time: Current time from scheduler |
103 | * | |
104 | * This structure is used in the cpudata structure to store performance sample | |
105 | * data for choosing next P State. | |
106 | */ | |
93f0822d | 107 | struct sample { |
a1c9787d | 108 | int32_t core_avg_perf; |
157386b6 | 109 | int32_t busy_scaled; |
93f0822d DB |
110 | u64 aperf; |
111 | u64 mperf; | |
4055fad3 | 112 | u64 tsc; |
a4675fbc | 113 | u64 time; |
93f0822d DB |
114 | }; |
115 | ||
13ad7701 SP |
116 | /** |
117 | * struct pstate_data - Store P state data | |
118 | * @current_pstate: Current requested P state | |
119 | * @min_pstate: Min P state possible for this platform | |
120 | * @max_pstate: Max P state possible for this platform | |
121 | * @max_pstate_physical:This is physical Max P state for a processor | |
122 | * This can be higher than the max_pstate which can | |
123 | * be limited by platform thermal design power limits | |
124 | * @scaling: Scaling factor to convert frequency to cpufreq | |
125 | * frequency units | |
126 | * @turbo_pstate: Max Turbo P state possible for this platform | |
001c76f0 RW |
127 | * @max_freq: @max_pstate frequency in cpufreq units |
128 | * @turbo_freq: @turbo_pstate frequency in cpufreq units | |
13ad7701 SP |
129 | * |
130 | * Stores the per cpu model P state limits and current P state. | |
131 | */ | |
93f0822d DB |
132 | struct pstate_data { |
133 | int current_pstate; | |
134 | int min_pstate; | |
135 | int max_pstate; | |
3bcc6fa9 | 136 | int max_pstate_physical; |
b27580b0 | 137 | int scaling; |
93f0822d | 138 | int turbo_pstate; |
001c76f0 RW |
139 | unsigned int max_freq; |
140 | unsigned int turbo_freq; | |
93f0822d DB |
141 | }; |
142 | ||
13ad7701 SP |
143 | /** |
144 | * struct vid_data - Stores voltage information data | |
145 | * @min: VID data for this platform corresponding to | |
146 | * the lowest P state | |
147 | * @max: VID data corresponding to the highest P State. | |
148 | * @turbo: VID data for turbo P state | |
149 | * @ratio: Ratio of (vid max - vid min) / | |
150 | * (max P state - Min P State) | |
151 | * | |
152 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
153 | * This data is used in Atom platforms, where in addition to target P state, | |
154 | * the voltage data needs to be specified to select next P State. | |
155 | */ | |
007bea09 | 156 | struct vid_data { |
21855ff5 DB |
157 | int min; |
158 | int max; | |
159 | int turbo; | |
007bea09 DB |
160 | int32_t ratio; |
161 | }; | |
162 | ||
13ad7701 SP |
163 | /** |
164 | * struct _pid - Stores PID data | |
165 | * @setpoint: Target set point for busyness or performance | |
166 | * @integral: Storage for accumulated error values | |
167 | * @p_gain: PID proportional gain | |
168 | * @i_gain: PID integral gain | |
169 | * @d_gain: PID derivative gain | |
170 | * @deadband: PID deadband | |
171 | * @last_err: Last error storage for integral part of PID calculation | |
172 | * | |
173 | * Stores PID coefficients and last error for PID controller. | |
174 | */ | |
93f0822d DB |
175 | struct _pid { |
176 | int setpoint; | |
177 | int32_t integral; | |
178 | int32_t p_gain; | |
179 | int32_t i_gain; | |
180 | int32_t d_gain; | |
181 | int deadband; | |
d253d2a5 | 182 | int32_t last_err; |
93f0822d DB |
183 | }; |
184 | ||
eae48f04 SP |
185 | /** |
186 | * struct perf_limits - Store user and policy limits | |
187 | * @no_turbo: User requested turbo state from intel_pstate sysfs | |
188 | * @turbo_disabled: Platform turbo status either from msr | |
189 | * MSR_IA32_MISC_ENABLE or when maximum available pstate | |
190 | * matches the maximum turbo pstate | |
191 | * @max_perf_pct: Effective maximum performance limit in percentage, this | |
192 | * is minimum of either limits enforced by cpufreq policy | |
193 | * or limits from user set limits via intel_pstate sysfs | |
194 | * @min_perf_pct: Effective minimum performance limit in percentage, this | |
195 | * is maximum of either limits enforced by cpufreq policy | |
196 | * or limits from user set limits via intel_pstate sysfs | |
197 | * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct | |
198 | * This value is used to limit max pstate | |
199 | * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct | |
200 | * This value is used to limit min pstate | |
201 | * @max_policy_pct: The maximum performance in percentage enforced by | |
202 | * cpufreq setpolicy interface | |
203 | * @max_sysfs_pct: The maximum performance in percentage enforced by | |
204 | * intel pstate sysfs interface, unused when per cpu | |
205 | * controls are enforced | |
206 | * @min_policy_pct: The minimum performance in percentage enforced by | |
207 | * cpufreq setpolicy interface | |
208 | * @min_sysfs_pct: The minimum performance in percentage enforced by | |
209 | * intel pstate sysfs interface, unused when per cpu | |
210 | * controls are enforced | |
211 | * | |
212 | * Storage for user and policy defined limits. | |
213 | */ | |
214 | struct perf_limits { | |
215 | int no_turbo; | |
216 | int turbo_disabled; | |
217 | int max_perf_pct; | |
218 | int min_perf_pct; | |
219 | int32_t max_perf; | |
220 | int32_t min_perf; | |
221 | int max_policy_pct; | |
222 | int max_sysfs_pct; | |
223 | int min_policy_pct; | |
224 | int min_sysfs_pct; | |
225 | }; | |
226 | ||
13ad7701 SP |
227 | /** |
228 | * struct cpudata - Per CPU instance data storage | |
229 | * @cpu: CPU number for this instance data | |
2f1d407a | 230 | * @policy: CPUFreq policy value |
13ad7701 | 231 | * @update_util: CPUFreq utility callback information |
4578ee7e | 232 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
233 | * @iowait_boost: iowait-related boost fraction |
234 | * @last_update: Time of the last update. | |
13ad7701 SP |
235 | * @pstate: Stores P state limits for this CPU |
236 | * @vid: Stores VID limits for this CPU | |
237 | * @pid: Stores PID parameters for this CPU | |
238 | * @last_sample_time: Last Sample time | |
239 | * @prev_aperf: Last APERF value read from APERF MSR | |
240 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
241 | * @prev_tsc: Last timestamp counter (TSC) value | |
242 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
243 | * current sample | |
244 | * @sample: Storage for storing last Sample data | |
eae48f04 SP |
245 | * @perf_limits: Pointer to perf_limit unique to this CPU |
246 | * Not all field in the structure are applicable | |
247 | * when per cpu controls are enforced | |
9522a2ff SP |
248 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
249 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
13ad7701 SP |
250 | * |
251 | * This structure stores per CPU instance data for all CPUs. | |
252 | */ | |
93f0822d DB |
253 | struct cpudata { |
254 | int cpu; | |
255 | ||
2f1d407a | 256 | unsigned int policy; |
a4675fbc | 257 | struct update_util_data update_util; |
4578ee7e | 258 | bool update_util_set; |
93f0822d | 259 | |
93f0822d | 260 | struct pstate_data pstate; |
007bea09 | 261 | struct vid_data vid; |
93f0822d | 262 | struct _pid pid; |
93f0822d | 263 | |
09c448d3 | 264 | u64 last_update; |
a4675fbc | 265 | u64 last_sample_time; |
93f0822d DB |
266 | u64 prev_aperf; |
267 | u64 prev_mperf; | |
4055fad3 | 268 | u64 prev_tsc; |
63d1d656 | 269 | u64 prev_cummulative_iowait; |
d37e2b76 | 270 | struct sample sample; |
eae48f04 | 271 | struct perf_limits *perf_limits; |
9522a2ff SP |
272 | #ifdef CONFIG_ACPI |
273 | struct acpi_processor_performance acpi_perf_data; | |
274 | bool valid_pss_table; | |
275 | #endif | |
09c448d3 | 276 | unsigned int iowait_boost; |
93f0822d DB |
277 | }; |
278 | ||
279 | static struct cpudata **all_cpu_data; | |
13ad7701 SP |
280 | |
281 | /** | |
3954517e | 282 | * struct pstate_adjust_policy - Stores static PID configuration data |
13ad7701 SP |
283 | * @sample_rate_ms: PID calculation sample rate in ms |
284 | * @sample_rate_ns: Sample rate calculation in ns | |
285 | * @deadband: PID deadband | |
286 | * @setpoint: PID Setpoint | |
287 | * @p_gain_pct: PID proportional gain | |
288 | * @i_gain_pct: PID integral gain | |
289 | * @d_gain_pct: PID derivative gain | |
290 | * | |
291 | * Stores per CPU model static PID configuration data. | |
292 | */ | |
93f0822d DB |
293 | struct pstate_adjust_policy { |
294 | int sample_rate_ms; | |
a4675fbc | 295 | s64 sample_rate_ns; |
93f0822d DB |
296 | int deadband; |
297 | int setpoint; | |
298 | int p_gain_pct; | |
299 | int d_gain_pct; | |
300 | int i_gain_pct; | |
301 | }; | |
302 | ||
13ad7701 SP |
303 | /** |
304 | * struct pstate_funcs - Per CPU model specific callbacks | |
305 | * @get_max: Callback to get maximum non turbo effective P state | |
306 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
307 | * @get_min: Callback to get minimum P state | |
308 | * @get_turbo: Callback to get turbo P state | |
309 | * @get_scaling: Callback to get frequency scaling factor | |
310 | * @get_val: Callback to convert P state to actual MSR write value | |
311 | * @get_vid: Callback to get VID data for Atom platforms | |
312 | * @get_target_pstate: Callback to a function to calculate next P state to use | |
313 | * | |
314 | * Core and Atom CPU models have different way to get P State limits. This | |
315 | * structure is used to store those callbacks. | |
316 | */ | |
016c8150 DB |
317 | struct pstate_funcs { |
318 | int (*get_max)(void); | |
3bcc6fa9 | 319 | int (*get_max_physical)(void); |
016c8150 DB |
320 | int (*get_min)(void); |
321 | int (*get_turbo)(void); | |
b27580b0 | 322 | int (*get_scaling)(void); |
fdfdb2b1 | 323 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 324 | void (*get_vid)(struct cpudata *); |
157386b6 | 325 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
326 | }; |
327 | ||
13ad7701 SP |
328 | /** |
329 | * struct cpu_defaults- Per CPU model default config data | |
330 | * @pid_policy: PID config data | |
331 | * @funcs: Callback function data | |
332 | */ | |
016c8150 DB |
333 | struct cpu_defaults { |
334 | struct pstate_adjust_policy pid_policy; | |
335 | struct pstate_funcs funcs; | |
93f0822d DB |
336 | }; |
337 | ||
157386b6 | 338 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
e70eed2b | 339 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); |
157386b6 | 340 | |
4a7cb7a9 JZ |
341 | static struct pstate_adjust_policy pid_params __read_mostly; |
342 | static struct pstate_funcs pstate_funcs __read_mostly; | |
343 | static int hwp_active __read_mostly; | |
eae48f04 | 344 | static bool per_cpu_limits __read_mostly; |
016c8150 | 345 | |
9522a2ff SP |
346 | #ifdef CONFIG_ACPI |
347 | static bool acpi_ppc; | |
348 | #endif | |
13ad7701 | 349 | |
51443fbf PB |
350 | static struct perf_limits performance_limits = { |
351 | .no_turbo = 0, | |
352 | .turbo_disabled = 0, | |
353 | .max_perf_pct = 100, | |
354 | .max_perf = int_tofp(1), | |
355 | .min_perf_pct = 100, | |
356 | .min_perf = int_tofp(1), | |
357 | .max_policy_pct = 100, | |
358 | .max_sysfs_pct = 100, | |
359 | .min_policy_pct = 0, | |
360 | .min_sysfs_pct = 0, | |
361 | }; | |
362 | ||
363 | static struct perf_limits powersave_limits = { | |
93f0822d | 364 | .no_turbo = 0, |
4521e1a0 | 365 | .turbo_disabled = 0, |
93f0822d DB |
366 | .max_perf_pct = 100, |
367 | .max_perf = int_tofp(1), | |
368 | .min_perf_pct = 0, | |
369 | .min_perf = 0, | |
d8f469e9 DB |
370 | .max_policy_pct = 100, |
371 | .max_sysfs_pct = 100, | |
a0475992 KCA |
372 | .min_policy_pct = 0, |
373 | .min_sysfs_pct = 0, | |
93f0822d DB |
374 | }; |
375 | ||
51443fbf PB |
376 | #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE |
377 | static struct perf_limits *limits = &performance_limits; | |
378 | #else | |
379 | static struct perf_limits *limits = &powersave_limits; | |
380 | #endif | |
381 | ||
a410c03d SP |
382 | static DEFINE_MUTEX(intel_pstate_limits_lock); |
383 | ||
9522a2ff | 384 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
385 | |
386 | static bool intel_pstate_get_ppc_enable_status(void) | |
387 | { | |
388 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
389 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
390 | return true; | |
391 | ||
392 | return acpi_ppc; | |
393 | } | |
394 | ||
9522a2ff SP |
395 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
396 | { | |
397 | struct cpudata *cpu; | |
9522a2ff SP |
398 | int ret; |
399 | int i; | |
400 | ||
e59a8f7f SP |
401 | if (hwp_active) |
402 | return; | |
403 | ||
2b3ec765 | 404 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
405 | return; |
406 | ||
407 | cpu = all_cpu_data[policy->cpu]; | |
408 | ||
409 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
410 | policy->cpu); | |
411 | if (ret) | |
412 | return; | |
413 | ||
414 | /* | |
415 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
416 | * guarantee that the states returned by it map to the states in our | |
417 | * list directly. | |
418 | */ | |
419 | if (cpu->acpi_perf_data.control_register.space_id != | |
420 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
421 | goto err; | |
422 | ||
423 | /* | |
424 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
425 | * usual without taking _PSS into account | |
426 | */ | |
427 | if (cpu->acpi_perf_data.state_count < 2) | |
428 | goto err; | |
429 | ||
430 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
431 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
432 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
433 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
434 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
435 | (u32) cpu->acpi_perf_data.states[i].power, | |
436 | (u32) cpu->acpi_perf_data.states[i].control); | |
437 | } | |
438 | ||
439 | /* | |
440 | * The _PSS table doesn't contain whole turbo frequency range. | |
441 | * This just contains +1 MHZ above the max non turbo frequency, | |
442 | * with control value corresponding to max turbo ratio. But | |
443 | * when cpufreq set policy is called, it will call with this | |
444 | * max frequency, which will cause a reduced performance as | |
445 | * this driver uses real max turbo frequency as the max | |
446 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 447 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
448 | * Also need to convert to MHz as _PSS freq is in MHz. |
449 | */ | |
b00345d1 | 450 | if (!limits->turbo_disabled) |
9522a2ff SP |
451 | cpu->acpi_perf_data.states[0].core_frequency = |
452 | policy->cpuinfo.max_freq / 1000; | |
453 | cpu->valid_pss_table = true; | |
6cacd115 | 454 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
455 | |
456 | return; | |
457 | ||
458 | err: | |
459 | cpu->valid_pss_table = false; | |
460 | acpi_processor_unregister_performance(policy->cpu); | |
461 | } | |
462 | ||
463 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
464 | { | |
465 | struct cpudata *cpu; | |
466 | ||
467 | cpu = all_cpu_data[policy->cpu]; | |
468 | if (!cpu->valid_pss_table) | |
469 | return; | |
470 | ||
471 | acpi_processor_unregister_performance(policy->cpu); | |
472 | } | |
473 | ||
474 | #else | |
475 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) | |
476 | { | |
477 | } | |
478 | ||
001c76f0 | 479 | static inline int intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
480 | { |
481 | } | |
482 | #endif | |
483 | ||
93f0822d | 484 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 485 | int deadband, int integral) { |
b54a0dfd PL |
486 | pid->setpoint = int_tofp(setpoint); |
487 | pid->deadband = int_tofp(deadband); | |
93f0822d | 488 | pid->integral = int_tofp(integral); |
d98d099b | 489 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
490 | } |
491 | ||
492 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
493 | { | |
22590efb | 494 | pid->p_gain = div_fp(percent, 100); |
93f0822d DB |
495 | } |
496 | ||
497 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
498 | { | |
22590efb | 499 | pid->i_gain = div_fp(percent, 100); |
93f0822d DB |
500 | } |
501 | ||
502 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
503 | { | |
22590efb | 504 | pid->d_gain = div_fp(percent, 100); |
93f0822d DB |
505 | } |
506 | ||
d253d2a5 | 507 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 508 | { |
d253d2a5 | 509 | signed int result; |
93f0822d DB |
510 | int32_t pterm, dterm, fp_error; |
511 | int32_t integral_limit; | |
512 | ||
b54a0dfd | 513 | fp_error = pid->setpoint - busy; |
93f0822d | 514 | |
b54a0dfd | 515 | if (abs(fp_error) <= pid->deadband) |
93f0822d DB |
516 | return 0; |
517 | ||
518 | pterm = mul_fp(pid->p_gain, fp_error); | |
519 | ||
520 | pid->integral += fp_error; | |
521 | ||
e0d4c8f8 KCA |
522 | /* |
523 | * We limit the integral here so that it will never | |
524 | * get higher than 30. This prevents it from becoming | |
525 | * too large an input over long periods of time and allows | |
526 | * it to get factored out sooner. | |
527 | * | |
528 | * The value of 30 was chosen through experimentation. | |
529 | */ | |
93f0822d DB |
530 | integral_limit = int_tofp(30); |
531 | if (pid->integral > integral_limit) | |
532 | pid->integral = integral_limit; | |
533 | if (pid->integral < -integral_limit) | |
534 | pid->integral = -integral_limit; | |
535 | ||
d253d2a5 BS |
536 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
537 | pid->last_err = fp_error; | |
93f0822d DB |
538 | |
539 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 540 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
541 | return (signed int)fp_toint(result); |
542 | } | |
543 | ||
544 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
545 | { | |
016c8150 DB |
546 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
547 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
548 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 549 | |
2d8d1f18 | 550 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
551 | } |
552 | ||
93f0822d DB |
553 | static inline void intel_pstate_reset_all_pid(void) |
554 | { | |
555 | unsigned int cpu; | |
845c1cbe | 556 | |
93f0822d DB |
557 | for_each_online_cpu(cpu) { |
558 | if (all_cpu_data[cpu]) | |
559 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
560 | } | |
561 | } | |
562 | ||
4521e1a0 GM |
563 | static inline void update_turbo_state(void) |
564 | { | |
565 | u64 misc_en; | |
566 | struct cpudata *cpu; | |
567 | ||
568 | cpu = all_cpu_data[0]; | |
569 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
51443fbf | 570 | limits->turbo_disabled = |
4521e1a0 GM |
571 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
572 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
573 | } | |
574 | ||
41cfd64c | 575 | static void intel_pstate_hwp_set(const struct cpumask *cpumask) |
2f86dc4c | 576 | { |
74da56ce | 577 | int min, hw_min, max, hw_max, cpu, range, adj_range; |
eae48f04 | 578 | struct perf_limits *perf_limits = limits; |
74da56ce KCA |
579 | u64 value, cap; |
580 | ||
41cfd64c | 581 | for_each_cpu(cpu, cpumask) { |
eae48f04 SP |
582 | int max_perf_pct, min_perf_pct; |
583 | ||
584 | if (per_cpu_limits) | |
585 | perf_limits = all_cpu_data[cpu]->perf_limits; | |
586 | ||
f9f4872d SP |
587 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
588 | hw_min = HWP_LOWEST_PERF(cap); | |
589 | hw_max = HWP_HIGHEST_PERF(cap); | |
590 | range = hw_max - hw_min; | |
591 | ||
eae48f04 SP |
592 | max_perf_pct = perf_limits->max_perf_pct; |
593 | min_perf_pct = perf_limits->min_perf_pct; | |
594 | ||
2f86dc4c | 595 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
eae48f04 | 596 | adj_range = min_perf_pct * range / 100; |
74da56ce | 597 | min = hw_min + adj_range; |
2f86dc4c DB |
598 | value &= ~HWP_MIN_PERF(~0L); |
599 | value |= HWP_MIN_PERF(min); | |
600 | ||
eae48f04 | 601 | adj_range = max_perf_pct * range / 100; |
74da56ce | 602 | max = hw_min + adj_range; |
51443fbf | 603 | if (limits->no_turbo) { |
74da56ce KCA |
604 | hw_max = HWP_GUARANTEED_PERF(cap); |
605 | if (hw_max < max) | |
606 | max = hw_max; | |
2f86dc4c DB |
607 | } |
608 | ||
609 | value &= ~HWP_MAX_PERF(~0L); | |
610 | value |= HWP_MAX_PERF(max); | |
611 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
612 | } | |
41cfd64c | 613 | } |
2f86dc4c | 614 | |
ba41e1bc RW |
615 | static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) |
616 | { | |
617 | if (hwp_active) | |
618 | intel_pstate_hwp_set(policy->cpus); | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
41cfd64c VK |
623 | static void intel_pstate_hwp_set_online_cpus(void) |
624 | { | |
625 | get_online_cpus(); | |
626 | intel_pstate_hwp_set(cpu_online_mask); | |
2f86dc4c DB |
627 | put_online_cpus(); |
628 | } | |
629 | ||
93f0822d DB |
630 | /************************** debugfs begin ************************/ |
631 | static int pid_param_set(void *data, u64 val) | |
632 | { | |
633 | *(u32 *)data = val; | |
634 | intel_pstate_reset_all_pid(); | |
635 | return 0; | |
636 | } | |
845c1cbe | 637 | |
93f0822d DB |
638 | static int pid_param_get(void *data, u64 *val) |
639 | { | |
640 | *val = *(u32 *)data; | |
641 | return 0; | |
642 | } | |
2d8d1f18 | 643 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
644 | |
645 | struct pid_param { | |
646 | char *name; | |
647 | void *value; | |
648 | }; | |
649 | ||
650 | static struct pid_param pid_files[] = { | |
016c8150 DB |
651 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
652 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
653 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
654 | {"deadband", &pid_params.deadband}, | |
655 | {"setpoint", &pid_params.setpoint}, | |
656 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
657 | {NULL, NULL} |
658 | }; | |
659 | ||
317dd50e | 660 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 661 | { |
317dd50e | 662 | struct dentry *debugfs_parent; |
93f0822d DB |
663 | int i = 0; |
664 | ||
185d8245 SP |
665 | if (hwp_active || |
666 | pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) | |
2f86dc4c | 667 | return; |
185d8245 | 668 | |
93f0822d DB |
669 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
670 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
671 | return; | |
672 | while (pid_files[i].name) { | |
673 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
674 | debugfs_parent, pid_files[i].value, |
675 | &fops_pid_param); | |
93f0822d DB |
676 | i++; |
677 | } | |
678 | } | |
679 | ||
680 | /************************** debugfs end ************************/ | |
681 | ||
682 | /************************** sysfs begin ************************/ | |
683 | #define show_one(file_name, object) \ | |
684 | static ssize_t show_##file_name \ | |
685 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
686 | { \ | |
51443fbf | 687 | return sprintf(buf, "%u\n", limits->object); \ |
93f0822d DB |
688 | } |
689 | ||
d01b1f48 KCA |
690 | static ssize_t show_turbo_pct(struct kobject *kobj, |
691 | struct attribute *attr, char *buf) | |
692 | { | |
693 | struct cpudata *cpu; | |
694 | int total, no_turbo, turbo_pct; | |
695 | uint32_t turbo_fp; | |
696 | ||
697 | cpu = all_cpu_data[0]; | |
698 | ||
699 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
700 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 701 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 KCA |
702 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
703 | return sprintf(buf, "%u\n", turbo_pct); | |
704 | } | |
705 | ||
0522424e KCA |
706 | static ssize_t show_num_pstates(struct kobject *kobj, |
707 | struct attribute *attr, char *buf) | |
708 | { | |
709 | struct cpudata *cpu; | |
710 | int total; | |
711 | ||
712 | cpu = all_cpu_data[0]; | |
713 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
714 | return sprintf(buf, "%u\n", total); | |
715 | } | |
716 | ||
4521e1a0 GM |
717 | static ssize_t show_no_turbo(struct kobject *kobj, |
718 | struct attribute *attr, char *buf) | |
719 | { | |
720 | ssize_t ret; | |
721 | ||
722 | update_turbo_state(); | |
51443fbf PB |
723 | if (limits->turbo_disabled) |
724 | ret = sprintf(buf, "%u\n", limits->turbo_disabled); | |
4521e1a0 | 725 | else |
51443fbf | 726 | ret = sprintf(buf, "%u\n", limits->no_turbo); |
4521e1a0 GM |
727 | |
728 | return ret; | |
729 | } | |
730 | ||
93f0822d | 731 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 732 | const char *buf, size_t count) |
93f0822d DB |
733 | { |
734 | unsigned int input; | |
735 | int ret; | |
845c1cbe | 736 | |
93f0822d DB |
737 | ret = sscanf(buf, "%u", &input); |
738 | if (ret != 1) | |
739 | return -EINVAL; | |
4521e1a0 | 740 | |
a410c03d SP |
741 | mutex_lock(&intel_pstate_limits_lock); |
742 | ||
4521e1a0 | 743 | update_turbo_state(); |
51443fbf | 744 | if (limits->turbo_disabled) { |
4836df17 | 745 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
a410c03d | 746 | mutex_unlock(&intel_pstate_limits_lock); |
4521e1a0 | 747 | return -EPERM; |
dd5fbf70 | 748 | } |
2f86dc4c | 749 | |
51443fbf | 750 | limits->no_turbo = clamp_t(int, input, 0, 1); |
4521e1a0 | 751 | |
a410c03d SP |
752 | mutex_unlock(&intel_pstate_limits_lock); |
753 | ||
2f86dc4c | 754 | if (hwp_active) |
41cfd64c | 755 | intel_pstate_hwp_set_online_cpus(); |
2f86dc4c | 756 | |
93f0822d DB |
757 | return count; |
758 | } | |
759 | ||
760 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 761 | const char *buf, size_t count) |
93f0822d DB |
762 | { |
763 | unsigned int input; | |
764 | int ret; | |
845c1cbe | 765 | |
93f0822d DB |
766 | ret = sscanf(buf, "%u", &input); |
767 | if (ret != 1) | |
768 | return -EINVAL; | |
769 | ||
a410c03d SP |
770 | mutex_lock(&intel_pstate_limits_lock); |
771 | ||
51443fbf PB |
772 | limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); |
773 | limits->max_perf_pct = min(limits->max_policy_pct, | |
774 | limits->max_sysfs_pct); | |
775 | limits->max_perf_pct = max(limits->min_policy_pct, | |
776 | limits->max_perf_pct); | |
777 | limits->max_perf_pct = max(limits->min_perf_pct, | |
778 | limits->max_perf_pct); | |
22590efb | 779 | limits->max_perf = div_fp(limits->max_perf_pct, 100); |
845c1cbe | 780 | |
a410c03d SP |
781 | mutex_unlock(&intel_pstate_limits_lock); |
782 | ||
2f86dc4c | 783 | if (hwp_active) |
41cfd64c | 784 | intel_pstate_hwp_set_online_cpus(); |
93f0822d DB |
785 | return count; |
786 | } | |
787 | ||
788 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 789 | const char *buf, size_t count) |
93f0822d DB |
790 | { |
791 | unsigned int input; | |
792 | int ret; | |
845c1cbe | 793 | |
93f0822d DB |
794 | ret = sscanf(buf, "%u", &input); |
795 | if (ret != 1) | |
796 | return -EINVAL; | |
a0475992 | 797 | |
a410c03d SP |
798 | mutex_lock(&intel_pstate_limits_lock); |
799 | ||
51443fbf PB |
800 | limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); |
801 | limits->min_perf_pct = max(limits->min_policy_pct, | |
802 | limits->min_sysfs_pct); | |
803 | limits->min_perf_pct = min(limits->max_policy_pct, | |
804 | limits->min_perf_pct); | |
805 | limits->min_perf_pct = min(limits->max_perf_pct, | |
806 | limits->min_perf_pct); | |
22590efb | 807 | limits->min_perf = div_fp(limits->min_perf_pct, 100); |
93f0822d | 808 | |
a410c03d SP |
809 | mutex_unlock(&intel_pstate_limits_lock); |
810 | ||
2f86dc4c | 811 | if (hwp_active) |
41cfd64c | 812 | intel_pstate_hwp_set_online_cpus(); |
93f0822d DB |
813 | return count; |
814 | } | |
815 | ||
93f0822d DB |
816 | show_one(max_perf_pct, max_perf_pct); |
817 | show_one(min_perf_pct, min_perf_pct); | |
818 | ||
819 | define_one_global_rw(no_turbo); | |
820 | define_one_global_rw(max_perf_pct); | |
821 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 822 | define_one_global_ro(turbo_pct); |
0522424e | 823 | define_one_global_ro(num_pstates); |
93f0822d DB |
824 | |
825 | static struct attribute *intel_pstate_attributes[] = { | |
826 | &no_turbo.attr, | |
d01b1f48 | 827 | &turbo_pct.attr, |
0522424e | 828 | &num_pstates.attr, |
93f0822d DB |
829 | NULL |
830 | }; | |
831 | ||
832 | static struct attribute_group intel_pstate_attr_group = { | |
833 | .attrs = intel_pstate_attributes, | |
834 | }; | |
93f0822d | 835 | |
317dd50e | 836 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 837 | { |
317dd50e | 838 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
839 | int rc; |
840 | ||
841 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
842 | &cpu_subsys.dev_root->kobj); | |
eae48f04 SP |
843 | if (WARN_ON(!intel_pstate_kobject)) |
844 | return; | |
845 | ||
2d8d1f18 | 846 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
eae48f04 SP |
847 | if (WARN_ON(rc)) |
848 | return; | |
849 | ||
850 | /* | |
851 | * If per cpu limits are enforced there are no global limits, so | |
852 | * return without creating max/min_perf_pct attributes | |
853 | */ | |
854 | if (per_cpu_limits) | |
855 | return; | |
856 | ||
857 | rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); | |
858 | WARN_ON(rc); | |
859 | ||
860 | rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); | |
861 | WARN_ON(rc); | |
862 | ||
93f0822d | 863 | } |
93f0822d | 864 | /************************** sysfs end ************************/ |
2f86dc4c | 865 | |
ba88d433 | 866 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 867 | { |
f05c9665 | 868 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
869 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
870 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 871 | |
ba88d433 | 872 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
873 | } |
874 | ||
938d21a2 | 875 | static int atom_get_min_pstate(void) |
19e77c28 DB |
876 | { |
877 | u64 value; | |
845c1cbe | 878 | |
938d21a2 | 879 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 880 | return (value >> 8) & 0x7F; |
19e77c28 DB |
881 | } |
882 | ||
938d21a2 | 883 | static int atom_get_max_pstate(void) |
19e77c28 DB |
884 | { |
885 | u64 value; | |
845c1cbe | 886 | |
938d21a2 | 887 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 888 | return (value >> 16) & 0x7F; |
19e77c28 | 889 | } |
93f0822d | 890 | |
938d21a2 | 891 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
892 | { |
893 | u64 value; | |
845c1cbe | 894 | |
938d21a2 | 895 | rdmsrl(ATOM_TURBO_RATIOS, value); |
c16ed060 | 896 | return value & 0x7F; |
61d8d2ab DB |
897 | } |
898 | ||
fdfdb2b1 | 899 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
900 | { |
901 | u64 val; | |
902 | int32_t vid_fp; | |
903 | u32 vid; | |
904 | ||
144c8e17 | 905 | val = (u64)pstate << 8; |
51443fbf | 906 | if (limits->no_turbo && !limits->turbo_disabled) |
007bea09 DB |
907 | val |= (u64)1 << 32; |
908 | ||
909 | vid_fp = cpudata->vid.min + mul_fp( | |
910 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
911 | cpudata->vid.ratio); | |
912 | ||
913 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 914 | vid = ceiling_fp(vid_fp); |
007bea09 | 915 | |
21855ff5 DB |
916 | if (pstate > cpudata->pstate.max_pstate) |
917 | vid = cpudata->vid.turbo; | |
918 | ||
fdfdb2b1 | 919 | return val | vid; |
007bea09 DB |
920 | } |
921 | ||
1421df63 | 922 | static int silvermont_get_scaling(void) |
b27580b0 DB |
923 | { |
924 | u64 value; | |
925 | int i; | |
1421df63 PL |
926 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
927 | static int silvermont_freq_table[] = { | |
928 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
929 | |
930 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
931 | i = value & 0x7; |
932 | WARN_ON(i > 4); | |
b27580b0 | 933 | |
1421df63 PL |
934 | return silvermont_freq_table[i]; |
935 | } | |
b27580b0 | 936 | |
1421df63 PL |
937 | static int airmont_get_scaling(void) |
938 | { | |
939 | u64 value; | |
940 | int i; | |
941 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
942 | static int airmont_freq_table[] = { | |
943 | 83300, 100000, 133300, 116700, 80000, | |
944 | 93300, 90000, 88900, 87500}; | |
945 | ||
946 | rdmsrl(MSR_FSB_FREQ, value); | |
947 | i = value & 0xF; | |
948 | WARN_ON(i > 8); | |
949 | ||
950 | return airmont_freq_table[i]; | |
b27580b0 DB |
951 | } |
952 | ||
938d21a2 | 953 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
954 | { |
955 | u64 value; | |
956 | ||
938d21a2 | 957 | rdmsrl(ATOM_VIDS, value); |
c16ed060 DB |
958 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
959 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
960 | cpudata->vid.ratio = div_fp( |
961 | cpudata->vid.max - cpudata->vid.min, | |
962 | int_tofp(cpudata->pstate.max_pstate - | |
963 | cpudata->pstate.min_pstate)); | |
21855ff5 | 964 | |
938d21a2 | 965 | rdmsrl(ATOM_TURBO_VIDS, value); |
21855ff5 | 966 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
967 | } |
968 | ||
016c8150 | 969 | static int core_get_min_pstate(void) |
93f0822d DB |
970 | { |
971 | u64 value; | |
845c1cbe | 972 | |
05e99c8c | 973 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
974 | return (value >> 40) & 0xFF; |
975 | } | |
976 | ||
3bcc6fa9 | 977 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
978 | { |
979 | u64 value; | |
845c1cbe | 980 | |
05e99c8c | 981 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
982 | return (value >> 8) & 0xFF; |
983 | } | |
984 | ||
016c8150 | 985 | static int core_get_max_pstate(void) |
93f0822d | 986 | { |
6a35fc2d SP |
987 | u64 tar; |
988 | u64 plat_info; | |
989 | int max_pstate; | |
990 | int err; | |
991 | ||
992 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
993 | max_pstate = (plat_info >> 8) & 0xFF; | |
994 | ||
995 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); | |
996 | if (!err) { | |
997 | /* Do some sanity checking for safety */ | |
998 | if (plat_info & 0x600000000) { | |
999 | u64 tdp_ctrl; | |
1000 | u64 tdp_ratio; | |
1001 | int tdp_msr; | |
1002 | ||
1003 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
1004 | if (err) | |
1005 | goto skip_tar; | |
1006 | ||
5fc8f707 | 1007 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3); |
6a35fc2d SP |
1008 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); |
1009 | if (err) | |
1010 | goto skip_tar; | |
1011 | ||
1becf035 SP |
1012 | /* For level 1 and 2, bits[23:16] contain the ratio */ |
1013 | if (tdp_ctrl) | |
1014 | tdp_ratio >>= 16; | |
1015 | ||
1016 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
6a35fc2d SP |
1017 | if (tdp_ratio - 1 == tar) { |
1018 | max_pstate = tar; | |
1019 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
1020 | } else { | |
1021 | goto skip_tar; | |
1022 | } | |
1023 | } | |
1024 | } | |
845c1cbe | 1025 | |
6a35fc2d SP |
1026 | skip_tar: |
1027 | return max_pstate; | |
93f0822d DB |
1028 | } |
1029 | ||
016c8150 | 1030 | static int core_get_turbo_pstate(void) |
93f0822d DB |
1031 | { |
1032 | u64 value; | |
1033 | int nont, ret; | |
845c1cbe | 1034 | |
100cf6f2 | 1035 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 1036 | nont = core_get_max_pstate(); |
285cb990 | 1037 | ret = (value) & 255; |
93f0822d DB |
1038 | if (ret <= nont) |
1039 | ret = nont; | |
1040 | return ret; | |
1041 | } | |
1042 | ||
b27580b0 DB |
1043 | static inline int core_get_scaling(void) |
1044 | { | |
1045 | return 100000; | |
1046 | } | |
1047 | ||
fdfdb2b1 | 1048 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
1049 | { |
1050 | u64 val; | |
1051 | ||
144c8e17 | 1052 | val = (u64)pstate << 8; |
51443fbf | 1053 | if (limits->no_turbo && !limits->turbo_disabled) |
016c8150 DB |
1054 | val |= (u64)1 << 32; |
1055 | ||
fdfdb2b1 | 1056 | return val; |
016c8150 DB |
1057 | } |
1058 | ||
b34ef932 DC |
1059 | static int knl_get_turbo_pstate(void) |
1060 | { | |
1061 | u64 value; | |
1062 | int nont, ret; | |
1063 | ||
100cf6f2 | 1064 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1065 | nont = core_get_max_pstate(); |
1066 | ret = (((value) >> 8) & 0xFF); | |
1067 | if (ret <= nont) | |
1068 | ret = nont; | |
1069 | return ret; | |
1070 | } | |
1071 | ||
016c8150 DB |
1072 | static struct cpu_defaults core_params = { |
1073 | .pid_policy = { | |
1074 | .sample_rate_ms = 10, | |
1075 | .deadband = 0, | |
1076 | .setpoint = 97, | |
1077 | .p_gain_pct = 20, | |
1078 | .d_gain_pct = 0, | |
1079 | .i_gain_pct = 0, | |
1080 | }, | |
1081 | .funcs = { | |
1082 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1083 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
1084 | .get_min = core_get_min_pstate, |
1085 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 1086 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1087 | .get_val = core_get_val, |
157386b6 | 1088 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
1089 | }, |
1090 | }; | |
1091 | ||
42ce8921 | 1092 | static const struct cpu_defaults silvermont_params = { |
1421df63 PL |
1093 | .pid_policy = { |
1094 | .sample_rate_ms = 10, | |
1095 | .deadband = 0, | |
1096 | .setpoint = 60, | |
1097 | .p_gain_pct = 14, | |
1098 | .d_gain_pct = 0, | |
1099 | .i_gain_pct = 4, | |
1100 | }, | |
1101 | .funcs = { | |
1102 | .get_max = atom_get_max_pstate, | |
1103 | .get_max_physical = atom_get_max_pstate, | |
1104 | .get_min = atom_get_min_pstate, | |
1105 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1106 | .get_val = atom_get_val, |
1421df63 PL |
1107 | .get_scaling = silvermont_get_scaling, |
1108 | .get_vid = atom_get_vid, | |
e70eed2b | 1109 | .get_target_pstate = get_target_pstate_use_cpu_load, |
1421df63 PL |
1110 | }, |
1111 | }; | |
1112 | ||
42ce8921 | 1113 | static const struct cpu_defaults airmont_params = { |
19e77c28 DB |
1114 | .pid_policy = { |
1115 | .sample_rate_ms = 10, | |
1116 | .deadband = 0, | |
6a82ba6d | 1117 | .setpoint = 60, |
19e77c28 DB |
1118 | .p_gain_pct = 14, |
1119 | .d_gain_pct = 0, | |
1120 | .i_gain_pct = 4, | |
1121 | }, | |
1122 | .funcs = { | |
938d21a2 PL |
1123 | .get_max = atom_get_max_pstate, |
1124 | .get_max_physical = atom_get_max_pstate, | |
1125 | .get_min = atom_get_min_pstate, | |
1126 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1127 | .get_val = atom_get_val, |
1421df63 | 1128 | .get_scaling = airmont_get_scaling, |
938d21a2 | 1129 | .get_vid = atom_get_vid, |
e70eed2b | 1130 | .get_target_pstate = get_target_pstate_use_cpu_load, |
19e77c28 DB |
1131 | }, |
1132 | }; | |
1133 | ||
42ce8921 | 1134 | static const struct cpu_defaults knl_params = { |
b34ef932 DC |
1135 | .pid_policy = { |
1136 | .sample_rate_ms = 10, | |
1137 | .deadband = 0, | |
1138 | .setpoint = 97, | |
1139 | .p_gain_pct = 20, | |
1140 | .d_gain_pct = 0, | |
1141 | .i_gain_pct = 0, | |
1142 | }, | |
1143 | .funcs = { | |
1144 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1145 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
1146 | .get_min = core_get_min_pstate, |
1147 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 1148 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1149 | .get_val = core_get_val, |
157386b6 | 1150 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
1151 | }, |
1152 | }; | |
1153 | ||
42ce8921 | 1154 | static const struct cpu_defaults bxt_params = { |
41bad47f SP |
1155 | .pid_policy = { |
1156 | .sample_rate_ms = 10, | |
1157 | .deadband = 0, | |
1158 | .setpoint = 60, | |
1159 | .p_gain_pct = 14, | |
1160 | .d_gain_pct = 0, | |
1161 | .i_gain_pct = 4, | |
1162 | }, | |
1163 | .funcs = { | |
1164 | .get_max = core_get_max_pstate, | |
1165 | .get_max_physical = core_get_max_pstate_physical, | |
1166 | .get_min = core_get_min_pstate, | |
1167 | .get_turbo = core_get_turbo_pstate, | |
1168 | .get_scaling = core_get_scaling, | |
1169 | .get_val = core_get_val, | |
1170 | .get_target_pstate = get_target_pstate_use_cpu_load, | |
1171 | }, | |
1172 | }; | |
1173 | ||
93f0822d DB |
1174 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
1175 | { | |
1176 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 1177 | int max_perf_adj; |
93f0822d | 1178 | int min_perf; |
eae48f04 | 1179 | struct perf_limits *perf_limits = limits; |
845c1cbe | 1180 | |
51443fbf | 1181 | if (limits->no_turbo || limits->turbo_disabled) |
93f0822d DB |
1182 | max_perf = cpu->pstate.max_pstate; |
1183 | ||
eae48f04 SP |
1184 | if (per_cpu_limits) |
1185 | perf_limits = cpu->perf_limits; | |
1186 | ||
e0d4c8f8 KCA |
1187 | /* |
1188 | * performance can be limited by user through sysfs, by cpufreq | |
1189 | * policy, or by cpu specific default values determined through | |
1190 | * experimentation. | |
1191 | */ | |
eae48f04 | 1192 | max_perf_adj = fp_toint(max_perf * perf_limits->max_perf); |
799281a3 RW |
1193 | *max = clamp_t(int, max_perf_adj, |
1194 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 1195 | |
eae48f04 | 1196 | min_perf = fp_toint(max_perf * perf_limits->min_perf); |
799281a3 | 1197 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
1198 | } |
1199 | ||
a6c6ead1 | 1200 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1201 | { |
bc95a454 RW |
1202 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1203 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1204 | /* |
1205 | * Generally, there is no guarantee that this code will always run on | |
1206 | * the CPU being updated, so force the register update to run on the | |
1207 | * right CPU. | |
1208 | */ | |
1209 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1210 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1211 | } |
1212 | ||
a6c6ead1 RW |
1213 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1214 | { | |
1215 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); | |
1216 | } | |
1217 | ||
1218 | static void intel_pstate_max_within_limits(struct cpudata *cpu) | |
1219 | { | |
1220 | int min_pstate, max_pstate; | |
1221 | ||
1222 | update_turbo_state(); | |
1223 | intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); | |
1224 | intel_pstate_set_pstate(cpu, max_pstate); | |
1225 | } | |
1226 | ||
93f0822d DB |
1227 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1228 | { | |
016c8150 DB |
1229 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1230 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1231 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1232 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1233 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
001c76f0 RW |
1234 | cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; |
1235 | cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d | 1236 | |
007bea09 DB |
1237 | if (pstate_funcs.get_vid) |
1238 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1239 | |
1240 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1241 | } |
1242 | ||
a1c9787d | 1243 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1244 | { |
6b17ddb2 | 1245 | struct sample *sample = &cpu->sample; |
e66c1768 | 1246 | |
a1c9787d | 1247 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1248 | } |
1249 | ||
4fec7ad5 | 1250 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1251 | { |
93f0822d | 1252 | u64 aperf, mperf; |
4ab60c3f | 1253 | unsigned long flags; |
4055fad3 | 1254 | u64 tsc; |
93f0822d | 1255 | |
4ab60c3f | 1256 | local_irq_save(flags); |
93f0822d DB |
1257 | rdmsrl(MSR_IA32_APERF, aperf); |
1258 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1259 | tsc = rdtsc(); |
4fec7ad5 | 1260 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1261 | local_irq_restore(flags); |
4fec7ad5 | 1262 | return false; |
8e601a9f | 1263 | } |
4ab60c3f | 1264 | local_irq_restore(flags); |
b69880f9 | 1265 | |
c4ee841f | 1266 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1267 | cpu->sample.time = time; |
d37e2b76 DB |
1268 | cpu->sample.aperf = aperf; |
1269 | cpu->sample.mperf = mperf; | |
4055fad3 | 1270 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1271 | cpu->sample.aperf -= cpu->prev_aperf; |
1272 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1273 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1274 | |
93f0822d DB |
1275 | cpu->prev_aperf = aperf; |
1276 | cpu->prev_mperf = mperf; | |
4055fad3 | 1277 | cpu->prev_tsc = tsc; |
febce40f RW |
1278 | /* |
1279 | * First time this function is invoked in a given cycle, all of the | |
1280 | * previous sample data fields are equal to zero or stale and they must | |
1281 | * be populated with meaningful numbers for things to work, so assume | |
1282 | * that sample.time will always be reset before setting the utilization | |
1283 | * update hook and make the caller skip the sample then. | |
1284 | */ | |
1285 | return !!cpu->last_sample_time; | |
93f0822d DB |
1286 | } |
1287 | ||
8fa520af PL |
1288 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1289 | { | |
a1c9787d RW |
1290 | return mul_ext_fp(cpu->sample.core_avg_perf, |
1291 | cpu->pstate.max_pstate_physical * cpu->pstate.scaling); | |
8fa520af PL |
1292 | } |
1293 | ||
bdcaa23f PL |
1294 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1295 | { | |
8edb0a6e RW |
1296 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1297 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1298 | } |
1299 | ||
e70eed2b PL |
1300 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
1301 | { | |
1302 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1303 | int32_t busy_frac, boost; |
0843e83c | 1304 | int target, avg_pstate; |
e70eed2b | 1305 | |
09c448d3 | 1306 | busy_frac = div_fp(sample->mperf, sample->tsc); |
63d1d656 | 1307 | |
09c448d3 RW |
1308 | boost = cpu->iowait_boost; |
1309 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1310 | |
09c448d3 RW |
1311 | if (busy_frac < boost) |
1312 | busy_frac = boost; | |
63d1d656 | 1313 | |
09c448d3 | 1314 | sample->busy_scaled = busy_frac * 100; |
0843e83c RW |
1315 | |
1316 | target = limits->no_turbo || limits->turbo_disabled ? | |
1317 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; | |
1318 | target += target >> 2; | |
1319 | target = mul_fp(target, busy_frac); | |
1320 | if (target < cpu->pstate.min_pstate) | |
1321 | target = cpu->pstate.min_pstate; | |
1322 | ||
1323 | /* | |
1324 | * If the average P-state during the previous cycle was higher than the | |
1325 | * current target, add 50% of the difference to the target to reduce | |
1326 | * possible performance oscillations and offset possible performance | |
1327 | * loss related to moving the workload from one CPU to another within | |
1328 | * a package/module. | |
1329 | */ | |
1330 | avg_pstate = get_avg_pstate(cpu); | |
1331 | if (avg_pstate > target) | |
1332 | target += (avg_pstate - target) >> 1; | |
1333 | ||
1334 | return target; | |
e70eed2b PL |
1335 | } |
1336 | ||
157386b6 | 1337 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 1338 | { |
1aa7a6e2 | 1339 | int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; |
a4675fbc | 1340 | u64 duration_ns; |
93f0822d | 1341 | |
e0d4c8f8 | 1342 | /* |
f00593a4 RW |
1343 | * perf_scaled is the ratio of the average P-state during the last |
1344 | * sampling period to the P-state requested last time (in percent). | |
1345 | * | |
1346 | * That measures the system's response to the previous P-state | |
1347 | * selection. | |
e0d4c8f8 | 1348 | */ |
22590efb RW |
1349 | max_pstate = cpu->pstate.max_pstate_physical; |
1350 | current_pstate = cpu->pstate.current_pstate; | |
1aa7a6e2 | 1351 | perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, |
a1c9787d | 1352 | div_fp(100 * max_pstate, current_pstate)); |
c4ee841f | 1353 | |
e0d4c8f8 | 1354 | /* |
a4675fbc RW |
1355 | * Since our utilization update callback will not run unless we are |
1356 | * in C0, check if the actual elapsed time is significantly greater (3x) | |
1357 | * than our sample interval. If it is, then we were idle for a long | |
1aa7a6e2 | 1358 | * enough period of time to adjust our performance metric. |
e0d4c8f8 | 1359 | */ |
a4675fbc | 1360 | duration_ns = cpu->sample.time - cpu->last_sample_time; |
febce40f | 1361 | if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { |
22590efb | 1362 | sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); |
1aa7a6e2 | 1363 | perf_scaled = mul_fp(perf_scaled, sample_ratio); |
ffb81056 RW |
1364 | } else { |
1365 | sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); | |
1366 | if (sample_ratio < int_tofp(1)) | |
1aa7a6e2 | 1367 | perf_scaled = 0; |
c4ee841f DB |
1368 | } |
1369 | ||
1aa7a6e2 RW |
1370 | cpu->sample.busy_scaled = perf_scaled; |
1371 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); | |
93f0822d DB |
1372 | } |
1373 | ||
001c76f0 | 1374 | static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) |
fdfdb2b1 RW |
1375 | { |
1376 | int max_perf, min_perf; | |
1377 | ||
fdfdb2b1 RW |
1378 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
1379 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
bc95a454 | 1380 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
001c76f0 RW |
1381 | return pstate; |
1382 | } | |
1383 | ||
1384 | static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) | |
1385 | { | |
1386 | pstate = intel_pstate_prepare_request(cpu, pstate); | |
fdfdb2b1 RW |
1387 | if (pstate == cpu->pstate.current_pstate) |
1388 | return; | |
1389 | ||
bc95a454 | 1390 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1391 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1392 | } | |
1393 | ||
93f0822d DB |
1394 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) |
1395 | { | |
157386b6 | 1396 | int from, target_pstate; |
4055fad3 DS |
1397 | struct sample *sample; |
1398 | ||
1399 | from = cpu->pstate.current_pstate; | |
93f0822d | 1400 | |
2f1d407a RW |
1401 | target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ? |
1402 | cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu); | |
93f0822d | 1403 | |
001c76f0 RW |
1404 | update_turbo_state(); |
1405 | ||
fdfdb2b1 | 1406 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1407 | |
1408 | sample = &cpu->sample; | |
a1c9787d | 1409 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1410 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1411 | from, |
1412 | cpu->pstate.current_pstate, | |
1413 | sample->mperf, | |
1414 | sample->aperf, | |
1415 | sample->tsc, | |
3ba7bcaa SP |
1416 | get_avg_frequency(cpu), |
1417 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1418 | } |
1419 | ||
a4675fbc | 1420 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1421 | unsigned int flags) |
93f0822d | 1422 | { |
a4675fbc | 1423 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1424 | u64 delta_ns; |
1425 | ||
1d29815e | 1426 | if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) { |
09c448d3 RW |
1427 | if (flags & SCHED_CPUFREQ_IOWAIT) { |
1428 | cpu->iowait_boost = int_tofp(1); | |
1429 | } else if (cpu->iowait_boost) { | |
1430 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1431 | delta_ns = time - cpu->last_update; | |
1432 | if (delta_ns > TICK_NSEC) | |
1433 | cpu->iowait_boost = 0; | |
1434 | } | |
1435 | cpu->last_update = time; | |
1436 | } | |
b69880f9 | 1437 | |
09c448d3 | 1438 | delta_ns = time - cpu->sample.time; |
a4675fbc | 1439 | if ((s64)delta_ns >= pid_params.sample_rate_ns) { |
4fec7ad5 RW |
1440 | bool sample_taken = intel_pstate_sample(cpu, time); |
1441 | ||
6d45b719 | 1442 | if (sample_taken) { |
a1c9787d | 1443 | intel_pstate_calc_avg_perf(cpu); |
6d45b719 RW |
1444 | if (!hwp_active) |
1445 | intel_pstate_adjust_busy_pstate(cpu); | |
1446 | } | |
a4675fbc | 1447 | } |
93f0822d DB |
1448 | } |
1449 | ||
1450 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1451 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1452 | (unsigned long)&policy } | |
93f0822d DB |
1453 | |
1454 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
5b20c944 DH |
1455 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), |
1456 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), | |
1457 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), | |
1458 | ICPU(INTEL_FAM6_IVYBRIDGE, core_params), | |
1459 | ICPU(INTEL_FAM6_HASWELL_CORE, core_params), | |
1460 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), | |
1461 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), | |
1462 | ICPU(INTEL_FAM6_HASWELL_X, core_params), | |
1463 | ICPU(INTEL_FAM6_HASWELL_ULT, core_params), | |
1464 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), | |
1465 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), | |
1466 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), | |
1467 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), | |
1468 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), | |
1469 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), | |
1470 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), | |
1471 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), | |
41bad47f | 1472 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), |
93f0822d DB |
1473 | {} |
1474 | }; | |
1475 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1476 | ||
29327c84 | 1477 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
5b20c944 | 1478 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), |
65c1262f SP |
1479 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), |
1480 | ICPU(INTEL_FAM6_SKYLAKE_X, core_params), | |
2f86dc4c DB |
1481 | {} |
1482 | }; | |
1483 | ||
93f0822d DB |
1484 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1485 | { | |
93f0822d DB |
1486 | struct cpudata *cpu; |
1487 | ||
eae48f04 SP |
1488 | cpu = all_cpu_data[cpunum]; |
1489 | ||
1490 | if (!cpu) { | |
1491 | unsigned int size = sizeof(struct cpudata); | |
1492 | ||
1493 | if (per_cpu_limits) | |
1494 | size += sizeof(struct perf_limits); | |
1495 | ||
1496 | cpu = kzalloc(size, GFP_KERNEL); | |
1497 | if (!cpu) | |
1498 | return -ENOMEM; | |
1499 | ||
1500 | all_cpu_data[cpunum] = cpu; | |
1501 | if (per_cpu_limits) | |
1502 | cpu->perf_limits = (struct perf_limits *)(cpu + 1); | |
1503 | ||
1504 | } | |
93f0822d DB |
1505 | |
1506 | cpu = all_cpu_data[cpunum]; | |
1507 | ||
93f0822d | 1508 | cpu->cpu = cpunum; |
ba88d433 | 1509 | |
a4675fbc | 1510 | if (hwp_active) { |
ba88d433 | 1511 | intel_pstate_hwp_enable(cpu); |
a4675fbc RW |
1512 | pid_params.sample_rate_ms = 50; |
1513 | pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; | |
1514 | } | |
ba88d433 | 1515 | |
179e8471 | 1516 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1517 | |
93f0822d | 1518 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 1519 | |
4836df17 | 1520 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
1521 | |
1522 | return 0; | |
1523 | } | |
1524 | ||
1525 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1526 | { | |
f96fd0c8 | 1527 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
93f0822d | 1528 | |
f96fd0c8 | 1529 | return cpu ? get_avg_frequency(cpu) : 0; |
93f0822d DB |
1530 | } |
1531 | ||
febce40f | 1532 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1533 | { |
febce40f RW |
1534 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1535 | ||
5ab666e0 RW |
1536 | if (cpu->update_util_set) |
1537 | return; | |
1538 | ||
febce40f RW |
1539 | /* Prevent intel_pstate_update_util() from using stale data. */ |
1540 | cpu->sample.time = 0; | |
0bed612b RW |
1541 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
1542 | intel_pstate_update_util); | |
4578ee7e | 1543 | cpu->update_util_set = true; |
bb6ab52f RW |
1544 | } |
1545 | ||
1546 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1547 | { | |
4578ee7e CY |
1548 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
1549 | ||
1550 | if (!cpu_data->update_util_set) | |
1551 | return; | |
1552 | ||
0bed612b | 1553 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 1554 | cpu_data->update_util_set = false; |
bb6ab52f RW |
1555 | synchronize_sched(); |
1556 | } | |
1557 | ||
30a39153 SP |
1558 | static void intel_pstate_set_performance_limits(struct perf_limits *limits) |
1559 | { | |
a410c03d | 1560 | mutex_lock(&intel_pstate_limits_lock); |
30a39153 SP |
1561 | limits->no_turbo = 0; |
1562 | limits->turbo_disabled = 0; | |
1563 | limits->max_perf_pct = 100; | |
1564 | limits->max_perf = int_tofp(1); | |
1565 | limits->min_perf_pct = 100; | |
1566 | limits->min_perf = int_tofp(1); | |
1567 | limits->max_policy_pct = 100; | |
1568 | limits->max_sysfs_pct = 100; | |
1569 | limits->min_policy_pct = 0; | |
1570 | limits->min_sysfs_pct = 0; | |
a410c03d | 1571 | mutex_unlock(&intel_pstate_limits_lock); |
30a39153 SP |
1572 | } |
1573 | ||
eae48f04 SP |
1574 | static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, |
1575 | struct perf_limits *limits) | |
1576 | { | |
a410c03d SP |
1577 | |
1578 | mutex_lock(&intel_pstate_limits_lock); | |
1579 | ||
eae48f04 SP |
1580 | limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, |
1581 | policy->cpuinfo.max_freq); | |
1582 | limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100); | |
5879f877 SP |
1583 | if (policy->max == policy->min) { |
1584 | limits->min_policy_pct = limits->max_policy_pct; | |
1585 | } else { | |
46992d6b SP |
1586 | limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100, |
1587 | policy->cpuinfo.max_freq); | |
5879f877 SP |
1588 | limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, |
1589 | 0, 100); | |
1590 | } | |
eae48f04 SP |
1591 | |
1592 | /* Normalize user input to [min_policy_pct, max_policy_pct] */ | |
1593 | limits->min_perf_pct = max(limits->min_policy_pct, | |
1594 | limits->min_sysfs_pct); | |
1595 | limits->min_perf_pct = min(limits->max_policy_pct, | |
1596 | limits->min_perf_pct); | |
1597 | limits->max_perf_pct = min(limits->max_policy_pct, | |
1598 | limits->max_sysfs_pct); | |
1599 | limits->max_perf_pct = max(limits->min_policy_pct, | |
1600 | limits->max_perf_pct); | |
1601 | ||
1602 | /* Make sure min_perf_pct <= max_perf_pct */ | |
1603 | limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); | |
1604 | ||
1605 | limits->min_perf = div_fp(limits->min_perf_pct, 100); | |
1606 | limits->max_perf = div_fp(limits->max_perf_pct, 100); | |
1607 | limits->max_perf = round_up(limits->max_perf, FRAC_BITS); | |
46992d6b | 1608 | limits->min_perf = round_up(limits->min_perf, FRAC_BITS); |
eae48f04 | 1609 | |
a410c03d SP |
1610 | mutex_unlock(&intel_pstate_limits_lock); |
1611 | ||
eae48f04 SP |
1612 | pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, |
1613 | limits->max_perf_pct, limits->min_perf_pct); | |
1614 | } | |
1615 | ||
93f0822d DB |
1616 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
1617 | { | |
3be9200d | 1618 | struct cpudata *cpu; |
eae48f04 | 1619 | struct perf_limits *perf_limits = NULL; |
3be9200d | 1620 | |
d3929b83 DB |
1621 | if (!policy->cpuinfo.max_freq) |
1622 | return -ENODEV; | |
1623 | ||
2c2c1af4 SP |
1624 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
1625 | policy->cpuinfo.max_freq, policy->max); | |
1626 | ||
a6c6ead1 | 1627 | cpu = all_cpu_data[policy->cpu]; |
2f1d407a RW |
1628 | cpu->policy = policy->policy; |
1629 | ||
c749c64f RW |
1630 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && |
1631 | policy->max < policy->cpuinfo.max_freq && | |
1632 | policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { | |
1633 | pr_debug("policy->max > max non turbo frequency\n"); | |
1634 | policy->max = policy->cpuinfo.max_freq; | |
3be9200d SP |
1635 | } |
1636 | ||
eae48f04 SP |
1637 | if (per_cpu_limits) |
1638 | perf_limits = cpu->perf_limits; | |
1639 | ||
1640 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { | |
1641 | if (!perf_limits) { | |
1642 | limits = &performance_limits; | |
1643 | perf_limits = limits; | |
1644 | } | |
30a39153 | 1645 | if (policy->max >= policy->cpuinfo.max_freq) { |
4836df17 | 1646 | pr_debug("set performance\n"); |
eae48f04 | 1647 | intel_pstate_set_performance_limits(perf_limits); |
30a39153 SP |
1648 | goto out; |
1649 | } | |
1650 | } else { | |
4836df17 | 1651 | pr_debug("set powersave\n"); |
eae48f04 SP |
1652 | if (!perf_limits) { |
1653 | limits = &powersave_limits; | |
1654 | perf_limits = limits; | |
1655 | } | |
43717aad | 1656 | |
eae48f04 | 1657 | } |
93f0822d | 1658 | |
eae48f04 | 1659 | intel_pstate_update_perf_limits(policy, perf_limits); |
bb6ab52f | 1660 | out: |
2f1d407a | 1661 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { |
a6c6ead1 RW |
1662 | /* |
1663 | * NOHZ_FULL CPUs need this as the governor callback may not | |
1664 | * be invoked on them. | |
1665 | */ | |
1666 | intel_pstate_clear_update_util_hook(policy->cpu); | |
1667 | intel_pstate_max_within_limits(cpu); | |
1668 | } | |
1669 | ||
bb6ab52f RW |
1670 | intel_pstate_set_update_util_hook(policy->cpu); |
1671 | ||
ba41e1bc | 1672 | intel_pstate_hwp_set_policy(policy); |
2f86dc4c | 1673 | |
93f0822d DB |
1674 | return 0; |
1675 | } | |
1676 | ||
1677 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1678 | { | |
be49e346 | 1679 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1680 | |
285cb990 | 1681 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1682 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1683 | return -EINVAL; |
1684 | ||
1685 | return 0; | |
1686 | } | |
1687 | ||
001c76f0 RW |
1688 | static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
1689 | { | |
1690 | intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); | |
1691 | } | |
1692 | ||
bb18008f | 1693 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1694 | { |
001c76f0 | 1695 | pr_debug("CPU %d exiting\n", policy->cpu); |
93f0822d | 1696 | |
001c76f0 RW |
1697 | intel_pstate_clear_update_util_hook(policy->cpu); |
1698 | if (!hwp_active) | |
1699 | intel_cpufreq_stop_cpu(policy); | |
1700 | } | |
bb18008f | 1701 | |
001c76f0 RW |
1702 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
1703 | { | |
1704 | intel_pstate_exit_perf_limits(policy); | |
a4675fbc | 1705 | |
001c76f0 | 1706 | policy->fast_switch_possible = false; |
2f86dc4c | 1707 | |
001c76f0 | 1708 | return 0; |
93f0822d DB |
1709 | } |
1710 | ||
001c76f0 | 1711 | static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1712 | { |
93f0822d | 1713 | struct cpudata *cpu; |
52e0a509 | 1714 | int rc; |
93f0822d DB |
1715 | |
1716 | rc = intel_pstate_init_cpu(policy->cpu); | |
1717 | if (rc) | |
1718 | return rc; | |
1719 | ||
1720 | cpu = all_cpu_data[policy->cpu]; | |
1721 | ||
eae48f04 SP |
1722 | /* |
1723 | * We need sane value in the cpu->perf_limits, so inherit from global | |
1724 | * perf_limits limits, which are seeded with values based on the | |
1725 | * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up. | |
1726 | */ | |
1727 | if (per_cpu_limits) | |
1728 | memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits)); | |
1729 | ||
b27580b0 DB |
1730 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1731 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1732 | |
1733 | /* cpuinfo and default policy values */ | |
b27580b0 | 1734 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e SP |
1735 | update_turbo_state(); |
1736 | policy->cpuinfo.max_freq = limits->turbo_disabled ? | |
1737 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; | |
1738 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
1739 | ||
9522a2ff | 1740 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d DB |
1741 | cpumask_set_cpu(policy->cpu, policy->cpus); |
1742 | ||
001c76f0 RW |
1743 | policy->fast_switch_possible = true; |
1744 | ||
93f0822d DB |
1745 | return 0; |
1746 | } | |
1747 | ||
001c76f0 | 1748 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
9522a2ff | 1749 | { |
001c76f0 RW |
1750 | int ret = __intel_pstate_cpu_init(policy); |
1751 | ||
1752 | if (ret) | |
1753 | return ret; | |
1754 | ||
1755 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
1756 | if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) | |
1757 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; | |
1758 | else | |
1759 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
9522a2ff SP |
1760 | |
1761 | return 0; | |
1762 | } | |
1763 | ||
001c76f0 | 1764 | static struct cpufreq_driver intel_pstate = { |
93f0822d DB |
1765 | .flags = CPUFREQ_CONST_LOOPS, |
1766 | .verify = intel_pstate_verify_policy, | |
1767 | .setpolicy = intel_pstate_set_policy, | |
ba41e1bc | 1768 | .resume = intel_pstate_hwp_set_policy, |
93f0822d DB |
1769 | .get = intel_pstate_get, |
1770 | .init = intel_pstate_cpu_init, | |
9522a2ff | 1771 | .exit = intel_pstate_cpu_exit, |
bb18008f | 1772 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1773 | .name = "intel_pstate", |
93f0822d DB |
1774 | }; |
1775 | ||
001c76f0 RW |
1776 | static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) |
1777 | { | |
1778 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
1779 | struct perf_limits *perf_limits = limits; | |
1780 | ||
1781 | update_turbo_state(); | |
1782 | policy->cpuinfo.max_freq = limits->turbo_disabled ? | |
1783 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; | |
1784 | ||
1785 | cpufreq_verify_within_cpu_limits(policy); | |
1786 | ||
1787 | if (per_cpu_limits) | |
1788 | perf_limits = cpu->perf_limits; | |
1789 | ||
1790 | intel_pstate_update_perf_limits(policy, perf_limits); | |
1791 | ||
1792 | return 0; | |
1793 | } | |
1794 | ||
1795 | static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu, | |
1796 | struct cpufreq_policy *policy, | |
1797 | unsigned int target_freq) | |
1798 | { | |
1799 | unsigned int max_freq; | |
1800 | ||
1801 | update_turbo_state(); | |
1802 | ||
1803 | max_freq = limits->no_turbo || limits->turbo_disabled ? | |
1804 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; | |
1805 | policy->cpuinfo.max_freq = max_freq; | |
1806 | if (policy->max > max_freq) | |
1807 | policy->max = max_freq; | |
1808 | ||
1809 | if (target_freq > max_freq) | |
1810 | target_freq = max_freq; | |
1811 | ||
1812 | return target_freq; | |
1813 | } | |
1814 | ||
1815 | static int intel_cpufreq_target(struct cpufreq_policy *policy, | |
1816 | unsigned int target_freq, | |
1817 | unsigned int relation) | |
1818 | { | |
1819 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
1820 | struct cpufreq_freqs freqs; | |
1821 | int target_pstate; | |
1822 | ||
1823 | freqs.old = policy->cur; | |
1824 | freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq); | |
1825 | ||
1826 | cpufreq_freq_transition_begin(policy, &freqs); | |
1827 | switch (relation) { | |
1828 | case CPUFREQ_RELATION_L: | |
1829 | target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
1830 | break; | |
1831 | case CPUFREQ_RELATION_H: | |
1832 | target_pstate = freqs.new / cpu->pstate.scaling; | |
1833 | break; | |
1834 | default: | |
1835 | target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
1836 | break; | |
1837 | } | |
1838 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); | |
1839 | if (target_pstate != cpu->pstate.current_pstate) { | |
1840 | cpu->pstate.current_pstate = target_pstate; | |
1841 | wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, | |
1842 | pstate_funcs.get_val(cpu, target_pstate)); | |
1843 | } | |
1844 | cpufreq_freq_transition_end(policy, &freqs, false); | |
1845 | ||
1846 | return 0; | |
1847 | } | |
1848 | ||
1849 | static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, | |
1850 | unsigned int target_freq) | |
1851 | { | |
1852 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
1853 | int target_pstate; | |
1854 | ||
1855 | target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq); | |
1856 | target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); | |
1857 | intel_pstate_update_pstate(cpu, target_pstate); | |
1858 | return target_freq; | |
1859 | } | |
1860 | ||
1861 | static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
1862 | { | |
1863 | int ret = __intel_pstate_cpu_init(policy); | |
1864 | ||
1865 | if (ret) | |
1866 | return ret; | |
1867 | ||
1868 | policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; | |
1869 | /* This reflects the intel_pstate_get_cpu_pstates() setting. */ | |
1870 | policy->cur = policy->cpuinfo.min_freq; | |
1871 | ||
1872 | return 0; | |
1873 | } | |
1874 | ||
1875 | static struct cpufreq_driver intel_cpufreq = { | |
1876 | .flags = CPUFREQ_CONST_LOOPS, | |
1877 | .verify = intel_cpufreq_verify_policy, | |
1878 | .target = intel_cpufreq_target, | |
1879 | .fast_switch = intel_cpufreq_fast_switch, | |
1880 | .init = intel_cpufreq_cpu_init, | |
1881 | .exit = intel_pstate_cpu_exit, | |
1882 | .stop_cpu = intel_cpufreq_stop_cpu, | |
1883 | .name = "intel_cpufreq", | |
1884 | }; | |
1885 | ||
1886 | static struct cpufreq_driver *intel_pstate_driver = &intel_pstate; | |
1887 | ||
eed43609 JZ |
1888 | static int no_load __initdata; |
1889 | static int no_hwp __initdata; | |
1890 | static int hwp_only __initdata; | |
29327c84 | 1891 | static unsigned int force_load __initdata; |
6be26498 | 1892 | |
29327c84 | 1893 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 1894 | { |
016c8150 | 1895 | if (!pstate_funcs.get_max() || |
c410833a SK |
1896 | !pstate_funcs.get_min() || |
1897 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1898 | return -ENODEV; |
1899 | ||
b563b4e3 DB |
1900 | return 0; |
1901 | } | |
016c8150 | 1902 | |
29327c84 | 1903 | static void __init copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1904 | { |
1905 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
a4675fbc | 1906 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
016c8150 DB |
1907 | pid_params.p_gain_pct = policy->p_gain_pct; |
1908 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1909 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1910 | pid_params.deadband = policy->deadband; | |
1911 | pid_params.setpoint = policy->setpoint; | |
1912 | } | |
1913 | ||
7f7a516e SP |
1914 | #ifdef CONFIG_ACPI |
1915 | static void intel_pstate_use_acpi_profile(void) | |
1916 | { | |
1917 | if (acpi_gbl_FADT.preferred_profile == PM_MOBILE) | |
1918 | pstate_funcs.get_target_pstate = | |
1919 | get_target_pstate_use_cpu_load; | |
1920 | } | |
1921 | #else | |
1922 | static void intel_pstate_use_acpi_profile(void) | |
1923 | { | |
1924 | } | |
1925 | #endif | |
1926 | ||
29327c84 | 1927 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1928 | { |
1929 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 1930 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
1931 | pstate_funcs.get_min = funcs->get_min; |
1932 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1933 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 1934 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 1935 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
1936 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
1937 | ||
7f7a516e | 1938 | intel_pstate_use_acpi_profile(); |
016c8150 DB |
1939 | } |
1940 | ||
9522a2ff | 1941 | #ifdef CONFIG_ACPI |
fbbcdc07 | 1942 | |
29327c84 | 1943 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
1944 | { |
1945 | int i; | |
1946 | ||
1947 | for_each_possible_cpu(i) { | |
1948 | acpi_status status; | |
1949 | union acpi_object *pss; | |
1950 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1951 | struct acpi_processor *pr = per_cpu(processors, i); | |
1952 | ||
1953 | if (!pr) | |
1954 | continue; | |
1955 | ||
1956 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1957 | if (ACPI_FAILURE(status)) | |
1958 | continue; | |
1959 | ||
1960 | pss = buffer.pointer; | |
1961 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1962 | kfree(pss); | |
1963 | return false; | |
1964 | } | |
1965 | ||
1966 | kfree(pss); | |
1967 | } | |
1968 | ||
1969 | return true; | |
1970 | } | |
1971 | ||
29327c84 | 1972 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 1973 | { |
1974 | int i; | |
1975 | ||
1976 | for_each_possible_cpu(i) { | |
1977 | struct acpi_processor *pr = per_cpu(processors, i); | |
1978 | ||
1979 | if (!pr) | |
1980 | continue; | |
1981 | if (acpi_has_method(pr->handle, "_PPC")) | |
1982 | return true; | |
1983 | } | |
1984 | return false; | |
1985 | } | |
1986 | ||
1987 | enum { | |
1988 | PSS, | |
1989 | PPC, | |
1990 | }; | |
1991 | ||
fbbcdc07 AH |
1992 | struct hw_vendor_info { |
1993 | u16 valid; | |
1994 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1995 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1996 | int oem_pwr_table; |
fbbcdc07 AH |
1997 | }; |
1998 | ||
1999 | /* Hardware vendor-specific info that has its own power management modes */ | |
29327c84 | 2000 | static struct hw_vendor_info vendor_info[] __initdata = { |
966916ea | 2001 | {1, "HP ", "ProLiant", PSS}, |
2002 | {1, "ORACLE", "X4-2 ", PPC}, | |
2003 | {1, "ORACLE", "X4-2L ", PPC}, | |
2004 | {1, "ORACLE", "X4-2B ", PPC}, | |
2005 | {1, "ORACLE", "X3-2 ", PPC}, | |
2006 | {1, "ORACLE", "X3-2L ", PPC}, | |
2007 | {1, "ORACLE", "X3-2B ", PPC}, | |
2008 | {1, "ORACLE", "X4470M2 ", PPC}, | |
2009 | {1, "ORACLE", "X4270M3 ", PPC}, | |
2010 | {1, "ORACLE", "X4270M2 ", PPC}, | |
2011 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
2012 | {1, "ORACLE", "X4170 M3", PPC}, |
2013 | {1, "ORACLE", "X4275 M3", PPC}, | |
2014 | {1, "ORACLE", "X6-2 ", PPC}, | |
2015 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
2016 | {0, "", ""}, |
2017 | }; | |
2018 | ||
29327c84 | 2019 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 AH |
2020 | { |
2021 | struct acpi_table_header hdr; | |
2022 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
2023 | const struct x86_cpu_id *id; |
2024 | u64 misc_pwr; | |
2025 | ||
2026 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
2027 | if (id) { | |
2028 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
2029 | if ( misc_pwr & (1 << 8)) | |
2030 | return true; | |
2031 | } | |
fbbcdc07 | 2032 | |
c410833a SK |
2033 | if (acpi_disabled || |
2034 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
2035 | return false; |
2036 | ||
2037 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 2038 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 2039 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
2040 | ACPI_OEM_TABLE_ID_SIZE)) | |
2041 | switch (v_info->oem_pwr_table) { | |
2042 | case PSS: | |
2043 | return intel_pstate_no_acpi_pss(); | |
2044 | case PPC: | |
aa4ea34d EZ |
2045 | return intel_pstate_has_acpi_ppc() && |
2046 | (!force_load); | |
966916ea | 2047 | } |
fbbcdc07 AH |
2048 | } |
2049 | ||
2050 | return false; | |
2051 | } | |
d0ea59e1 RW |
2052 | |
2053 | static void intel_pstate_request_control_from_smm(void) | |
2054 | { | |
2055 | /* | |
2056 | * It may be unsafe to request P-states control from SMM if _PPC support | |
2057 | * has not been enabled. | |
2058 | */ | |
2059 | if (acpi_ppc) | |
2060 | acpi_processor_pstate_control(); | |
2061 | } | |
fbbcdc07 AH |
2062 | #else /* CONFIG_ACPI not enabled */ |
2063 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 2064 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
d0ea59e1 | 2065 | static inline void intel_pstate_request_control_from_smm(void) {} |
fbbcdc07 AH |
2066 | #endif /* CONFIG_ACPI */ |
2067 | ||
7791e4aa SP |
2068 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
2069 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
2070 | {} | |
2071 | }; | |
2072 | ||
93f0822d DB |
2073 | static int __init intel_pstate_init(void) |
2074 | { | |
907cc908 | 2075 | int cpu, rc = 0; |
93f0822d | 2076 | const struct x86_cpu_id *id; |
64df1fdf | 2077 | struct cpu_defaults *cpu_def; |
93f0822d | 2078 | |
6be26498 DB |
2079 | if (no_load) |
2080 | return -ENODEV; | |
2081 | ||
7791e4aa SP |
2082 | if (x86_match_cpu(hwp_support_ids) && !no_hwp) { |
2083 | copy_cpu_funcs(&core_params.funcs); | |
2084 | hwp_active++; | |
2085 | goto hwp_cpu_matched; | |
2086 | } | |
2087 | ||
93f0822d DB |
2088 | id = x86_match_cpu(intel_pstate_cpu_ids); |
2089 | if (!id) | |
2090 | return -ENODEV; | |
2091 | ||
64df1fdf | 2092 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 2093 | |
64df1fdf BP |
2094 | copy_pid_params(&cpu_def->pid_policy); |
2095 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 2096 | |
b563b4e3 DB |
2097 | if (intel_pstate_msrs_not_valid()) |
2098 | return -ENODEV; | |
2099 | ||
7791e4aa SP |
2100 | hwp_cpu_matched: |
2101 | /* | |
2102 | * The Intel pstate driver will be ignored if the platform | |
2103 | * firmware has its own power management modes. | |
2104 | */ | |
2105 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
2106 | return -ENODEV; | |
2107 | ||
4836df17 | 2108 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 2109 | |
b57ffac5 | 2110 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
2111 | if (!all_cpu_data) |
2112 | return -ENOMEM; | |
93f0822d | 2113 | |
d64c3b0b KCA |
2114 | if (!hwp_active && hwp_only) |
2115 | goto out; | |
2116 | ||
d0ea59e1 RW |
2117 | intel_pstate_request_control_from_smm(); |
2118 | ||
001c76f0 | 2119 | rc = cpufreq_register_driver(intel_pstate_driver); |
93f0822d DB |
2120 | if (rc) |
2121 | goto out; | |
2122 | ||
2123 | intel_pstate_debug_expose_params(); | |
2124 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 2125 | |
7791e4aa | 2126 | if (hwp_active) |
4836df17 | 2127 | pr_info("HWP enabled\n"); |
7791e4aa | 2128 | |
93f0822d DB |
2129 | return rc; |
2130 | out: | |
907cc908 DB |
2131 | get_online_cpus(); |
2132 | for_each_online_cpu(cpu) { | |
2133 | if (all_cpu_data[cpu]) { | |
001c76f0 RW |
2134 | if (intel_pstate_driver == &intel_pstate) |
2135 | intel_pstate_clear_update_util_hook(cpu); | |
2136 | ||
907cc908 DB |
2137 | kfree(all_cpu_data[cpu]); |
2138 | } | |
2139 | } | |
2140 | ||
2141 | put_online_cpus(); | |
2142 | vfree(all_cpu_data); | |
93f0822d DB |
2143 | return -ENODEV; |
2144 | } | |
2145 | device_initcall(intel_pstate_init); | |
2146 | ||
6be26498 DB |
2147 | static int __init intel_pstate_setup(char *str) |
2148 | { | |
2149 | if (!str) | |
2150 | return -EINVAL; | |
2151 | ||
001c76f0 | 2152 | if (!strcmp(str, "disable")) { |
6be26498 | 2153 | no_load = 1; |
001c76f0 RW |
2154 | } else if (!strcmp(str, "passive")) { |
2155 | pr_info("Passive mode enabled\n"); | |
2156 | intel_pstate_driver = &intel_cpufreq; | |
2157 | no_hwp = 1; | |
2158 | } | |
539342f6 | 2159 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 2160 | pr_info("HWP disabled\n"); |
2f86dc4c | 2161 | no_hwp = 1; |
539342f6 | 2162 | } |
aa4ea34d EZ |
2163 | if (!strcmp(str, "force")) |
2164 | force_load = 1; | |
d64c3b0b KCA |
2165 | if (!strcmp(str, "hwp_only")) |
2166 | hwp_only = 1; | |
eae48f04 SP |
2167 | if (!strcmp(str, "per_cpu_perf_limits")) |
2168 | per_cpu_limits = true; | |
9522a2ff SP |
2169 | |
2170 | #ifdef CONFIG_ACPI | |
2171 | if (!strcmp(str, "support_acpi_ppc")) | |
2172 | acpi_ppc = true; | |
2173 | #endif | |
2174 | ||
6be26498 DB |
2175 | return 0; |
2176 | } | |
2177 | early_param("intel_pstate", intel_pstate_setup); | |
2178 | ||
93f0822d DB |
2179 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
2180 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
2181 | MODULE_LICENSE("GPL"); |