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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
55687da1 | 22 | #include <linux/sched/cpufreq.h> |
93f0822d DB |
23 | #include <linux/list.h> |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
001c76f0 RW |
40 | #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 |
41 | ||
9522a2ff SP |
42 | #ifdef CONFIG_ACPI |
43 | #include <acpi/processor.h> | |
17669006 | 44 | #include <acpi/cppc_acpi.h> |
9522a2ff SP |
45 | #endif |
46 | ||
f0fe3cd7 | 47 | #define FRAC_BITS 8 |
93f0822d DB |
48 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
49 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 50 | |
a1c9787d RW |
51 | #define EXT_BITS 6 |
52 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
d5dd33d9 SP |
53 | #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) |
54 | #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) | |
a1c9787d | 55 | |
93f0822d DB |
56 | static inline int32_t mul_fp(int32_t x, int32_t y) |
57 | { | |
58 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
59 | } | |
60 | ||
7180dddf | 61 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 62 | { |
7180dddf | 63 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
64 | } |
65 | ||
d022a65e DB |
66 | static inline int ceiling_fp(int32_t x) |
67 | { | |
68 | int mask, ret; | |
69 | ||
70 | ret = fp_toint(x); | |
71 | mask = (1 << FRAC_BITS) - 1; | |
72 | if (x & mask) | |
73 | ret += 1; | |
74 | return ret; | |
75 | } | |
76 | ||
a1c9787d RW |
77 | static inline u64 mul_ext_fp(u64 x, u64 y) |
78 | { | |
79 | return (x * y) >> EXT_FRAC_BITS; | |
80 | } | |
81 | ||
82 | static inline u64 div_ext_fp(u64 x, u64 y) | |
83 | { | |
84 | return div64_u64(x << EXT_FRAC_BITS, y); | |
85 | } | |
86 | ||
e4c204ce RW |
87 | static inline int32_t percent_ext_fp(int percent) |
88 | { | |
89 | return div_ext_fp(percent, 100); | |
90 | } | |
91 | ||
13ad7701 SP |
92 | /** |
93 | * struct sample - Store performance sample | |
a1c9787d | 94 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
95 | * performance during last sample period |
96 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 97 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
98 | * to account for cpu idle period |
99 | * @aperf: Difference of actual performance frequency clock count | |
100 | * read from APERF MSR between last and current sample | |
101 | * @mperf: Difference of maximum performance frequency clock count | |
102 | * read from MPERF MSR between last and current sample | |
103 | * @tsc: Difference of time stamp counter between last and | |
104 | * current sample | |
13ad7701 SP |
105 | * @time: Current time from scheduler |
106 | * | |
107 | * This structure is used in the cpudata structure to store performance sample | |
108 | * data for choosing next P State. | |
109 | */ | |
93f0822d | 110 | struct sample { |
a1c9787d | 111 | int32_t core_avg_perf; |
157386b6 | 112 | int32_t busy_scaled; |
93f0822d DB |
113 | u64 aperf; |
114 | u64 mperf; | |
4055fad3 | 115 | u64 tsc; |
a4675fbc | 116 | u64 time; |
93f0822d DB |
117 | }; |
118 | ||
13ad7701 SP |
119 | /** |
120 | * struct pstate_data - Store P state data | |
121 | * @current_pstate: Current requested P state | |
122 | * @min_pstate: Min P state possible for this platform | |
123 | * @max_pstate: Max P state possible for this platform | |
124 | * @max_pstate_physical:This is physical Max P state for a processor | |
125 | * This can be higher than the max_pstate which can | |
126 | * be limited by platform thermal design power limits | |
127 | * @scaling: Scaling factor to convert frequency to cpufreq | |
128 | * frequency units | |
129 | * @turbo_pstate: Max Turbo P state possible for this platform | |
001c76f0 RW |
130 | * @max_freq: @max_pstate frequency in cpufreq units |
131 | * @turbo_freq: @turbo_pstate frequency in cpufreq units | |
13ad7701 SP |
132 | * |
133 | * Stores the per cpu model P state limits and current P state. | |
134 | */ | |
93f0822d DB |
135 | struct pstate_data { |
136 | int current_pstate; | |
137 | int min_pstate; | |
138 | int max_pstate; | |
3bcc6fa9 | 139 | int max_pstate_physical; |
b27580b0 | 140 | int scaling; |
93f0822d | 141 | int turbo_pstate; |
001c76f0 RW |
142 | unsigned int max_freq; |
143 | unsigned int turbo_freq; | |
93f0822d DB |
144 | }; |
145 | ||
13ad7701 SP |
146 | /** |
147 | * struct vid_data - Stores voltage information data | |
148 | * @min: VID data for this platform corresponding to | |
149 | * the lowest P state | |
150 | * @max: VID data corresponding to the highest P State. | |
151 | * @turbo: VID data for turbo P state | |
152 | * @ratio: Ratio of (vid max - vid min) / | |
153 | * (max P state - Min P State) | |
154 | * | |
155 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
156 | * This data is used in Atom platforms, where in addition to target P state, | |
157 | * the voltage data needs to be specified to select next P State. | |
158 | */ | |
007bea09 | 159 | struct vid_data { |
21855ff5 DB |
160 | int min; |
161 | int max; | |
162 | int turbo; | |
007bea09 DB |
163 | int32_t ratio; |
164 | }; | |
165 | ||
13ad7701 SP |
166 | /** |
167 | * struct _pid - Stores PID data | |
168 | * @setpoint: Target set point for busyness or performance | |
169 | * @integral: Storage for accumulated error values | |
170 | * @p_gain: PID proportional gain | |
171 | * @i_gain: PID integral gain | |
172 | * @d_gain: PID derivative gain | |
173 | * @deadband: PID deadband | |
174 | * @last_err: Last error storage for integral part of PID calculation | |
175 | * | |
176 | * Stores PID coefficients and last error for PID controller. | |
177 | */ | |
93f0822d DB |
178 | struct _pid { |
179 | int setpoint; | |
180 | int32_t integral; | |
181 | int32_t p_gain; | |
182 | int32_t i_gain; | |
183 | int32_t d_gain; | |
184 | int deadband; | |
d253d2a5 | 185 | int32_t last_err; |
93f0822d DB |
186 | }; |
187 | ||
eae48f04 SP |
188 | /** |
189 | * struct perf_limits - Store user and policy limits | |
190 | * @no_turbo: User requested turbo state from intel_pstate sysfs | |
191 | * @turbo_disabled: Platform turbo status either from msr | |
192 | * MSR_IA32_MISC_ENABLE or when maximum available pstate | |
193 | * matches the maximum turbo pstate | |
194 | * @max_perf_pct: Effective maximum performance limit in percentage, this | |
195 | * is minimum of either limits enforced by cpufreq policy | |
196 | * or limits from user set limits via intel_pstate sysfs | |
197 | * @min_perf_pct: Effective minimum performance limit in percentage, this | |
198 | * is maximum of either limits enforced by cpufreq policy | |
199 | * or limits from user set limits via intel_pstate sysfs | |
200 | * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct | |
201 | * This value is used to limit max pstate | |
202 | * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct | |
203 | * This value is used to limit min pstate | |
204 | * @max_policy_pct: The maximum performance in percentage enforced by | |
205 | * cpufreq setpolicy interface | |
206 | * @max_sysfs_pct: The maximum performance in percentage enforced by | |
207 | * intel pstate sysfs interface, unused when per cpu | |
208 | * controls are enforced | |
209 | * @min_policy_pct: The minimum performance in percentage enforced by | |
210 | * cpufreq setpolicy interface | |
211 | * @min_sysfs_pct: The minimum performance in percentage enforced by | |
212 | * intel pstate sysfs interface, unused when per cpu | |
213 | * controls are enforced | |
214 | * | |
215 | * Storage for user and policy defined limits. | |
216 | */ | |
217 | struct perf_limits { | |
218 | int no_turbo; | |
219 | int turbo_disabled; | |
220 | int max_perf_pct; | |
221 | int min_perf_pct; | |
222 | int32_t max_perf; | |
223 | int32_t min_perf; | |
224 | int max_policy_pct; | |
225 | int max_sysfs_pct; | |
226 | int min_policy_pct; | |
227 | int min_sysfs_pct; | |
228 | }; | |
229 | ||
13ad7701 SP |
230 | /** |
231 | * struct cpudata - Per CPU instance data storage | |
232 | * @cpu: CPU number for this instance data | |
2f1d407a | 233 | * @policy: CPUFreq policy value |
13ad7701 | 234 | * @update_util: CPUFreq utility callback information |
4578ee7e | 235 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
236 | * @iowait_boost: iowait-related boost fraction |
237 | * @last_update: Time of the last update. | |
13ad7701 SP |
238 | * @pstate: Stores P state limits for this CPU |
239 | * @vid: Stores VID limits for this CPU | |
240 | * @pid: Stores PID parameters for this CPU | |
241 | * @last_sample_time: Last Sample time | |
242 | * @prev_aperf: Last APERF value read from APERF MSR | |
243 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
244 | * @prev_tsc: Last timestamp counter (TSC) value | |
245 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
246 | * current sample | |
247 | * @sample: Storage for storing last Sample data | |
eae48f04 SP |
248 | * @perf_limits: Pointer to perf_limit unique to this CPU |
249 | * Not all field in the structure are applicable | |
250 | * when per cpu controls are enforced | |
9522a2ff SP |
251 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
252 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
984edbdc SP |
253 | * @epp_powersave: Last saved HWP energy performance preference |
254 | * (EPP) or energy performance bias (EPB), | |
255 | * when policy switched to performance | |
8442885f | 256 | * @epp_policy: Last saved policy used to set EPP/EPB |
984edbdc SP |
257 | * @epp_default: Power on default HWP energy performance |
258 | * preference/bias | |
259 | * @epp_saved: Saved EPP/EPB during system suspend or CPU offline | |
260 | * operation | |
13ad7701 SP |
261 | * |
262 | * This structure stores per CPU instance data for all CPUs. | |
263 | */ | |
93f0822d DB |
264 | struct cpudata { |
265 | int cpu; | |
266 | ||
2f1d407a | 267 | unsigned int policy; |
a4675fbc | 268 | struct update_util_data update_util; |
4578ee7e | 269 | bool update_util_set; |
93f0822d | 270 | |
93f0822d | 271 | struct pstate_data pstate; |
007bea09 | 272 | struct vid_data vid; |
93f0822d | 273 | struct _pid pid; |
93f0822d | 274 | |
09c448d3 | 275 | u64 last_update; |
a4675fbc | 276 | u64 last_sample_time; |
93f0822d DB |
277 | u64 prev_aperf; |
278 | u64 prev_mperf; | |
4055fad3 | 279 | u64 prev_tsc; |
63d1d656 | 280 | u64 prev_cummulative_iowait; |
d37e2b76 | 281 | struct sample sample; |
eae48f04 | 282 | struct perf_limits *perf_limits; |
9522a2ff SP |
283 | #ifdef CONFIG_ACPI |
284 | struct acpi_processor_performance acpi_perf_data; | |
285 | bool valid_pss_table; | |
286 | #endif | |
09c448d3 | 287 | unsigned int iowait_boost; |
984edbdc | 288 | s16 epp_powersave; |
8442885f | 289 | s16 epp_policy; |
984edbdc SP |
290 | s16 epp_default; |
291 | s16 epp_saved; | |
93f0822d DB |
292 | }; |
293 | ||
294 | static struct cpudata **all_cpu_data; | |
13ad7701 SP |
295 | |
296 | /** | |
3954517e | 297 | * struct pstate_adjust_policy - Stores static PID configuration data |
13ad7701 SP |
298 | * @sample_rate_ms: PID calculation sample rate in ms |
299 | * @sample_rate_ns: Sample rate calculation in ns | |
300 | * @deadband: PID deadband | |
301 | * @setpoint: PID Setpoint | |
302 | * @p_gain_pct: PID proportional gain | |
303 | * @i_gain_pct: PID integral gain | |
304 | * @d_gain_pct: PID derivative gain | |
305 | * | |
306 | * Stores per CPU model static PID configuration data. | |
307 | */ | |
93f0822d DB |
308 | struct pstate_adjust_policy { |
309 | int sample_rate_ms; | |
a4675fbc | 310 | s64 sample_rate_ns; |
93f0822d DB |
311 | int deadband; |
312 | int setpoint; | |
313 | int p_gain_pct; | |
314 | int d_gain_pct; | |
315 | int i_gain_pct; | |
316 | }; | |
317 | ||
13ad7701 SP |
318 | /** |
319 | * struct pstate_funcs - Per CPU model specific callbacks | |
320 | * @get_max: Callback to get maximum non turbo effective P state | |
321 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
322 | * @get_min: Callback to get minimum P state | |
323 | * @get_turbo: Callback to get turbo P state | |
324 | * @get_scaling: Callback to get frequency scaling factor | |
325 | * @get_val: Callback to convert P state to actual MSR write value | |
326 | * @get_vid: Callback to get VID data for Atom platforms | |
327 | * @get_target_pstate: Callback to a function to calculate next P state to use | |
328 | * | |
329 | * Core and Atom CPU models have different way to get P State limits. This | |
330 | * structure is used to store those callbacks. | |
331 | */ | |
016c8150 DB |
332 | struct pstate_funcs { |
333 | int (*get_max)(void); | |
3bcc6fa9 | 334 | int (*get_max_physical)(void); |
016c8150 DB |
335 | int (*get_min)(void); |
336 | int (*get_turbo)(void); | |
b27580b0 | 337 | int (*get_scaling)(void); |
fdfdb2b1 | 338 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 339 | void (*get_vid)(struct cpudata *); |
157386b6 | 340 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
341 | }; |
342 | ||
13ad7701 SP |
343 | /** |
344 | * struct cpu_defaults- Per CPU model default config data | |
345 | * @pid_policy: PID config data | |
346 | * @funcs: Callback function data | |
347 | */ | |
016c8150 DB |
348 | struct cpu_defaults { |
349 | struct pstate_adjust_policy pid_policy; | |
350 | struct pstate_funcs funcs; | |
93f0822d DB |
351 | }; |
352 | ||
157386b6 | 353 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
e70eed2b | 354 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); |
157386b6 | 355 | |
4a7cb7a9 JZ |
356 | static struct pstate_adjust_policy pid_params __read_mostly; |
357 | static struct pstate_funcs pstate_funcs __read_mostly; | |
358 | static int hwp_active __read_mostly; | |
eae48f04 | 359 | static bool per_cpu_limits __read_mostly; |
016c8150 | 360 | |
0c30b65b RW |
361 | static bool driver_registered __read_mostly; |
362 | ||
9522a2ff SP |
363 | #ifdef CONFIG_ACPI |
364 | static bool acpi_ppc; | |
365 | #endif | |
13ad7701 | 366 | |
7de32556 | 367 | static struct perf_limits global; |
51443fbf | 368 | |
c3a49c89 RW |
369 | static void intel_pstate_init_limits(struct perf_limits *limits) |
370 | { | |
371 | memset(limits, 0, sizeof(*limits)); | |
372 | limits->max_perf_pct = 100; | |
373 | limits->max_perf = int_ext_tofp(1); | |
374 | limits->max_policy_pct = 100; | |
375 | limits->max_sysfs_pct = 100; | |
376 | } | |
93f0822d | 377 | |
0c30b65b | 378 | static DEFINE_MUTEX(intel_pstate_driver_lock); |
a410c03d SP |
379 | static DEFINE_MUTEX(intel_pstate_limits_lock); |
380 | ||
9522a2ff | 381 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
382 | |
383 | static bool intel_pstate_get_ppc_enable_status(void) | |
384 | { | |
385 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
386 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
387 | return true; | |
388 | ||
389 | return acpi_ppc; | |
390 | } | |
391 | ||
17669006 RW |
392 | #ifdef CONFIG_ACPI_CPPC_LIB |
393 | ||
394 | /* The work item is needed to avoid CPU hotplug locking issues */ | |
395 | static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) | |
396 | { | |
397 | sched_set_itmt_support(); | |
398 | } | |
399 | ||
400 | static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); | |
401 | ||
402 | static void intel_pstate_set_itmt_prio(int cpu) | |
403 | { | |
404 | struct cppc_perf_caps cppc_perf; | |
405 | static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; | |
406 | int ret; | |
407 | ||
408 | ret = cppc_get_perf_caps(cpu, &cppc_perf); | |
409 | if (ret) | |
410 | return; | |
411 | ||
412 | /* | |
413 | * The priorities can be set regardless of whether or not | |
414 | * sched_set_itmt_support(true) has been called and it is valid to | |
415 | * update them at any time after it has been called. | |
416 | */ | |
417 | sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); | |
418 | ||
419 | if (max_highest_perf <= min_highest_perf) { | |
420 | if (cppc_perf.highest_perf > max_highest_perf) | |
421 | max_highest_perf = cppc_perf.highest_perf; | |
422 | ||
423 | if (cppc_perf.highest_perf < min_highest_perf) | |
424 | min_highest_perf = cppc_perf.highest_perf; | |
425 | ||
426 | if (max_highest_perf > min_highest_perf) { | |
427 | /* | |
428 | * This code can be run during CPU online under the | |
429 | * CPU hotplug locks, so sched_set_itmt_support() | |
430 | * cannot be called from here. Queue up a work item | |
431 | * to invoke it. | |
432 | */ | |
433 | schedule_work(&sched_itmt_work); | |
434 | } | |
435 | } | |
436 | } | |
437 | #else | |
438 | static void intel_pstate_set_itmt_prio(int cpu) | |
439 | { | |
440 | } | |
441 | #endif | |
442 | ||
9522a2ff SP |
443 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
444 | { | |
445 | struct cpudata *cpu; | |
9522a2ff SP |
446 | int ret; |
447 | int i; | |
448 | ||
17669006 RW |
449 | if (hwp_active) { |
450 | intel_pstate_set_itmt_prio(policy->cpu); | |
e59a8f7f | 451 | return; |
17669006 | 452 | } |
e59a8f7f | 453 | |
2b3ec765 | 454 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
455 | return; |
456 | ||
457 | cpu = all_cpu_data[policy->cpu]; | |
458 | ||
459 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
460 | policy->cpu); | |
461 | if (ret) | |
462 | return; | |
463 | ||
464 | /* | |
465 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
466 | * guarantee that the states returned by it map to the states in our | |
467 | * list directly. | |
468 | */ | |
469 | if (cpu->acpi_perf_data.control_register.space_id != | |
470 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
471 | goto err; | |
472 | ||
473 | /* | |
474 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
475 | * usual without taking _PSS into account | |
476 | */ | |
477 | if (cpu->acpi_perf_data.state_count < 2) | |
478 | goto err; | |
479 | ||
480 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
481 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
482 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
483 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
484 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
485 | (u32) cpu->acpi_perf_data.states[i].power, | |
486 | (u32) cpu->acpi_perf_data.states[i].control); | |
487 | } | |
488 | ||
489 | /* | |
490 | * The _PSS table doesn't contain whole turbo frequency range. | |
491 | * This just contains +1 MHZ above the max non turbo frequency, | |
492 | * with control value corresponding to max turbo ratio. But | |
493 | * when cpufreq set policy is called, it will call with this | |
494 | * max frequency, which will cause a reduced performance as | |
495 | * this driver uses real max turbo frequency as the max | |
496 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 497 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
498 | * Also need to convert to MHz as _PSS freq is in MHz. |
499 | */ | |
7de32556 | 500 | if (!global.turbo_disabled) |
9522a2ff SP |
501 | cpu->acpi_perf_data.states[0].core_frequency = |
502 | policy->cpuinfo.max_freq / 1000; | |
503 | cpu->valid_pss_table = true; | |
6cacd115 | 504 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
505 | |
506 | return; | |
507 | ||
508 | err: | |
509 | cpu->valid_pss_table = false; | |
510 | acpi_processor_unregister_performance(policy->cpu); | |
511 | } | |
512 | ||
513 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
514 | { | |
515 | struct cpudata *cpu; | |
516 | ||
517 | cpu = all_cpu_data[policy->cpu]; | |
518 | if (!cpu->valid_pss_table) | |
519 | return; | |
520 | ||
521 | acpi_processor_unregister_performance(policy->cpu); | |
522 | } | |
9522a2ff | 523 | #else |
7a3ba767 | 524 | static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
525 | { |
526 | } | |
527 | ||
7a3ba767 | 528 | static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
529 | { |
530 | } | |
531 | #endif | |
532 | ||
93f0822d | 533 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 534 | int deadband, int integral) { |
b54a0dfd PL |
535 | pid->setpoint = int_tofp(setpoint); |
536 | pid->deadband = int_tofp(deadband); | |
93f0822d | 537 | pid->integral = int_tofp(integral); |
d98d099b | 538 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
539 | } |
540 | ||
541 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
542 | { | |
22590efb | 543 | pid->p_gain = div_fp(percent, 100); |
93f0822d DB |
544 | } |
545 | ||
546 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
547 | { | |
22590efb | 548 | pid->i_gain = div_fp(percent, 100); |
93f0822d DB |
549 | } |
550 | ||
551 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
552 | { | |
22590efb | 553 | pid->d_gain = div_fp(percent, 100); |
93f0822d DB |
554 | } |
555 | ||
d253d2a5 | 556 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 557 | { |
d253d2a5 | 558 | signed int result; |
93f0822d DB |
559 | int32_t pterm, dterm, fp_error; |
560 | int32_t integral_limit; | |
561 | ||
b54a0dfd | 562 | fp_error = pid->setpoint - busy; |
93f0822d | 563 | |
b54a0dfd | 564 | if (abs(fp_error) <= pid->deadband) |
93f0822d DB |
565 | return 0; |
566 | ||
567 | pterm = mul_fp(pid->p_gain, fp_error); | |
568 | ||
569 | pid->integral += fp_error; | |
570 | ||
e0d4c8f8 KCA |
571 | /* |
572 | * We limit the integral here so that it will never | |
573 | * get higher than 30. This prevents it from becoming | |
574 | * too large an input over long periods of time and allows | |
575 | * it to get factored out sooner. | |
576 | * | |
577 | * The value of 30 was chosen through experimentation. | |
578 | */ | |
93f0822d DB |
579 | integral_limit = int_tofp(30); |
580 | if (pid->integral > integral_limit) | |
581 | pid->integral = integral_limit; | |
582 | if (pid->integral < -integral_limit) | |
583 | pid->integral = -integral_limit; | |
584 | ||
d253d2a5 BS |
585 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
586 | pid->last_err = fp_error; | |
93f0822d DB |
587 | |
588 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 589 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
590 | return (signed int)fp_toint(result); |
591 | } | |
592 | ||
593 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
594 | { | |
016c8150 DB |
595 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
596 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
597 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 598 | |
2d8d1f18 | 599 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
600 | } |
601 | ||
93f0822d DB |
602 | static inline void intel_pstate_reset_all_pid(void) |
603 | { | |
604 | unsigned int cpu; | |
845c1cbe | 605 | |
93f0822d DB |
606 | for_each_online_cpu(cpu) { |
607 | if (all_cpu_data[cpu]) | |
608 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
609 | } | |
610 | } | |
611 | ||
4521e1a0 GM |
612 | static inline void update_turbo_state(void) |
613 | { | |
614 | u64 misc_en; | |
615 | struct cpudata *cpu; | |
616 | ||
617 | cpu = all_cpu_data[0]; | |
618 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
7de32556 | 619 | global.turbo_disabled = |
4521e1a0 GM |
620 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
621 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
622 | } | |
623 | ||
8442885f SP |
624 | static s16 intel_pstate_get_epb(struct cpudata *cpu_data) |
625 | { | |
626 | u64 epb; | |
627 | int ret; | |
628 | ||
629 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
630 | return -ENXIO; | |
631 | ||
632 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); | |
633 | if (ret) | |
634 | return (s16)ret; | |
635 | ||
636 | return (s16)(epb & 0x0f); | |
637 | } | |
638 | ||
639 | static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) | |
640 | { | |
641 | s16 epp; | |
642 | ||
984edbdc SP |
643 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
644 | /* | |
645 | * When hwp_req_data is 0, means that caller didn't read | |
646 | * MSR_HWP_REQUEST, so need to read and get EPP. | |
647 | */ | |
648 | if (!hwp_req_data) { | |
649 | epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, | |
650 | &hwp_req_data); | |
651 | if (epp) | |
652 | return epp; | |
653 | } | |
8442885f | 654 | epp = (hwp_req_data >> 24) & 0xff; |
984edbdc | 655 | } else { |
8442885f SP |
656 | /* When there is no EPP present, HWP uses EPB settings */ |
657 | epp = intel_pstate_get_epb(cpu_data); | |
984edbdc | 658 | } |
8442885f SP |
659 | |
660 | return epp; | |
661 | } | |
662 | ||
984edbdc | 663 | static int intel_pstate_set_epb(int cpu, s16 pref) |
8442885f SP |
664 | { |
665 | u64 epb; | |
984edbdc | 666 | int ret; |
8442885f SP |
667 | |
668 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
984edbdc | 669 | return -ENXIO; |
8442885f | 670 | |
984edbdc SP |
671 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); |
672 | if (ret) | |
673 | return ret; | |
8442885f SP |
674 | |
675 | epb = (epb & ~0x0f) | pref; | |
676 | wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); | |
984edbdc SP |
677 | |
678 | return 0; | |
8442885f SP |
679 | } |
680 | ||
984edbdc SP |
681 | /* |
682 | * EPP/EPB display strings corresponding to EPP index in the | |
683 | * energy_perf_strings[] | |
684 | * index String | |
685 | *------------------------------------- | |
686 | * 0 default | |
687 | * 1 performance | |
688 | * 2 balance_performance | |
689 | * 3 balance_power | |
690 | * 4 power | |
691 | */ | |
692 | static const char * const energy_perf_strings[] = { | |
693 | "default", | |
694 | "performance", | |
695 | "balance_performance", | |
696 | "balance_power", | |
697 | "power", | |
698 | NULL | |
699 | }; | |
700 | ||
701 | static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) | |
702 | { | |
703 | s16 epp; | |
704 | int index = -EINVAL; | |
705 | ||
706 | epp = intel_pstate_get_epp(cpu_data, 0); | |
707 | if (epp < 0) | |
708 | return epp; | |
709 | ||
710 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
711 | /* | |
712 | * Range: | |
713 | * 0x00-0x3F : Performance | |
714 | * 0x40-0x7F : Balance performance | |
715 | * 0x80-0xBF : Balance power | |
716 | * 0xC0-0xFF : Power | |
717 | * The EPP is a 8 bit value, but our ranges restrict the | |
718 | * value which can be set. Here only using top two bits | |
719 | * effectively. | |
720 | */ | |
721 | index = (epp >> 6) + 1; | |
722 | } else if (static_cpu_has(X86_FEATURE_EPB)) { | |
723 | /* | |
724 | * Range: | |
725 | * 0x00-0x03 : Performance | |
726 | * 0x04-0x07 : Balance performance | |
727 | * 0x08-0x0B : Balance power | |
728 | * 0x0C-0x0F : Power | |
729 | * The EPB is a 4 bit value, but our ranges restrict the | |
730 | * value which can be set. Here only using top two bits | |
731 | * effectively. | |
732 | */ | |
733 | index = (epp >> 2) + 1; | |
734 | } | |
735 | ||
736 | return index; | |
737 | } | |
738 | ||
739 | static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, | |
740 | int pref_index) | |
741 | { | |
742 | int epp = -EINVAL; | |
743 | int ret; | |
744 | ||
745 | if (!pref_index) | |
746 | epp = cpu_data->epp_default; | |
747 | ||
748 | mutex_lock(&intel_pstate_limits_lock); | |
749 | ||
750 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
751 | u64 value; | |
752 | ||
753 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); | |
754 | if (ret) | |
755 | goto return_pref; | |
756 | ||
757 | value &= ~GENMASK_ULL(31, 24); | |
758 | ||
759 | /* | |
760 | * If epp is not default, convert from index into | |
761 | * energy_perf_strings to epp value, by shifting 6 | |
762 | * bits left to use only top two bits in epp. | |
763 | * The resultant epp need to shifted by 24 bits to | |
764 | * epp position in MSR_HWP_REQUEST. | |
765 | */ | |
766 | if (epp == -EINVAL) | |
767 | epp = (pref_index - 1) << 6; | |
768 | ||
769 | value |= (u64)epp << 24; | |
770 | ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); | |
771 | } else { | |
772 | if (epp == -EINVAL) | |
773 | epp = (pref_index - 1) << 2; | |
774 | ret = intel_pstate_set_epb(cpu_data->cpu, epp); | |
775 | } | |
776 | return_pref: | |
777 | mutex_unlock(&intel_pstate_limits_lock); | |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
782 | static ssize_t show_energy_performance_available_preferences( | |
783 | struct cpufreq_policy *policy, char *buf) | |
784 | { | |
785 | int i = 0; | |
786 | int ret = 0; | |
787 | ||
788 | while (energy_perf_strings[i] != NULL) | |
789 | ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); | |
790 | ||
791 | ret += sprintf(&buf[ret], "\n"); | |
792 | ||
793 | return ret; | |
794 | } | |
795 | ||
796 | cpufreq_freq_attr_ro(energy_performance_available_preferences); | |
797 | ||
798 | static ssize_t store_energy_performance_preference( | |
799 | struct cpufreq_policy *policy, const char *buf, size_t count) | |
800 | { | |
801 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
802 | char str_preference[21]; | |
803 | int ret, i = 0; | |
804 | ||
805 | ret = sscanf(buf, "%20s", str_preference); | |
806 | if (ret != 1) | |
807 | return -EINVAL; | |
808 | ||
809 | while (energy_perf_strings[i] != NULL) { | |
810 | if (!strcmp(str_preference, energy_perf_strings[i])) { | |
811 | intel_pstate_set_energy_pref_index(cpu_data, i); | |
812 | return count; | |
813 | } | |
814 | ++i; | |
815 | } | |
816 | ||
817 | return -EINVAL; | |
818 | } | |
819 | ||
820 | static ssize_t show_energy_performance_preference( | |
821 | struct cpufreq_policy *policy, char *buf) | |
822 | { | |
823 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
824 | int preference; | |
825 | ||
826 | preference = intel_pstate_get_energy_pref_index(cpu_data); | |
827 | if (preference < 0) | |
828 | return preference; | |
829 | ||
830 | return sprintf(buf, "%s\n", energy_perf_strings[preference]); | |
831 | } | |
832 | ||
833 | cpufreq_freq_attr_rw(energy_performance_preference); | |
834 | ||
835 | static struct freq_attr *hwp_cpufreq_attrs[] = { | |
836 | &energy_performance_preference, | |
837 | &energy_performance_available_preferences, | |
838 | NULL, | |
839 | }; | |
840 | ||
111b8b3f | 841 | static void intel_pstate_hwp_set(struct cpufreq_policy *policy) |
2f86dc4c | 842 | { |
3f8ed54a | 843 | int min, hw_min, max, hw_max, cpu; |
7de32556 | 844 | struct perf_limits *perf_limits = &global; |
74da56ce KCA |
845 | u64 value, cap; |
846 | ||
111b8b3f | 847 | for_each_cpu(cpu, policy->cpus) { |
8442885f SP |
848 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
849 | s16 epp; | |
eae48f04 SP |
850 | |
851 | if (per_cpu_limits) | |
852 | perf_limits = all_cpu_data[cpu]->perf_limits; | |
853 | ||
f9f4872d SP |
854 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
855 | hw_min = HWP_LOWEST_PERF(cap); | |
7de32556 | 856 | if (global.no_turbo) |
4e5d3f71 SP |
857 | hw_max = HWP_GUARANTEED_PERF(cap); |
858 | else | |
859 | hw_max = HWP_HIGHEST_PERF(cap); | |
f9f4872d | 860 | |
7de32556 RW |
861 | max = fp_ext_toint(hw_max * perf_limits->max_perf); |
862 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) | |
863 | min = max; | |
864 | else | |
865 | min = fp_ext_toint(hw_max * perf_limits->min_perf); | |
eae48f04 | 866 | |
2f86dc4c | 867 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
3f8ed54a | 868 | |
2f86dc4c DB |
869 | value &= ~HWP_MIN_PERF(~0L); |
870 | value |= HWP_MIN_PERF(min); | |
871 | ||
2f86dc4c DB |
872 | value &= ~HWP_MAX_PERF(~0L); |
873 | value |= HWP_MAX_PERF(max); | |
8442885f SP |
874 | |
875 | if (cpu_data->epp_policy == cpu_data->policy) | |
876 | goto skip_epp; | |
877 | ||
878 | cpu_data->epp_policy = cpu_data->policy; | |
879 | ||
984edbdc SP |
880 | if (cpu_data->epp_saved >= 0) { |
881 | epp = cpu_data->epp_saved; | |
882 | cpu_data->epp_saved = -EINVAL; | |
883 | goto update_epp; | |
884 | } | |
885 | ||
8442885f SP |
886 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { |
887 | epp = intel_pstate_get_epp(cpu_data, value); | |
984edbdc | 888 | cpu_data->epp_powersave = epp; |
8442885f | 889 | /* If EPP read was failed, then don't try to write */ |
984edbdc | 890 | if (epp < 0) |
8442885f | 891 | goto skip_epp; |
8442885f | 892 | |
8442885f SP |
893 | |
894 | epp = 0; | |
895 | } else { | |
896 | /* skip setting EPP, when saved value is invalid */ | |
984edbdc | 897 | if (cpu_data->epp_powersave < 0) |
8442885f SP |
898 | goto skip_epp; |
899 | ||
900 | /* | |
901 | * No need to restore EPP when it is not zero. This | |
902 | * means: | |
903 | * - Policy is not changed | |
904 | * - user has manually changed | |
905 | * - Error reading EPB | |
906 | */ | |
907 | epp = intel_pstate_get_epp(cpu_data, value); | |
908 | if (epp) | |
909 | goto skip_epp; | |
910 | ||
984edbdc | 911 | epp = cpu_data->epp_powersave; |
8442885f | 912 | } |
984edbdc | 913 | update_epp: |
8442885f SP |
914 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
915 | value &= ~GENMASK_ULL(31, 24); | |
916 | value |= (u64)epp << 24; | |
917 | } else { | |
918 | intel_pstate_set_epb(cpu, epp); | |
919 | } | |
920 | skip_epp: | |
2f86dc4c DB |
921 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); |
922 | } | |
41cfd64c | 923 | } |
2f86dc4c | 924 | |
984edbdc SP |
925 | static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) |
926 | { | |
927 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
928 | ||
929 | if (!hwp_active) | |
930 | return 0; | |
931 | ||
932 | cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); | |
933 | ||
934 | return 0; | |
935 | } | |
936 | ||
8442885f SP |
937 | static int intel_pstate_resume(struct cpufreq_policy *policy) |
938 | { | |
939 | if (!hwp_active) | |
940 | return 0; | |
941 | ||
aa439248 RW |
942 | mutex_lock(&intel_pstate_limits_lock); |
943 | ||
8442885f | 944 | all_cpu_data[policy->cpu]->epp_policy = 0; |
5f98ced1 | 945 | intel_pstate_hwp_set(policy); |
aa439248 RW |
946 | |
947 | mutex_unlock(&intel_pstate_limits_lock); | |
948 | ||
5f98ced1 | 949 | return 0; |
8442885f SP |
950 | } |
951 | ||
111b8b3f | 952 | static void intel_pstate_update_policies(void) |
41cfd64c | 953 | { |
111b8b3f RW |
954 | int cpu; |
955 | ||
956 | for_each_possible_cpu(cpu) | |
957 | cpufreq_update_policy(cpu); | |
2f86dc4c DB |
958 | } |
959 | ||
93f0822d DB |
960 | /************************** debugfs begin ************************/ |
961 | static int pid_param_set(void *data, u64 val) | |
962 | { | |
963 | *(u32 *)data = val; | |
6e7408ac | 964 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
93f0822d DB |
965 | intel_pstate_reset_all_pid(); |
966 | return 0; | |
967 | } | |
845c1cbe | 968 | |
93f0822d DB |
969 | static int pid_param_get(void *data, u64 *val) |
970 | { | |
971 | *val = *(u32 *)data; | |
972 | return 0; | |
973 | } | |
2d8d1f18 | 974 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d | 975 | |
fb1fe104 RW |
976 | static struct dentry *debugfs_parent; |
977 | ||
93f0822d DB |
978 | struct pid_param { |
979 | char *name; | |
980 | void *value; | |
fb1fe104 | 981 | struct dentry *dentry; |
93f0822d DB |
982 | }; |
983 | ||
984 | static struct pid_param pid_files[] = { | |
fb1fe104 RW |
985 | {"sample_rate_ms", &pid_params.sample_rate_ms, }, |
986 | {"d_gain_pct", &pid_params.d_gain_pct, }, | |
987 | {"i_gain_pct", &pid_params.i_gain_pct, }, | |
988 | {"deadband", &pid_params.deadband, }, | |
989 | {"setpoint", &pid_params.setpoint, }, | |
990 | {"p_gain_pct", &pid_params.p_gain_pct, }, | |
991 | {NULL, NULL, } | |
93f0822d DB |
992 | }; |
993 | ||
fb1fe104 | 994 | static void intel_pstate_debug_expose_params(void) |
93f0822d | 995 | { |
fb1fe104 | 996 | int i; |
93f0822d DB |
997 | |
998 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); | |
999 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
1000 | return; | |
fb1fe104 RW |
1001 | |
1002 | for (i = 0; pid_files[i].name; i++) { | |
1003 | struct dentry *dentry; | |
1004 | ||
1005 | dentry = debugfs_create_file(pid_files[i].name, 0660, | |
1006 | debugfs_parent, pid_files[i].value, | |
1007 | &fops_pid_param); | |
1008 | if (!IS_ERR(dentry)) | |
1009 | pid_files[i].dentry = dentry; | |
93f0822d DB |
1010 | } |
1011 | } | |
1012 | ||
fb1fe104 RW |
1013 | static void intel_pstate_debug_hide_params(void) |
1014 | { | |
1015 | int i; | |
1016 | ||
1017 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
1018 | return; | |
1019 | ||
1020 | for (i = 0; pid_files[i].name; i++) { | |
1021 | debugfs_remove(pid_files[i].dentry); | |
1022 | pid_files[i].dentry = NULL; | |
93f0822d | 1023 | } |
fb1fe104 RW |
1024 | |
1025 | debugfs_remove(debugfs_parent); | |
1026 | debugfs_parent = NULL; | |
93f0822d DB |
1027 | } |
1028 | ||
1029 | /************************** debugfs end ************************/ | |
1030 | ||
1031 | /************************** sysfs begin ************************/ | |
1032 | #define show_one(file_name, object) \ | |
1033 | static ssize_t show_##file_name \ | |
1034 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
1035 | { \ | |
7de32556 | 1036 | return sprintf(buf, "%u\n", global.object); \ |
93f0822d DB |
1037 | } |
1038 | ||
fb1fe104 RW |
1039 | static ssize_t intel_pstate_show_status(char *buf); |
1040 | static int intel_pstate_update_status(const char *buf, size_t size); | |
1041 | ||
1042 | static ssize_t show_status(struct kobject *kobj, | |
1043 | struct attribute *attr, char *buf) | |
1044 | { | |
1045 | ssize_t ret; | |
1046 | ||
1047 | mutex_lock(&intel_pstate_driver_lock); | |
1048 | ret = intel_pstate_show_status(buf); | |
1049 | mutex_unlock(&intel_pstate_driver_lock); | |
1050 | ||
1051 | return ret; | |
1052 | } | |
1053 | ||
1054 | static ssize_t store_status(struct kobject *a, struct attribute *b, | |
1055 | const char *buf, size_t count) | |
1056 | { | |
1057 | char *p = memchr(buf, '\n', count); | |
1058 | int ret; | |
1059 | ||
1060 | mutex_lock(&intel_pstate_driver_lock); | |
1061 | ret = intel_pstate_update_status(buf, p ? p - buf : count); | |
1062 | mutex_unlock(&intel_pstate_driver_lock); | |
1063 | ||
1064 | return ret < 0 ? ret : count; | |
1065 | } | |
1066 | ||
d01b1f48 KCA |
1067 | static ssize_t show_turbo_pct(struct kobject *kobj, |
1068 | struct attribute *attr, char *buf) | |
1069 | { | |
1070 | struct cpudata *cpu; | |
1071 | int total, no_turbo, turbo_pct; | |
1072 | uint32_t turbo_fp; | |
1073 | ||
0c30b65b RW |
1074 | mutex_lock(&intel_pstate_driver_lock); |
1075 | ||
1076 | if (!driver_registered) { | |
1077 | mutex_unlock(&intel_pstate_driver_lock); | |
1078 | return -EAGAIN; | |
1079 | } | |
1080 | ||
d01b1f48 KCA |
1081 | cpu = all_cpu_data[0]; |
1082 | ||
1083 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
1084 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 1085 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 | 1086 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
0c30b65b RW |
1087 | |
1088 | mutex_unlock(&intel_pstate_driver_lock); | |
1089 | ||
d01b1f48 KCA |
1090 | return sprintf(buf, "%u\n", turbo_pct); |
1091 | } | |
1092 | ||
0522424e KCA |
1093 | static ssize_t show_num_pstates(struct kobject *kobj, |
1094 | struct attribute *attr, char *buf) | |
1095 | { | |
1096 | struct cpudata *cpu; | |
1097 | int total; | |
1098 | ||
0c30b65b RW |
1099 | mutex_lock(&intel_pstate_driver_lock); |
1100 | ||
1101 | if (!driver_registered) { | |
1102 | mutex_unlock(&intel_pstate_driver_lock); | |
1103 | return -EAGAIN; | |
1104 | } | |
1105 | ||
0522424e KCA |
1106 | cpu = all_cpu_data[0]; |
1107 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
0c30b65b RW |
1108 | |
1109 | mutex_unlock(&intel_pstate_driver_lock); | |
1110 | ||
0522424e KCA |
1111 | return sprintf(buf, "%u\n", total); |
1112 | } | |
1113 | ||
4521e1a0 GM |
1114 | static ssize_t show_no_turbo(struct kobject *kobj, |
1115 | struct attribute *attr, char *buf) | |
1116 | { | |
1117 | ssize_t ret; | |
1118 | ||
0c30b65b RW |
1119 | mutex_lock(&intel_pstate_driver_lock); |
1120 | ||
1121 | if (!driver_registered) { | |
1122 | mutex_unlock(&intel_pstate_driver_lock); | |
1123 | return -EAGAIN; | |
1124 | } | |
1125 | ||
4521e1a0 | 1126 | update_turbo_state(); |
7de32556 RW |
1127 | if (global.turbo_disabled) |
1128 | ret = sprintf(buf, "%u\n", global.turbo_disabled); | |
4521e1a0 | 1129 | else |
7de32556 | 1130 | ret = sprintf(buf, "%u\n", global.no_turbo); |
4521e1a0 | 1131 | |
0c30b65b RW |
1132 | mutex_unlock(&intel_pstate_driver_lock); |
1133 | ||
4521e1a0 GM |
1134 | return ret; |
1135 | } | |
1136 | ||
93f0822d | 1137 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 1138 | const char *buf, size_t count) |
93f0822d DB |
1139 | { |
1140 | unsigned int input; | |
1141 | int ret; | |
845c1cbe | 1142 | |
93f0822d DB |
1143 | ret = sscanf(buf, "%u", &input); |
1144 | if (ret != 1) | |
1145 | return -EINVAL; | |
4521e1a0 | 1146 | |
0c30b65b RW |
1147 | mutex_lock(&intel_pstate_driver_lock); |
1148 | ||
1149 | if (!driver_registered) { | |
1150 | mutex_unlock(&intel_pstate_driver_lock); | |
1151 | return -EAGAIN; | |
1152 | } | |
1153 | ||
a410c03d SP |
1154 | mutex_lock(&intel_pstate_limits_lock); |
1155 | ||
4521e1a0 | 1156 | update_turbo_state(); |
7de32556 | 1157 | if (global.turbo_disabled) { |
4836df17 | 1158 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
a410c03d | 1159 | mutex_unlock(&intel_pstate_limits_lock); |
0c30b65b | 1160 | mutex_unlock(&intel_pstate_driver_lock); |
4521e1a0 | 1161 | return -EPERM; |
dd5fbf70 | 1162 | } |
2f86dc4c | 1163 | |
7de32556 | 1164 | global.no_turbo = clamp_t(int, input, 0, 1); |
111b8b3f | 1165 | |
cd59b4be RW |
1166 | mutex_unlock(&intel_pstate_limits_lock); |
1167 | ||
7de32556 RW |
1168 | intel_pstate_update_policies(); |
1169 | ||
0c30b65b RW |
1170 | mutex_unlock(&intel_pstate_driver_lock); |
1171 | ||
93f0822d DB |
1172 | return count; |
1173 | } | |
1174 | ||
1175 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 1176 | const char *buf, size_t count) |
93f0822d DB |
1177 | { |
1178 | unsigned int input; | |
1179 | int ret; | |
845c1cbe | 1180 | |
93f0822d DB |
1181 | ret = sscanf(buf, "%u", &input); |
1182 | if (ret != 1) | |
1183 | return -EINVAL; | |
1184 | ||
0c30b65b RW |
1185 | mutex_lock(&intel_pstate_driver_lock); |
1186 | ||
1187 | if (!driver_registered) { | |
1188 | mutex_unlock(&intel_pstate_driver_lock); | |
1189 | return -EAGAIN; | |
1190 | } | |
1191 | ||
a410c03d SP |
1192 | mutex_lock(&intel_pstate_limits_lock); |
1193 | ||
7de32556 RW |
1194 | global.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
1195 | global.max_perf_pct = min(global.max_policy_pct, global.max_sysfs_pct); | |
1196 | global.max_perf_pct = max(global.min_policy_pct, global.max_perf_pct); | |
1197 | global.max_perf_pct = max(global.min_perf_pct, global.max_perf_pct); | |
1198 | global.max_perf = percent_ext_fp(global.max_perf_pct); | |
111b8b3f | 1199 | |
cd59b4be RW |
1200 | mutex_unlock(&intel_pstate_limits_lock); |
1201 | ||
7de32556 RW |
1202 | intel_pstate_update_policies(); |
1203 | ||
0c30b65b RW |
1204 | mutex_unlock(&intel_pstate_driver_lock); |
1205 | ||
93f0822d DB |
1206 | return count; |
1207 | } | |
1208 | ||
1209 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 1210 | const char *buf, size_t count) |
93f0822d DB |
1211 | { |
1212 | unsigned int input; | |
1213 | int ret; | |
845c1cbe | 1214 | |
93f0822d DB |
1215 | ret = sscanf(buf, "%u", &input); |
1216 | if (ret != 1) | |
1217 | return -EINVAL; | |
a0475992 | 1218 | |
0c30b65b RW |
1219 | mutex_lock(&intel_pstate_driver_lock); |
1220 | ||
1221 | if (!driver_registered) { | |
1222 | mutex_unlock(&intel_pstate_driver_lock); | |
1223 | return -EAGAIN; | |
1224 | } | |
1225 | ||
a410c03d SP |
1226 | mutex_lock(&intel_pstate_limits_lock); |
1227 | ||
7de32556 RW |
1228 | global.min_sysfs_pct = clamp_t(int, input, 0 , 100); |
1229 | global.min_perf_pct = max(global.min_policy_pct, global.min_sysfs_pct); | |
1230 | global.min_perf_pct = min(global.max_policy_pct, global.min_perf_pct); | |
1231 | global.min_perf_pct = min(global.max_perf_pct, global.min_perf_pct); | |
1232 | global.min_perf = percent_ext_fp(global.min_perf_pct); | |
111b8b3f | 1233 | |
cd59b4be RW |
1234 | mutex_unlock(&intel_pstate_limits_lock); |
1235 | ||
7de32556 RW |
1236 | intel_pstate_update_policies(); |
1237 | ||
0c30b65b RW |
1238 | mutex_unlock(&intel_pstate_driver_lock); |
1239 | ||
93f0822d DB |
1240 | return count; |
1241 | } | |
1242 | ||
93f0822d DB |
1243 | show_one(max_perf_pct, max_perf_pct); |
1244 | show_one(min_perf_pct, min_perf_pct); | |
1245 | ||
fb1fe104 | 1246 | define_one_global_rw(status); |
93f0822d DB |
1247 | define_one_global_rw(no_turbo); |
1248 | define_one_global_rw(max_perf_pct); | |
1249 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 1250 | define_one_global_ro(turbo_pct); |
0522424e | 1251 | define_one_global_ro(num_pstates); |
93f0822d DB |
1252 | |
1253 | static struct attribute *intel_pstate_attributes[] = { | |
fb1fe104 | 1254 | &status.attr, |
93f0822d | 1255 | &no_turbo.attr, |
d01b1f48 | 1256 | &turbo_pct.attr, |
0522424e | 1257 | &num_pstates.attr, |
93f0822d DB |
1258 | NULL |
1259 | }; | |
1260 | ||
1261 | static struct attribute_group intel_pstate_attr_group = { | |
1262 | .attrs = intel_pstate_attributes, | |
1263 | }; | |
93f0822d | 1264 | |
317dd50e | 1265 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 1266 | { |
317dd50e | 1267 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
1268 | int rc; |
1269 | ||
1270 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
1271 | &cpu_subsys.dev_root->kobj); | |
eae48f04 SP |
1272 | if (WARN_ON(!intel_pstate_kobject)) |
1273 | return; | |
1274 | ||
2d8d1f18 | 1275 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
eae48f04 SP |
1276 | if (WARN_ON(rc)) |
1277 | return; | |
1278 | ||
1279 | /* | |
1280 | * If per cpu limits are enforced there are no global limits, so | |
1281 | * return without creating max/min_perf_pct attributes | |
1282 | */ | |
1283 | if (per_cpu_limits) | |
1284 | return; | |
1285 | ||
1286 | rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); | |
1287 | WARN_ON(rc); | |
1288 | ||
1289 | rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); | |
1290 | WARN_ON(rc); | |
1291 | ||
93f0822d | 1292 | } |
93f0822d | 1293 | /************************** sysfs end ************************/ |
2f86dc4c | 1294 | |
ba88d433 | 1295 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 1296 | { |
f05c9665 | 1297 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
1298 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
1299 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 1300 | |
ba88d433 | 1301 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
8442885f | 1302 | cpudata->epp_policy = 0; |
984edbdc SP |
1303 | if (cpudata->epp_default == -EINVAL) |
1304 | cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); | |
2f86dc4c DB |
1305 | } |
1306 | ||
6e978b22 SP |
1307 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
1308 | ||
1309 | /* Disable energy efficiency optimization */ | |
1310 | static void intel_pstate_disable_ee(int cpu) | |
1311 | { | |
1312 | u64 power_ctl; | |
1313 | int ret; | |
1314 | ||
1315 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); | |
1316 | if (ret) | |
1317 | return; | |
1318 | ||
1319 | if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { | |
1320 | pr_info("Disabling energy efficiency optimization\n"); | |
1321 | power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); | |
1322 | wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); | |
1323 | } | |
1324 | } | |
1325 | ||
938d21a2 | 1326 | static int atom_get_min_pstate(void) |
19e77c28 DB |
1327 | { |
1328 | u64 value; | |
845c1cbe | 1329 | |
92134bdb | 1330 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1331 | return (value >> 8) & 0x7F; |
19e77c28 DB |
1332 | } |
1333 | ||
938d21a2 | 1334 | static int atom_get_max_pstate(void) |
19e77c28 DB |
1335 | { |
1336 | u64 value; | |
845c1cbe | 1337 | |
92134bdb | 1338 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1339 | return (value >> 16) & 0x7F; |
19e77c28 | 1340 | } |
93f0822d | 1341 | |
938d21a2 | 1342 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
1343 | { |
1344 | u64 value; | |
845c1cbe | 1345 | |
92134bdb | 1346 | rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); |
c16ed060 | 1347 | return value & 0x7F; |
61d8d2ab DB |
1348 | } |
1349 | ||
fdfdb2b1 | 1350 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
1351 | { |
1352 | u64 val; | |
1353 | int32_t vid_fp; | |
1354 | u32 vid; | |
1355 | ||
144c8e17 | 1356 | val = (u64)pstate << 8; |
7de32556 | 1357 | if (global.no_turbo && !global.turbo_disabled) |
007bea09 DB |
1358 | val |= (u64)1 << 32; |
1359 | ||
1360 | vid_fp = cpudata->vid.min + mul_fp( | |
1361 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
1362 | cpudata->vid.ratio); | |
1363 | ||
1364 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 1365 | vid = ceiling_fp(vid_fp); |
007bea09 | 1366 | |
21855ff5 DB |
1367 | if (pstate > cpudata->pstate.max_pstate) |
1368 | vid = cpudata->vid.turbo; | |
1369 | ||
fdfdb2b1 | 1370 | return val | vid; |
007bea09 DB |
1371 | } |
1372 | ||
1421df63 | 1373 | static int silvermont_get_scaling(void) |
b27580b0 DB |
1374 | { |
1375 | u64 value; | |
1376 | int i; | |
1421df63 PL |
1377 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
1378 | static int silvermont_freq_table[] = { | |
1379 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
1380 | |
1381 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
1382 | i = value & 0x7; |
1383 | WARN_ON(i > 4); | |
b27580b0 | 1384 | |
1421df63 PL |
1385 | return silvermont_freq_table[i]; |
1386 | } | |
b27580b0 | 1387 | |
1421df63 PL |
1388 | static int airmont_get_scaling(void) |
1389 | { | |
1390 | u64 value; | |
1391 | int i; | |
1392 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
1393 | static int airmont_freq_table[] = { | |
1394 | 83300, 100000, 133300, 116700, 80000, | |
1395 | 93300, 90000, 88900, 87500}; | |
1396 | ||
1397 | rdmsrl(MSR_FSB_FREQ, value); | |
1398 | i = value & 0xF; | |
1399 | WARN_ON(i > 8); | |
1400 | ||
1401 | return airmont_freq_table[i]; | |
b27580b0 DB |
1402 | } |
1403 | ||
938d21a2 | 1404 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
1405 | { |
1406 | u64 value; | |
1407 | ||
92134bdb | 1408 | rdmsrl(MSR_ATOM_CORE_VIDS, value); |
c16ed060 DB |
1409 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
1410 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
1411 | cpudata->vid.ratio = div_fp( |
1412 | cpudata->vid.max - cpudata->vid.min, | |
1413 | int_tofp(cpudata->pstate.max_pstate - | |
1414 | cpudata->pstate.min_pstate)); | |
21855ff5 | 1415 | |
92134bdb | 1416 | rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); |
21855ff5 | 1417 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
1418 | } |
1419 | ||
016c8150 | 1420 | static int core_get_min_pstate(void) |
93f0822d DB |
1421 | { |
1422 | u64 value; | |
845c1cbe | 1423 | |
05e99c8c | 1424 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1425 | return (value >> 40) & 0xFF; |
1426 | } | |
1427 | ||
3bcc6fa9 | 1428 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
1429 | { |
1430 | u64 value; | |
845c1cbe | 1431 | |
05e99c8c | 1432 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1433 | return (value >> 8) & 0xFF; |
1434 | } | |
1435 | ||
8fc7554a SP |
1436 | static int core_get_tdp_ratio(u64 plat_info) |
1437 | { | |
1438 | /* Check how many TDP levels present */ | |
1439 | if (plat_info & 0x600000000) { | |
1440 | u64 tdp_ctrl; | |
1441 | u64 tdp_ratio; | |
1442 | int tdp_msr; | |
1443 | int err; | |
1444 | ||
1445 | /* Get the TDP level (0, 1, 2) to get ratios */ | |
1446 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
1447 | if (err) | |
1448 | return err; | |
1449 | ||
1450 | /* TDP MSR are continuous starting at 0x648 */ | |
1451 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); | |
1452 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
1453 | if (err) | |
1454 | return err; | |
1455 | ||
1456 | /* For level 1 and 2, bits[23:16] contain the ratio */ | |
1457 | if (tdp_ctrl & 0x03) | |
1458 | tdp_ratio >>= 16; | |
1459 | ||
1460 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
1461 | pr_debug("tdp_ratio %x\n", (int)tdp_ratio); | |
1462 | ||
1463 | return (int)tdp_ratio; | |
1464 | } | |
1465 | ||
1466 | return -ENXIO; | |
1467 | } | |
1468 | ||
016c8150 | 1469 | static int core_get_max_pstate(void) |
93f0822d | 1470 | { |
6a35fc2d SP |
1471 | u64 tar; |
1472 | u64 plat_info; | |
1473 | int max_pstate; | |
8fc7554a | 1474 | int tdp_ratio; |
6a35fc2d SP |
1475 | int err; |
1476 | ||
1477 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
1478 | max_pstate = (plat_info >> 8) & 0xFF; | |
1479 | ||
8fc7554a SP |
1480 | tdp_ratio = core_get_tdp_ratio(plat_info); |
1481 | if (tdp_ratio <= 0) | |
1482 | return max_pstate; | |
1483 | ||
1484 | if (hwp_active) { | |
1485 | /* Turbo activation ratio is not used on HWP platforms */ | |
1486 | return tdp_ratio; | |
1487 | } | |
1488 | ||
6a35fc2d SP |
1489 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); |
1490 | if (!err) { | |
8fc7554a SP |
1491 | int tar_levels; |
1492 | ||
6a35fc2d | 1493 | /* Do some sanity checking for safety */ |
8fc7554a SP |
1494 | tar_levels = tar & 0xff; |
1495 | if (tdp_ratio - 1 == tar_levels) { | |
1496 | max_pstate = tar_levels; | |
1497 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
6a35fc2d SP |
1498 | } |
1499 | } | |
845c1cbe | 1500 | |
6a35fc2d | 1501 | return max_pstate; |
93f0822d DB |
1502 | } |
1503 | ||
016c8150 | 1504 | static int core_get_turbo_pstate(void) |
93f0822d DB |
1505 | { |
1506 | u64 value; | |
1507 | int nont, ret; | |
845c1cbe | 1508 | |
100cf6f2 | 1509 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 1510 | nont = core_get_max_pstate(); |
285cb990 | 1511 | ret = (value) & 255; |
93f0822d DB |
1512 | if (ret <= nont) |
1513 | ret = nont; | |
1514 | return ret; | |
1515 | } | |
1516 | ||
b27580b0 DB |
1517 | static inline int core_get_scaling(void) |
1518 | { | |
1519 | return 100000; | |
1520 | } | |
1521 | ||
fdfdb2b1 | 1522 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
1523 | { |
1524 | u64 val; | |
1525 | ||
144c8e17 | 1526 | val = (u64)pstate << 8; |
7de32556 | 1527 | if (global.no_turbo && !global.turbo_disabled) |
016c8150 DB |
1528 | val |= (u64)1 << 32; |
1529 | ||
fdfdb2b1 | 1530 | return val; |
016c8150 DB |
1531 | } |
1532 | ||
b34ef932 DC |
1533 | static int knl_get_turbo_pstate(void) |
1534 | { | |
1535 | u64 value; | |
1536 | int nont, ret; | |
1537 | ||
100cf6f2 | 1538 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1539 | nont = core_get_max_pstate(); |
1540 | ret = (((value) >> 8) & 0xFF); | |
1541 | if (ret <= nont) | |
1542 | ret = nont; | |
1543 | return ret; | |
1544 | } | |
1545 | ||
016c8150 DB |
1546 | static struct cpu_defaults core_params = { |
1547 | .pid_policy = { | |
1548 | .sample_rate_ms = 10, | |
1549 | .deadband = 0, | |
1550 | .setpoint = 97, | |
1551 | .p_gain_pct = 20, | |
1552 | .d_gain_pct = 0, | |
1553 | .i_gain_pct = 0, | |
1554 | }, | |
1555 | .funcs = { | |
1556 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1557 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
1558 | .get_min = core_get_min_pstate, |
1559 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 1560 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1561 | .get_val = core_get_val, |
157386b6 | 1562 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
1563 | }, |
1564 | }; | |
1565 | ||
42ce8921 | 1566 | static const struct cpu_defaults silvermont_params = { |
1421df63 PL |
1567 | .pid_policy = { |
1568 | .sample_rate_ms = 10, | |
1569 | .deadband = 0, | |
1570 | .setpoint = 60, | |
1571 | .p_gain_pct = 14, | |
1572 | .d_gain_pct = 0, | |
1573 | .i_gain_pct = 4, | |
1574 | }, | |
1575 | .funcs = { | |
1576 | .get_max = atom_get_max_pstate, | |
1577 | .get_max_physical = atom_get_max_pstate, | |
1578 | .get_min = atom_get_min_pstate, | |
1579 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1580 | .get_val = atom_get_val, |
1421df63 PL |
1581 | .get_scaling = silvermont_get_scaling, |
1582 | .get_vid = atom_get_vid, | |
e70eed2b | 1583 | .get_target_pstate = get_target_pstate_use_cpu_load, |
1421df63 PL |
1584 | }, |
1585 | }; | |
1586 | ||
42ce8921 | 1587 | static const struct cpu_defaults airmont_params = { |
19e77c28 DB |
1588 | .pid_policy = { |
1589 | .sample_rate_ms = 10, | |
1590 | .deadband = 0, | |
6a82ba6d | 1591 | .setpoint = 60, |
19e77c28 DB |
1592 | .p_gain_pct = 14, |
1593 | .d_gain_pct = 0, | |
1594 | .i_gain_pct = 4, | |
1595 | }, | |
1596 | .funcs = { | |
938d21a2 PL |
1597 | .get_max = atom_get_max_pstate, |
1598 | .get_max_physical = atom_get_max_pstate, | |
1599 | .get_min = atom_get_min_pstate, | |
1600 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1601 | .get_val = atom_get_val, |
1421df63 | 1602 | .get_scaling = airmont_get_scaling, |
938d21a2 | 1603 | .get_vid = atom_get_vid, |
e70eed2b | 1604 | .get_target_pstate = get_target_pstate_use_cpu_load, |
19e77c28 DB |
1605 | }, |
1606 | }; | |
1607 | ||
42ce8921 | 1608 | static const struct cpu_defaults knl_params = { |
b34ef932 DC |
1609 | .pid_policy = { |
1610 | .sample_rate_ms = 10, | |
1611 | .deadband = 0, | |
1612 | .setpoint = 97, | |
1613 | .p_gain_pct = 20, | |
1614 | .d_gain_pct = 0, | |
1615 | .i_gain_pct = 0, | |
1616 | }, | |
1617 | .funcs = { | |
1618 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1619 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
1620 | .get_min = core_get_min_pstate, |
1621 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 1622 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1623 | .get_val = core_get_val, |
157386b6 | 1624 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
1625 | }, |
1626 | }; | |
1627 | ||
42ce8921 | 1628 | static const struct cpu_defaults bxt_params = { |
41bad47f SP |
1629 | .pid_policy = { |
1630 | .sample_rate_ms = 10, | |
1631 | .deadband = 0, | |
1632 | .setpoint = 60, | |
1633 | .p_gain_pct = 14, | |
1634 | .d_gain_pct = 0, | |
1635 | .i_gain_pct = 4, | |
1636 | }, | |
1637 | .funcs = { | |
1638 | .get_max = core_get_max_pstate, | |
1639 | .get_max_physical = core_get_max_pstate_physical, | |
1640 | .get_min = core_get_min_pstate, | |
1641 | .get_turbo = core_get_turbo_pstate, | |
1642 | .get_scaling = core_get_scaling, | |
1643 | .get_val = core_get_val, | |
1644 | .get_target_pstate = get_target_pstate_use_cpu_load, | |
1645 | }, | |
1646 | }; | |
1647 | ||
93f0822d DB |
1648 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
1649 | { | |
1650 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 1651 | int max_perf_adj; |
93f0822d | 1652 | int min_perf; |
7de32556 | 1653 | struct perf_limits *perf_limits = &global; |
845c1cbe | 1654 | |
7de32556 | 1655 | if (global.no_turbo || global.turbo_disabled) |
93f0822d DB |
1656 | max_perf = cpu->pstate.max_pstate; |
1657 | ||
eae48f04 SP |
1658 | if (per_cpu_limits) |
1659 | perf_limits = cpu->perf_limits; | |
1660 | ||
e0d4c8f8 KCA |
1661 | /* |
1662 | * performance can be limited by user through sysfs, by cpufreq | |
1663 | * policy, or by cpu specific default values determined through | |
1664 | * experimentation. | |
1665 | */ | |
d5dd33d9 | 1666 | max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf); |
799281a3 RW |
1667 | *max = clamp_t(int, max_perf_adj, |
1668 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 1669 | |
d5dd33d9 | 1670 | min_perf = fp_ext_toint(max_perf * perf_limits->min_perf); |
799281a3 | 1671 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
1672 | } |
1673 | ||
a6c6ead1 | 1674 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1675 | { |
bc95a454 RW |
1676 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1677 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1678 | /* |
1679 | * Generally, there is no guarantee that this code will always run on | |
1680 | * the CPU being updated, so force the register update to run on the | |
1681 | * right CPU. | |
1682 | */ | |
1683 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1684 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1685 | } |
1686 | ||
a6c6ead1 RW |
1687 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1688 | { | |
1689 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); | |
1690 | } | |
1691 | ||
1692 | static void intel_pstate_max_within_limits(struct cpudata *cpu) | |
1693 | { | |
1694 | int min_pstate, max_pstate; | |
1695 | ||
1696 | update_turbo_state(); | |
1697 | intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); | |
1698 | intel_pstate_set_pstate(cpu, max_pstate); | |
1699 | } | |
1700 | ||
93f0822d DB |
1701 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1702 | { | |
016c8150 DB |
1703 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1704 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1705 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1706 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1707 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
001c76f0 RW |
1708 | cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; |
1709 | cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d | 1710 | |
007bea09 DB |
1711 | if (pstate_funcs.get_vid) |
1712 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1713 | |
1714 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1715 | } |
1716 | ||
a1c9787d | 1717 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1718 | { |
6b17ddb2 | 1719 | struct sample *sample = &cpu->sample; |
e66c1768 | 1720 | |
a1c9787d | 1721 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1722 | } |
1723 | ||
4fec7ad5 | 1724 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1725 | { |
93f0822d | 1726 | u64 aperf, mperf; |
4ab60c3f | 1727 | unsigned long flags; |
4055fad3 | 1728 | u64 tsc; |
93f0822d | 1729 | |
4ab60c3f | 1730 | local_irq_save(flags); |
93f0822d DB |
1731 | rdmsrl(MSR_IA32_APERF, aperf); |
1732 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1733 | tsc = rdtsc(); |
4fec7ad5 | 1734 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1735 | local_irq_restore(flags); |
4fec7ad5 | 1736 | return false; |
8e601a9f | 1737 | } |
4ab60c3f | 1738 | local_irq_restore(flags); |
b69880f9 | 1739 | |
c4ee841f | 1740 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1741 | cpu->sample.time = time; |
d37e2b76 DB |
1742 | cpu->sample.aperf = aperf; |
1743 | cpu->sample.mperf = mperf; | |
4055fad3 | 1744 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1745 | cpu->sample.aperf -= cpu->prev_aperf; |
1746 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1747 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1748 | |
93f0822d DB |
1749 | cpu->prev_aperf = aperf; |
1750 | cpu->prev_mperf = mperf; | |
4055fad3 | 1751 | cpu->prev_tsc = tsc; |
febce40f RW |
1752 | /* |
1753 | * First time this function is invoked in a given cycle, all of the | |
1754 | * previous sample data fields are equal to zero or stale and they must | |
1755 | * be populated with meaningful numbers for things to work, so assume | |
1756 | * that sample.time will always be reset before setting the utilization | |
1757 | * update hook and make the caller skip the sample then. | |
1758 | */ | |
1759 | return !!cpu->last_sample_time; | |
93f0822d DB |
1760 | } |
1761 | ||
8fa520af PL |
1762 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1763 | { | |
a1c9787d RW |
1764 | return mul_ext_fp(cpu->sample.core_avg_perf, |
1765 | cpu->pstate.max_pstate_physical * cpu->pstate.scaling); | |
8fa520af PL |
1766 | } |
1767 | ||
bdcaa23f PL |
1768 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1769 | { | |
8edb0a6e RW |
1770 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1771 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1772 | } |
1773 | ||
e70eed2b PL |
1774 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
1775 | { | |
1776 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1777 | int32_t busy_frac, boost; |
0843e83c | 1778 | int target, avg_pstate; |
e70eed2b | 1779 | |
09c448d3 | 1780 | busy_frac = div_fp(sample->mperf, sample->tsc); |
63d1d656 | 1781 | |
09c448d3 RW |
1782 | boost = cpu->iowait_boost; |
1783 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1784 | |
09c448d3 RW |
1785 | if (busy_frac < boost) |
1786 | busy_frac = boost; | |
63d1d656 | 1787 | |
09c448d3 | 1788 | sample->busy_scaled = busy_frac * 100; |
0843e83c | 1789 | |
7de32556 | 1790 | target = global.no_turbo || global.turbo_disabled ? |
0843e83c RW |
1791 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1792 | target += target >> 2; | |
1793 | target = mul_fp(target, busy_frac); | |
1794 | if (target < cpu->pstate.min_pstate) | |
1795 | target = cpu->pstate.min_pstate; | |
1796 | ||
1797 | /* | |
1798 | * If the average P-state during the previous cycle was higher than the | |
1799 | * current target, add 50% of the difference to the target to reduce | |
1800 | * possible performance oscillations and offset possible performance | |
1801 | * loss related to moving the workload from one CPU to another within | |
1802 | * a package/module. | |
1803 | */ | |
1804 | avg_pstate = get_avg_pstate(cpu); | |
1805 | if (avg_pstate > target) | |
1806 | target += (avg_pstate - target) >> 1; | |
1807 | ||
1808 | return target; | |
e70eed2b PL |
1809 | } |
1810 | ||
157386b6 | 1811 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 1812 | { |
1aa7a6e2 | 1813 | int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; |
a4675fbc | 1814 | u64 duration_ns; |
93f0822d | 1815 | |
e0d4c8f8 | 1816 | /* |
f00593a4 RW |
1817 | * perf_scaled is the ratio of the average P-state during the last |
1818 | * sampling period to the P-state requested last time (in percent). | |
1819 | * | |
1820 | * That measures the system's response to the previous P-state | |
1821 | * selection. | |
e0d4c8f8 | 1822 | */ |
22590efb RW |
1823 | max_pstate = cpu->pstate.max_pstate_physical; |
1824 | current_pstate = cpu->pstate.current_pstate; | |
1aa7a6e2 | 1825 | perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, |
a1c9787d | 1826 | div_fp(100 * max_pstate, current_pstate)); |
c4ee841f | 1827 | |
e0d4c8f8 | 1828 | /* |
a4675fbc RW |
1829 | * Since our utilization update callback will not run unless we are |
1830 | * in C0, check if the actual elapsed time is significantly greater (3x) | |
1831 | * than our sample interval. If it is, then we were idle for a long | |
1aa7a6e2 | 1832 | * enough period of time to adjust our performance metric. |
e0d4c8f8 | 1833 | */ |
a4675fbc | 1834 | duration_ns = cpu->sample.time - cpu->last_sample_time; |
febce40f | 1835 | if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { |
22590efb | 1836 | sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); |
1aa7a6e2 | 1837 | perf_scaled = mul_fp(perf_scaled, sample_ratio); |
ffb81056 RW |
1838 | } else { |
1839 | sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); | |
1840 | if (sample_ratio < int_tofp(1)) | |
1aa7a6e2 | 1841 | perf_scaled = 0; |
c4ee841f DB |
1842 | } |
1843 | ||
1aa7a6e2 RW |
1844 | cpu->sample.busy_scaled = perf_scaled; |
1845 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); | |
93f0822d DB |
1846 | } |
1847 | ||
001c76f0 | 1848 | static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) |
fdfdb2b1 RW |
1849 | { |
1850 | int max_perf, min_perf; | |
1851 | ||
fdfdb2b1 RW |
1852 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
1853 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
001c76f0 RW |
1854 | return pstate; |
1855 | } | |
1856 | ||
1857 | static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) | |
1858 | { | |
fdfdb2b1 RW |
1859 | if (pstate == cpu->pstate.current_pstate) |
1860 | return; | |
1861 | ||
bc95a454 | 1862 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1863 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1864 | } | |
1865 | ||
93f0822d DB |
1866 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) |
1867 | { | |
157386b6 | 1868 | int from, target_pstate; |
4055fad3 DS |
1869 | struct sample *sample; |
1870 | ||
1871 | from = cpu->pstate.current_pstate; | |
93f0822d | 1872 | |
2f1d407a RW |
1873 | target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ? |
1874 | cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu); | |
93f0822d | 1875 | |
001c76f0 RW |
1876 | update_turbo_state(); |
1877 | ||
64078299 RW |
1878 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
1879 | trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); | |
fdfdb2b1 | 1880 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1881 | |
1882 | sample = &cpu->sample; | |
a1c9787d | 1883 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1884 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1885 | from, |
1886 | cpu->pstate.current_pstate, | |
1887 | sample->mperf, | |
1888 | sample->aperf, | |
1889 | sample->tsc, | |
3ba7bcaa SP |
1890 | get_avg_frequency(cpu), |
1891 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1892 | } |
1893 | ||
a4675fbc | 1894 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1895 | unsigned int flags) |
93f0822d | 1896 | { |
a4675fbc | 1897 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1898 | u64 delta_ns; |
1899 | ||
1d29815e | 1900 | if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) { |
09c448d3 RW |
1901 | if (flags & SCHED_CPUFREQ_IOWAIT) { |
1902 | cpu->iowait_boost = int_tofp(1); | |
1903 | } else if (cpu->iowait_boost) { | |
1904 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1905 | delta_ns = time - cpu->last_update; | |
1906 | if (delta_ns > TICK_NSEC) | |
1907 | cpu->iowait_boost = 0; | |
1908 | } | |
1909 | cpu->last_update = time; | |
1910 | } | |
b69880f9 | 1911 | |
09c448d3 | 1912 | delta_ns = time - cpu->sample.time; |
a4675fbc | 1913 | if ((s64)delta_ns >= pid_params.sample_rate_ns) { |
4fec7ad5 RW |
1914 | bool sample_taken = intel_pstate_sample(cpu, time); |
1915 | ||
6d45b719 | 1916 | if (sample_taken) { |
a1c9787d | 1917 | intel_pstate_calc_avg_perf(cpu); |
6d45b719 RW |
1918 | if (!hwp_active) |
1919 | intel_pstate_adjust_busy_pstate(cpu); | |
1920 | } | |
a4675fbc | 1921 | } |
93f0822d DB |
1922 | } |
1923 | ||
1924 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1925 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1926 | (unsigned long)&policy } | |
93f0822d DB |
1927 | |
1928 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
5b20c944 DH |
1929 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), |
1930 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), | |
1931 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), | |
1932 | ICPU(INTEL_FAM6_IVYBRIDGE, core_params), | |
1933 | ICPU(INTEL_FAM6_HASWELL_CORE, core_params), | |
1934 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), | |
1935 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), | |
1936 | ICPU(INTEL_FAM6_HASWELL_X, core_params), | |
1937 | ICPU(INTEL_FAM6_HASWELL_ULT, core_params), | |
1938 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), | |
1939 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), | |
1940 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), | |
1941 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), | |
1942 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), | |
1943 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), | |
1944 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), | |
1945 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), | |
58bf4542 | 1946 | ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params), |
41bad47f | 1947 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), |
93f0822d DB |
1948 | {} |
1949 | }; | |
1950 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1951 | ||
29327c84 | 1952 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
5b20c944 | 1953 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), |
65c1262f SP |
1954 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), |
1955 | ICPU(INTEL_FAM6_SKYLAKE_X, core_params), | |
2f86dc4c DB |
1956 | {} |
1957 | }; | |
1958 | ||
6e978b22 SP |
1959 | static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { |
1960 | ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params), | |
1961 | {} | |
1962 | }; | |
1963 | ||
93f0822d DB |
1964 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1965 | { | |
93f0822d DB |
1966 | struct cpudata *cpu; |
1967 | ||
eae48f04 SP |
1968 | cpu = all_cpu_data[cpunum]; |
1969 | ||
1970 | if (!cpu) { | |
1971 | unsigned int size = sizeof(struct cpudata); | |
1972 | ||
1973 | if (per_cpu_limits) | |
1974 | size += sizeof(struct perf_limits); | |
1975 | ||
1976 | cpu = kzalloc(size, GFP_KERNEL); | |
1977 | if (!cpu) | |
1978 | return -ENOMEM; | |
1979 | ||
1980 | all_cpu_data[cpunum] = cpu; | |
1981 | if (per_cpu_limits) | |
1982 | cpu->perf_limits = (struct perf_limits *)(cpu + 1); | |
1983 | ||
984edbdc SP |
1984 | cpu->epp_default = -EINVAL; |
1985 | cpu->epp_powersave = -EINVAL; | |
1986 | cpu->epp_saved = -EINVAL; | |
eae48f04 | 1987 | } |
93f0822d DB |
1988 | |
1989 | cpu = all_cpu_data[cpunum]; | |
1990 | ||
93f0822d | 1991 | cpu->cpu = cpunum; |
ba88d433 | 1992 | |
a4675fbc | 1993 | if (hwp_active) { |
6e978b22 SP |
1994 | const struct x86_cpu_id *id; |
1995 | ||
1996 | id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); | |
1997 | if (id) | |
1998 | intel_pstate_disable_ee(cpunum); | |
1999 | ||
ba88d433 | 2000 | intel_pstate_hwp_enable(cpu); |
a4675fbc RW |
2001 | pid_params.sample_rate_ms = 50; |
2002 | pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; | |
2003 | } | |
ba88d433 | 2004 | |
179e8471 | 2005 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 2006 | |
93f0822d | 2007 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 2008 | |
4836df17 | 2009 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
2010 | |
2011 | return 0; | |
2012 | } | |
2013 | ||
2014 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
2015 | { | |
f96fd0c8 | 2016 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
93f0822d | 2017 | |
f96fd0c8 | 2018 | return cpu ? get_avg_frequency(cpu) : 0; |
93f0822d DB |
2019 | } |
2020 | ||
febce40f | 2021 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 2022 | { |
febce40f RW |
2023 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
2024 | ||
5ab666e0 RW |
2025 | if (cpu->update_util_set) |
2026 | return; | |
2027 | ||
febce40f RW |
2028 | /* Prevent intel_pstate_update_util() from using stale data. */ |
2029 | cpu->sample.time = 0; | |
0bed612b RW |
2030 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
2031 | intel_pstate_update_util); | |
4578ee7e | 2032 | cpu->update_util_set = true; |
bb6ab52f RW |
2033 | } |
2034 | ||
2035 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
2036 | { | |
4578ee7e CY |
2037 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
2038 | ||
2039 | if (!cpu_data->update_util_set) | |
2040 | return; | |
2041 | ||
0bed612b | 2042 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 2043 | cpu_data->update_util_set = false; |
bb6ab52f RW |
2044 | synchronize_sched(); |
2045 | } | |
2046 | ||
eae48f04 SP |
2047 | static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, |
2048 | struct perf_limits *limits) | |
2049 | { | |
e4c204ce | 2050 | int32_t max_policy_perf, min_policy_perf; |
a410c03d | 2051 | |
e4c204ce RW |
2052 | max_policy_perf = div_ext_fp(policy->max, policy->cpuinfo.max_freq); |
2053 | max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1)); | |
5879f877 | 2054 | if (policy->max == policy->min) { |
e4c204ce | 2055 | min_policy_perf = max_policy_perf; |
5879f877 | 2056 | } else { |
e4c204ce RW |
2057 | min_policy_perf = div_ext_fp(policy->min, |
2058 | policy->cpuinfo.max_freq); | |
2059 | min_policy_perf = clamp_t(int32_t, min_policy_perf, | |
2060 | 0, max_policy_perf); | |
5879f877 | 2061 | } |
eae48f04 | 2062 | |
e4c204ce RW |
2063 | /* Normalize user input to [min_perf, max_perf] */ |
2064 | limits->min_perf = max(min_policy_perf, | |
2065 | percent_ext_fp(limits->min_sysfs_pct)); | |
2066 | limits->min_perf = min(limits->min_perf, max_policy_perf); | |
2067 | limits->max_perf = min(max_policy_perf, | |
2068 | percent_ext_fp(limits->max_sysfs_pct)); | |
2069 | limits->max_perf = max(min_policy_perf, limits->max_perf); | |
eae48f04 | 2070 | |
e4c204ce RW |
2071 | /* Make sure min_perf <= max_perf */ |
2072 | limits->min_perf = min(limits->min_perf, limits->max_perf); | |
eae48f04 | 2073 | |
d5dd33d9 SP |
2074 | limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS); |
2075 | limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS); | |
e4c204ce RW |
2076 | limits->max_perf_pct = fp_ext_toint(limits->max_perf * 100); |
2077 | limits->min_perf_pct = fp_ext_toint(limits->min_perf * 100); | |
eae48f04 SP |
2078 | |
2079 | pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, | |
2080 | limits->max_perf_pct, limits->min_perf_pct); | |
2081 | } | |
2082 | ||
93f0822d DB |
2083 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
2084 | { | |
3be9200d | 2085 | struct cpudata *cpu; |
7de32556 | 2086 | struct perf_limits *perf_limits = &global; |
3be9200d | 2087 | |
d3929b83 DB |
2088 | if (!policy->cpuinfo.max_freq) |
2089 | return -ENODEV; | |
2090 | ||
2c2c1af4 SP |
2091 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
2092 | policy->cpuinfo.max_freq, policy->max); | |
2093 | ||
a6c6ead1 | 2094 | cpu = all_cpu_data[policy->cpu]; |
2f1d407a RW |
2095 | cpu->policy = policy->policy; |
2096 | ||
c749c64f RW |
2097 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && |
2098 | policy->max < policy->cpuinfo.max_freq && | |
2099 | policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { | |
2100 | pr_debug("policy->max > max non turbo frequency\n"); | |
2101 | policy->max = policy->cpuinfo.max_freq; | |
3be9200d SP |
2102 | } |
2103 | ||
eae48f04 SP |
2104 | if (per_cpu_limits) |
2105 | perf_limits = cpu->perf_limits; | |
2106 | ||
b59fe540 SP |
2107 | mutex_lock(&intel_pstate_limits_lock); |
2108 | ||
eae48f04 | 2109 | intel_pstate_update_perf_limits(policy, perf_limits); |
a240c4aa | 2110 | |
2f1d407a | 2111 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { |
a6c6ead1 RW |
2112 | /* |
2113 | * NOHZ_FULL CPUs need this as the governor callback may not | |
2114 | * be invoked on them. | |
2115 | */ | |
2116 | intel_pstate_clear_update_util_hook(policy->cpu); | |
2117 | intel_pstate_max_within_limits(cpu); | |
2118 | } | |
2119 | ||
bb6ab52f RW |
2120 | intel_pstate_set_update_util_hook(policy->cpu); |
2121 | ||
5f98ced1 RW |
2122 | if (hwp_active) |
2123 | intel_pstate_hwp_set(policy); | |
2f86dc4c | 2124 | |
b59fe540 SP |
2125 | mutex_unlock(&intel_pstate_limits_lock); |
2126 | ||
93f0822d DB |
2127 | return 0; |
2128 | } | |
2129 | ||
2130 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
2131 | { | |
7d9a8a9f | 2132 | struct cpudata *cpu = all_cpu_data[policy->cpu]; |
7d9a8a9f SP |
2133 | |
2134 | update_turbo_state(); | |
7de32556 | 2135 | policy->cpuinfo.max_freq = global.turbo_disabled || global.no_turbo ? |
7d9a8a9f SP |
2136 | cpu->pstate.max_freq : |
2137 | cpu->pstate.turbo_freq; | |
2138 | ||
be49e346 | 2139 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 2140 | |
285cb990 | 2141 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 2142 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
2143 | return -EINVAL; |
2144 | ||
1443ebba SP |
2145 | /* When per-CPU limits are used, sysfs limits are not used */ |
2146 | if (!per_cpu_limits) { | |
2147 | unsigned int max_freq, min_freq; | |
2148 | ||
2149 | max_freq = policy->cpuinfo.max_freq * | |
7de32556 | 2150 | global.max_sysfs_pct / 100; |
1443ebba | 2151 | min_freq = policy->cpuinfo.max_freq * |
7de32556 | 2152 | global.min_sysfs_pct / 100; |
1443ebba SP |
2153 | cpufreq_verify_within_limits(policy, min_freq, max_freq); |
2154 | } | |
2155 | ||
93f0822d DB |
2156 | return 0; |
2157 | } | |
2158 | ||
001c76f0 RW |
2159 | static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
2160 | { | |
2161 | intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); | |
2162 | } | |
2163 | ||
bb18008f | 2164 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 2165 | { |
001c76f0 | 2166 | pr_debug("CPU %d exiting\n", policy->cpu); |
93f0822d | 2167 | |
001c76f0 | 2168 | intel_pstate_clear_update_util_hook(policy->cpu); |
984edbdc SP |
2169 | if (hwp_active) |
2170 | intel_pstate_hwp_save_state(policy); | |
2171 | else | |
001c76f0 RW |
2172 | intel_cpufreq_stop_cpu(policy); |
2173 | } | |
bb18008f | 2174 | |
001c76f0 RW |
2175 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
2176 | { | |
2177 | intel_pstate_exit_perf_limits(policy); | |
a4675fbc | 2178 | |
001c76f0 | 2179 | policy->fast_switch_possible = false; |
2f86dc4c | 2180 | |
001c76f0 | 2181 | return 0; |
93f0822d DB |
2182 | } |
2183 | ||
001c76f0 | 2184 | static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 2185 | { |
93f0822d | 2186 | struct cpudata *cpu; |
52e0a509 | 2187 | int rc; |
93f0822d DB |
2188 | |
2189 | rc = intel_pstate_init_cpu(policy->cpu); | |
2190 | if (rc) | |
2191 | return rc; | |
2192 | ||
2193 | cpu = all_cpu_data[policy->cpu]; | |
2194 | ||
eae48f04 | 2195 | if (per_cpu_limits) |
a240c4aa | 2196 | intel_pstate_init_limits(cpu->perf_limits); |
93f0822d | 2197 | |
b27580b0 DB |
2198 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
2199 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
2200 | |
2201 | /* cpuinfo and default policy values */ | |
b27580b0 | 2202 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e | 2203 | update_turbo_state(); |
7de32556 | 2204 | policy->cpuinfo.max_freq = global.turbo_disabled ? |
983e600e SP |
2205 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
2206 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
2207 | ||
9522a2ff | 2208 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d DB |
2209 | cpumask_set_cpu(policy->cpu, policy->cpus); |
2210 | ||
001c76f0 RW |
2211 | policy->fast_switch_possible = true; |
2212 | ||
93f0822d DB |
2213 | return 0; |
2214 | } | |
2215 | ||
001c76f0 | 2216 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
9522a2ff | 2217 | { |
001c76f0 RW |
2218 | int ret = __intel_pstate_cpu_init(policy); |
2219 | ||
2220 | if (ret) | |
2221 | return ret; | |
2222 | ||
2223 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
7de32556 | 2224 | if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) |
001c76f0 RW |
2225 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
2226 | else | |
2227 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
9522a2ff SP |
2228 | |
2229 | return 0; | |
2230 | } | |
2231 | ||
001c76f0 | 2232 | static struct cpufreq_driver intel_pstate = { |
93f0822d DB |
2233 | .flags = CPUFREQ_CONST_LOOPS, |
2234 | .verify = intel_pstate_verify_policy, | |
2235 | .setpolicy = intel_pstate_set_policy, | |
984edbdc | 2236 | .suspend = intel_pstate_hwp_save_state, |
8442885f | 2237 | .resume = intel_pstate_resume, |
93f0822d DB |
2238 | .get = intel_pstate_get, |
2239 | .init = intel_pstate_cpu_init, | |
9522a2ff | 2240 | .exit = intel_pstate_cpu_exit, |
bb18008f | 2241 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 2242 | .name = "intel_pstate", |
93f0822d DB |
2243 | }; |
2244 | ||
001c76f0 RW |
2245 | static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) |
2246 | { | |
2247 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
001c76f0 RW |
2248 | |
2249 | update_turbo_state(); | |
64897b20 | 2250 | policy->cpuinfo.max_freq = global.no_turbo || global.turbo_disabled ? |
001c76f0 RW |
2251 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; |
2252 | ||
2253 | cpufreq_verify_within_cpu_limits(policy); | |
2254 | ||
001c76f0 RW |
2255 | return 0; |
2256 | } | |
2257 | ||
001c76f0 RW |
2258 | static int intel_cpufreq_target(struct cpufreq_policy *policy, |
2259 | unsigned int target_freq, | |
2260 | unsigned int relation) | |
2261 | { | |
2262 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2263 | struct cpufreq_freqs freqs; | |
2264 | int target_pstate; | |
2265 | ||
64897b20 RW |
2266 | update_turbo_state(); |
2267 | ||
001c76f0 | 2268 | freqs.old = policy->cur; |
64897b20 | 2269 | freqs.new = target_freq; |
001c76f0 RW |
2270 | |
2271 | cpufreq_freq_transition_begin(policy, &freqs); | |
2272 | switch (relation) { | |
2273 | case CPUFREQ_RELATION_L: | |
2274 | target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
2275 | break; | |
2276 | case CPUFREQ_RELATION_H: | |
2277 | target_pstate = freqs.new / cpu->pstate.scaling; | |
2278 | break; | |
2279 | default: | |
2280 | target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
2281 | break; | |
2282 | } | |
2283 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); | |
2284 | if (target_pstate != cpu->pstate.current_pstate) { | |
2285 | cpu->pstate.current_pstate = target_pstate; | |
2286 | wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, | |
2287 | pstate_funcs.get_val(cpu, target_pstate)); | |
2288 | } | |
64078299 | 2289 | freqs.new = target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2290 | cpufreq_freq_transition_end(policy, &freqs, false); |
2291 | ||
2292 | return 0; | |
2293 | } | |
2294 | ||
2295 | static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, | |
2296 | unsigned int target_freq) | |
2297 | { | |
2298 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2299 | int target_pstate; | |
2300 | ||
64897b20 RW |
2301 | update_turbo_state(); |
2302 | ||
001c76f0 | 2303 | target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); |
64078299 | 2304 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
001c76f0 | 2305 | intel_pstate_update_pstate(cpu, target_pstate); |
64078299 | 2306 | return target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2307 | } |
2308 | ||
2309 | static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
2310 | { | |
2311 | int ret = __intel_pstate_cpu_init(policy); | |
2312 | ||
2313 | if (ret) | |
2314 | return ret; | |
2315 | ||
2316 | policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; | |
2317 | /* This reflects the intel_pstate_get_cpu_pstates() setting. */ | |
2318 | policy->cur = policy->cpuinfo.min_freq; | |
2319 | ||
2320 | return 0; | |
2321 | } | |
2322 | ||
2323 | static struct cpufreq_driver intel_cpufreq = { | |
2324 | .flags = CPUFREQ_CONST_LOOPS, | |
2325 | .verify = intel_cpufreq_verify_policy, | |
2326 | .target = intel_cpufreq_target, | |
2327 | .fast_switch = intel_cpufreq_fast_switch, | |
2328 | .init = intel_cpufreq_cpu_init, | |
2329 | .exit = intel_pstate_cpu_exit, | |
2330 | .stop_cpu = intel_cpufreq_stop_cpu, | |
2331 | .name = "intel_cpufreq", | |
2332 | }; | |
2333 | ||
2334 | static struct cpufreq_driver *intel_pstate_driver = &intel_pstate; | |
2335 | ||
fb1fe104 RW |
2336 | static void intel_pstate_driver_cleanup(void) |
2337 | { | |
2338 | unsigned int cpu; | |
2339 | ||
2340 | get_online_cpus(); | |
2341 | for_each_online_cpu(cpu) { | |
2342 | if (all_cpu_data[cpu]) { | |
2343 | if (intel_pstate_driver == &intel_pstate) | |
2344 | intel_pstate_clear_update_util_hook(cpu); | |
2345 | ||
2346 | kfree(all_cpu_data[cpu]); | |
2347 | all_cpu_data[cpu] = NULL; | |
2348 | } | |
2349 | } | |
2350 | put_online_cpus(); | |
2351 | } | |
2352 | ||
2353 | static int intel_pstate_register_driver(void) | |
2354 | { | |
2355 | int ret; | |
2356 | ||
7de32556 | 2357 | intel_pstate_init_limits(&global); |
c3a49c89 | 2358 | |
fb1fe104 RW |
2359 | ret = cpufreq_register_driver(intel_pstate_driver); |
2360 | if (ret) { | |
2361 | intel_pstate_driver_cleanup(); | |
2362 | return ret; | |
2363 | } | |
2364 | ||
2365 | mutex_lock(&intel_pstate_limits_lock); | |
2366 | driver_registered = true; | |
2367 | mutex_unlock(&intel_pstate_limits_lock); | |
2368 | ||
2369 | if (intel_pstate_driver == &intel_pstate && !hwp_active && | |
2370 | pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load) | |
2371 | intel_pstate_debug_expose_params(); | |
2372 | ||
2373 | return 0; | |
2374 | } | |
2375 | ||
2376 | static int intel_pstate_unregister_driver(void) | |
2377 | { | |
2378 | if (hwp_active) | |
2379 | return -EBUSY; | |
2380 | ||
2381 | if (intel_pstate_driver == &intel_pstate && !hwp_active && | |
2382 | pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load) | |
2383 | intel_pstate_debug_hide_params(); | |
2384 | ||
2385 | mutex_lock(&intel_pstate_limits_lock); | |
2386 | driver_registered = false; | |
2387 | mutex_unlock(&intel_pstate_limits_lock); | |
2388 | ||
2389 | cpufreq_unregister_driver(intel_pstate_driver); | |
2390 | intel_pstate_driver_cleanup(); | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
2395 | static ssize_t intel_pstate_show_status(char *buf) | |
2396 | { | |
2397 | if (!driver_registered) | |
2398 | return sprintf(buf, "off\n"); | |
2399 | ||
2400 | return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? | |
2401 | "active" : "passive"); | |
2402 | } | |
2403 | ||
2404 | static int intel_pstate_update_status(const char *buf, size_t size) | |
2405 | { | |
2406 | int ret; | |
2407 | ||
2408 | if (size == 3 && !strncmp(buf, "off", size)) | |
2409 | return driver_registered ? | |
2410 | intel_pstate_unregister_driver() : -EINVAL; | |
2411 | ||
2412 | if (size == 6 && !strncmp(buf, "active", size)) { | |
2413 | if (driver_registered) { | |
2414 | if (intel_pstate_driver == &intel_pstate) | |
2415 | return 0; | |
2416 | ||
2417 | ret = intel_pstate_unregister_driver(); | |
2418 | if (ret) | |
2419 | return ret; | |
2420 | } | |
2421 | ||
2422 | intel_pstate_driver = &intel_pstate; | |
2423 | return intel_pstate_register_driver(); | |
2424 | } | |
2425 | ||
2426 | if (size == 7 && !strncmp(buf, "passive", size)) { | |
2427 | if (driver_registered) { | |
2428 | if (intel_pstate_driver != &intel_pstate) | |
2429 | return 0; | |
2430 | ||
2431 | ret = intel_pstate_unregister_driver(); | |
2432 | if (ret) | |
2433 | return ret; | |
2434 | } | |
2435 | ||
2436 | intel_pstate_driver = &intel_cpufreq; | |
2437 | return intel_pstate_register_driver(); | |
2438 | } | |
2439 | ||
2440 | return -EINVAL; | |
2441 | } | |
2442 | ||
eed43609 JZ |
2443 | static int no_load __initdata; |
2444 | static int no_hwp __initdata; | |
2445 | static int hwp_only __initdata; | |
29327c84 | 2446 | static unsigned int force_load __initdata; |
6be26498 | 2447 | |
29327c84 | 2448 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 2449 | { |
016c8150 | 2450 | if (!pstate_funcs.get_max() || |
c410833a SK |
2451 | !pstate_funcs.get_min() || |
2452 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
2453 | return -ENODEV; |
2454 | ||
b563b4e3 DB |
2455 | return 0; |
2456 | } | |
016c8150 | 2457 | |
29327c84 | 2458 | static void __init copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
2459 | { |
2460 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
a4675fbc | 2461 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
016c8150 DB |
2462 | pid_params.p_gain_pct = policy->p_gain_pct; |
2463 | pid_params.i_gain_pct = policy->i_gain_pct; | |
2464 | pid_params.d_gain_pct = policy->d_gain_pct; | |
2465 | pid_params.deadband = policy->deadband; | |
2466 | pid_params.setpoint = policy->setpoint; | |
2467 | } | |
2468 | ||
7f7a516e SP |
2469 | #ifdef CONFIG_ACPI |
2470 | static void intel_pstate_use_acpi_profile(void) | |
2471 | { | |
55395345 RW |
2472 | switch (acpi_gbl_FADT.preferred_profile) { |
2473 | case PM_MOBILE: | |
2474 | case PM_TABLET: | |
2475 | case PM_APPLIANCE_PC: | |
2476 | case PM_DESKTOP: | |
2477 | case PM_WORKSTATION: | |
7f7a516e SP |
2478 | pstate_funcs.get_target_pstate = |
2479 | get_target_pstate_use_cpu_load; | |
55395345 | 2480 | } |
7f7a516e SP |
2481 | } |
2482 | #else | |
2483 | static void intel_pstate_use_acpi_profile(void) | |
2484 | { | |
2485 | } | |
2486 | #endif | |
2487 | ||
29327c84 | 2488 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
2489 | { |
2490 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 2491 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
2492 | pstate_funcs.get_min = funcs->get_min; |
2493 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 2494 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 2495 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 2496 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
2497 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
2498 | ||
7f7a516e | 2499 | intel_pstate_use_acpi_profile(); |
016c8150 DB |
2500 | } |
2501 | ||
9522a2ff | 2502 | #ifdef CONFIG_ACPI |
fbbcdc07 | 2503 | |
29327c84 | 2504 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
2505 | { |
2506 | int i; | |
2507 | ||
2508 | for_each_possible_cpu(i) { | |
2509 | acpi_status status; | |
2510 | union acpi_object *pss; | |
2511 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
2512 | struct acpi_processor *pr = per_cpu(processors, i); | |
2513 | ||
2514 | if (!pr) | |
2515 | continue; | |
2516 | ||
2517 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
2518 | if (ACPI_FAILURE(status)) | |
2519 | continue; | |
2520 | ||
2521 | pss = buffer.pointer; | |
2522 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
2523 | kfree(pss); | |
2524 | return false; | |
2525 | } | |
2526 | ||
2527 | kfree(pss); | |
2528 | } | |
2529 | ||
2530 | return true; | |
2531 | } | |
2532 | ||
29327c84 | 2533 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 2534 | { |
2535 | int i; | |
2536 | ||
2537 | for_each_possible_cpu(i) { | |
2538 | struct acpi_processor *pr = per_cpu(processors, i); | |
2539 | ||
2540 | if (!pr) | |
2541 | continue; | |
2542 | if (acpi_has_method(pr->handle, "_PPC")) | |
2543 | return true; | |
2544 | } | |
2545 | return false; | |
2546 | } | |
2547 | ||
2548 | enum { | |
2549 | PSS, | |
2550 | PPC, | |
2551 | }; | |
2552 | ||
fbbcdc07 AH |
2553 | struct hw_vendor_info { |
2554 | u16 valid; | |
2555 | char oem_id[ACPI_OEM_ID_SIZE]; | |
2556 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 2557 | int oem_pwr_table; |
fbbcdc07 AH |
2558 | }; |
2559 | ||
2560 | /* Hardware vendor-specific info that has its own power management modes */ | |
29327c84 | 2561 | static struct hw_vendor_info vendor_info[] __initdata = { |
966916ea | 2562 | {1, "HP ", "ProLiant", PSS}, |
2563 | {1, "ORACLE", "X4-2 ", PPC}, | |
2564 | {1, "ORACLE", "X4-2L ", PPC}, | |
2565 | {1, "ORACLE", "X4-2B ", PPC}, | |
2566 | {1, "ORACLE", "X3-2 ", PPC}, | |
2567 | {1, "ORACLE", "X3-2L ", PPC}, | |
2568 | {1, "ORACLE", "X3-2B ", PPC}, | |
2569 | {1, "ORACLE", "X4470M2 ", PPC}, | |
2570 | {1, "ORACLE", "X4270M3 ", PPC}, | |
2571 | {1, "ORACLE", "X4270M2 ", PPC}, | |
2572 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
2573 | {1, "ORACLE", "X4170 M3", PPC}, |
2574 | {1, "ORACLE", "X4275 M3", PPC}, | |
2575 | {1, "ORACLE", "X6-2 ", PPC}, | |
2576 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
2577 | {0, "", ""}, |
2578 | }; | |
2579 | ||
29327c84 | 2580 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 AH |
2581 | { |
2582 | struct acpi_table_header hdr; | |
2583 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
2584 | const struct x86_cpu_id *id; |
2585 | u64 misc_pwr; | |
2586 | ||
2587 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
2588 | if (id) { | |
2589 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
2590 | if ( misc_pwr & (1 << 8)) | |
2591 | return true; | |
2592 | } | |
fbbcdc07 | 2593 | |
c410833a SK |
2594 | if (acpi_disabled || |
2595 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
2596 | return false; |
2597 | ||
2598 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 2599 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 2600 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
2601 | ACPI_OEM_TABLE_ID_SIZE)) | |
2602 | switch (v_info->oem_pwr_table) { | |
2603 | case PSS: | |
2604 | return intel_pstate_no_acpi_pss(); | |
2605 | case PPC: | |
aa4ea34d EZ |
2606 | return intel_pstate_has_acpi_ppc() && |
2607 | (!force_load); | |
966916ea | 2608 | } |
fbbcdc07 AH |
2609 | } |
2610 | ||
2611 | return false; | |
2612 | } | |
d0ea59e1 RW |
2613 | |
2614 | static void intel_pstate_request_control_from_smm(void) | |
2615 | { | |
2616 | /* | |
2617 | * It may be unsafe to request P-states control from SMM if _PPC support | |
2618 | * has not been enabled. | |
2619 | */ | |
2620 | if (acpi_ppc) | |
2621 | acpi_processor_pstate_control(); | |
2622 | } | |
fbbcdc07 AH |
2623 | #else /* CONFIG_ACPI not enabled */ |
2624 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 2625 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
d0ea59e1 | 2626 | static inline void intel_pstate_request_control_from_smm(void) {} |
fbbcdc07 AH |
2627 | #endif /* CONFIG_ACPI */ |
2628 | ||
7791e4aa SP |
2629 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
2630 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
2631 | {} | |
2632 | }; | |
2633 | ||
93f0822d DB |
2634 | static int __init intel_pstate_init(void) |
2635 | { | |
eb5139d1 | 2636 | int rc; |
93f0822d | 2637 | |
6be26498 DB |
2638 | if (no_load) |
2639 | return -ENODEV; | |
2640 | ||
eb5139d1 | 2641 | if (x86_match_cpu(hwp_support_ids)) { |
7791e4aa | 2642 | copy_cpu_funcs(&core_params.funcs); |
eb5139d1 RW |
2643 | if (no_hwp) { |
2644 | pstate_funcs.get_target_pstate = get_target_pstate_use_cpu_load; | |
2645 | } else { | |
2646 | hwp_active++; | |
2647 | intel_pstate.attr = hwp_cpufreq_attrs; | |
2648 | goto hwp_cpu_matched; | |
2649 | } | |
2650 | } else { | |
2651 | const struct x86_cpu_id *id; | |
2652 | struct cpu_defaults *cpu_def; | |
7791e4aa | 2653 | |
eb5139d1 RW |
2654 | id = x86_match_cpu(intel_pstate_cpu_ids); |
2655 | if (!id) | |
2656 | return -ENODEV; | |
93f0822d | 2657 | |
eb5139d1 | 2658 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 2659 | |
eb5139d1 RW |
2660 | copy_pid_params(&cpu_def->pid_policy); |
2661 | copy_cpu_funcs(&cpu_def->funcs); | |
2662 | } | |
016c8150 | 2663 | |
b563b4e3 DB |
2664 | if (intel_pstate_msrs_not_valid()) |
2665 | return -ENODEV; | |
2666 | ||
7791e4aa SP |
2667 | hwp_cpu_matched: |
2668 | /* | |
2669 | * The Intel pstate driver will be ignored if the platform | |
2670 | * firmware has its own power management modes. | |
2671 | */ | |
2672 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
2673 | return -ENODEV; | |
2674 | ||
fb1fe104 RW |
2675 | if (!hwp_active && hwp_only) |
2676 | return -ENOTSUPP; | |
2677 | ||
4836df17 | 2678 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 2679 | |
b57ffac5 | 2680 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
2681 | if (!all_cpu_data) |
2682 | return -ENOMEM; | |
93f0822d | 2683 | |
d0ea59e1 RW |
2684 | intel_pstate_request_control_from_smm(); |
2685 | ||
93f0822d | 2686 | intel_pstate_sysfs_expose_params(); |
b69880f9 | 2687 | |
0c30b65b | 2688 | mutex_lock(&intel_pstate_driver_lock); |
fb1fe104 | 2689 | rc = intel_pstate_register_driver(); |
0c30b65b | 2690 | mutex_unlock(&intel_pstate_driver_lock); |
fb1fe104 RW |
2691 | if (rc) |
2692 | return rc; | |
366430b5 | 2693 | |
7791e4aa | 2694 | if (hwp_active) |
4836df17 | 2695 | pr_info("HWP enabled\n"); |
7791e4aa | 2696 | |
fb1fe104 | 2697 | return 0; |
93f0822d DB |
2698 | } |
2699 | device_initcall(intel_pstate_init); | |
2700 | ||
6be26498 DB |
2701 | static int __init intel_pstate_setup(char *str) |
2702 | { | |
2703 | if (!str) | |
2704 | return -EINVAL; | |
2705 | ||
001c76f0 | 2706 | if (!strcmp(str, "disable")) { |
6be26498 | 2707 | no_load = 1; |
001c76f0 RW |
2708 | } else if (!strcmp(str, "passive")) { |
2709 | pr_info("Passive mode enabled\n"); | |
2710 | intel_pstate_driver = &intel_cpufreq; | |
2711 | no_hwp = 1; | |
2712 | } | |
539342f6 | 2713 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 2714 | pr_info("HWP disabled\n"); |
2f86dc4c | 2715 | no_hwp = 1; |
539342f6 | 2716 | } |
aa4ea34d EZ |
2717 | if (!strcmp(str, "force")) |
2718 | force_load = 1; | |
d64c3b0b KCA |
2719 | if (!strcmp(str, "hwp_only")) |
2720 | hwp_only = 1; | |
eae48f04 SP |
2721 | if (!strcmp(str, "per_cpu_perf_limits")) |
2722 | per_cpu_limits = true; | |
9522a2ff SP |
2723 | |
2724 | #ifdef CONFIG_ACPI | |
2725 | if (!strcmp(str, "support_acpi_ppc")) | |
2726 | acpi_ppc = true; | |
2727 | #endif | |
2728 | ||
6be26498 DB |
2729 | return 0; |
2730 | } | |
2731 | early_param("intel_pstate", intel_pstate_setup); | |
2732 | ||
93f0822d DB |
2733 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
2734 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
2735 | MODULE_LICENSE("GPL"); |