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93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB
3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
13#include <linux/kernel.h>
14#include <linux/kernel_stat.h>
15#include <linux/module.h>
16#include <linux/ktime.h>
17#include <linux/hrtimer.h>
18#include <linux/tick.h>
19#include <linux/slab.h>
20#include <linux/sched.h>
21#include <linux/list.h>
22#include <linux/cpu.h>
23#include <linux/cpufreq.h>
24#include <linux/sysfs.h>
25#include <linux/types.h>
26#include <linux/fs.h>
27#include <linux/debugfs.h>
fbbcdc07 28#include <linux/acpi.h>
93f0822d
DB
29#include <trace/events/power.h>
30
31#include <asm/div64.h>
32#include <asm/msr.h>
33#include <asm/cpu_device_id.h>
34
61d8d2ab
DB
35#define BYT_RATIOS 0x66a
36#define BYT_VIDS 0x66b
37#define BYT_TURBO_RATIOS 0x66c
38
19e77c28 39
e66c1768 40#define FRAC_BITS 6
93f0822d
DB
41#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
42#define fp_toint(X) ((X) >> FRAC_BITS)
e66c1768 43#define FP_ROUNDUP(X) ((X) += 1 << FRAC_BITS)
93f0822d
DB
44
45static inline int32_t mul_fp(int32_t x, int32_t y)
46{
47 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
48}
49
50static inline int32_t div_fp(int32_t x, int32_t y)
51{
52 return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);
53}
54
55struct sample {
d253d2a5 56 int32_t core_pct_busy;
93f0822d
DB
57 u64 aperf;
58 u64 mperf;
fcb6a15c 59 unsigned long long tsc;
93f0822d
DB
60 int freq;
61};
62
63struct pstate_data {
64 int current_pstate;
65 int min_pstate;
66 int max_pstate;
67 int turbo_pstate;
68};
69
007bea09
DB
70struct vid_data {
71 int32_t min;
72 int32_t max;
73 int32_t ratio;
74};
75
93f0822d
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76struct _pid {
77 int setpoint;
78 int32_t integral;
79 int32_t p_gain;
80 int32_t i_gain;
81 int32_t d_gain;
82 int deadband;
d253d2a5 83 int32_t last_err;
93f0822d
DB
84};
85
86struct cpudata {
87 int cpu;
88
89 char name[64];
90
91 struct timer_list timer;
92
93f0822d 93 struct pstate_data pstate;
007bea09 94 struct vid_data vid;
93f0822d 95 struct _pid pid;
93f0822d 96
93f0822d
DB
97 u64 prev_aperf;
98 u64 prev_mperf;
fcb6a15c 99 unsigned long long prev_tsc;
d37e2b76 100 struct sample sample;
93f0822d
DB
101};
102
103static struct cpudata **all_cpu_data;
104struct pstate_adjust_policy {
105 int sample_rate_ms;
106 int deadband;
107 int setpoint;
108 int p_gain_pct;
109 int d_gain_pct;
110 int i_gain_pct;
111};
112
016c8150
DB
113struct pstate_funcs {
114 int (*get_max)(void);
115 int (*get_min)(void);
116 int (*get_turbo)(void);
007bea09
DB
117 void (*set)(struct cpudata*, int pstate);
118 void (*get_vid)(struct cpudata *);
93f0822d
DB
119};
120
016c8150
DB
121struct cpu_defaults {
122 struct pstate_adjust_policy pid_policy;
123 struct pstate_funcs funcs;
93f0822d
DB
124};
125
016c8150
DB
126static struct pstate_adjust_policy pid_params;
127static struct pstate_funcs pstate_funcs;
128
93f0822d
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129struct perf_limits {
130 int no_turbo;
131 int max_perf_pct;
132 int min_perf_pct;
133 int32_t max_perf;
134 int32_t min_perf;
d8f469e9
DB
135 int max_policy_pct;
136 int max_sysfs_pct;
93f0822d
DB
137};
138
139static struct perf_limits limits = {
140 .no_turbo = 0,
141 .max_perf_pct = 100,
142 .max_perf = int_tofp(1),
143 .min_perf_pct = 0,
144 .min_perf = 0,
d8f469e9
DB
145 .max_policy_pct = 100,
146 .max_sysfs_pct = 100,
93f0822d
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147};
148
149static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
150 int deadband, int integral) {
151 pid->setpoint = setpoint;
152 pid->deadband = deadband;
153 pid->integral = int_tofp(integral);
d98d099b 154 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB
155}
156
157static inline void pid_p_gain_set(struct _pid *pid, int percent)
158{
159 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
160}
161
162static inline void pid_i_gain_set(struct _pid *pid, int percent)
163{
164 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
165}
166
167static inline void pid_d_gain_set(struct _pid *pid, int percent)
168{
169
170 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
171}
172
d253d2a5 173static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 174{
d253d2a5 175 signed int result;
93f0822d
DB
176 int32_t pterm, dterm, fp_error;
177 int32_t integral_limit;
178
d253d2a5 179 fp_error = int_tofp(pid->setpoint) - busy;
93f0822d 180
d253d2a5 181 if (abs(fp_error) <= int_tofp(pid->deadband))
93f0822d
DB
182 return 0;
183
184 pterm = mul_fp(pid->p_gain, fp_error);
185
186 pid->integral += fp_error;
187
188 /* limit the integral term */
189 integral_limit = int_tofp(30);
190 if (pid->integral > integral_limit)
191 pid->integral = integral_limit;
192 if (pid->integral < -integral_limit)
193 pid->integral = -integral_limit;
194
d253d2a5
BS
195 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
196 pid->last_err = fp_error;
93f0822d
DB
197
198 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
199
200 return (signed int)fp_toint(result);
201}
202
203static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
204{
016c8150
DB
205 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
206 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
207 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d
DB
208
209 pid_reset(&cpu->pid,
016c8150 210 pid_params.setpoint,
93f0822d 211 100,
016c8150 212 pid_params.deadband,
93f0822d
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213 0);
214}
215
93f0822d
DB
216static inline void intel_pstate_reset_all_pid(void)
217{
218 unsigned int cpu;
219 for_each_online_cpu(cpu) {
220 if (all_cpu_data[cpu])
221 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
222 }
223}
224
225/************************** debugfs begin ************************/
226static int pid_param_set(void *data, u64 val)
227{
228 *(u32 *)data = val;
229 intel_pstate_reset_all_pid();
230 return 0;
231}
232static int pid_param_get(void *data, u64 *val)
233{
234 *val = *(u32 *)data;
235 return 0;
236}
237DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,
238 pid_param_set, "%llu\n");
239
240struct pid_param {
241 char *name;
242 void *value;
243};
244
245static struct pid_param pid_files[] = {
016c8150
DB
246 {"sample_rate_ms", &pid_params.sample_rate_ms},
247 {"d_gain_pct", &pid_params.d_gain_pct},
248 {"i_gain_pct", &pid_params.i_gain_pct},
249 {"deadband", &pid_params.deadband},
250 {"setpoint", &pid_params.setpoint},
251 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
DB
252 {NULL, NULL}
253};
254
255static struct dentry *debugfs_parent;
256static void intel_pstate_debug_expose_params(void)
257{
258 int i = 0;
259
260 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
261 if (IS_ERR_OR_NULL(debugfs_parent))
262 return;
263 while (pid_files[i].name) {
264 debugfs_create_file(pid_files[i].name, 0660,
265 debugfs_parent, pid_files[i].value,
266 &fops_pid_param);
267 i++;
268 }
269}
270
271/************************** debugfs end ************************/
272
273/************************** sysfs begin ************************/
274#define show_one(file_name, object) \
275 static ssize_t show_##file_name \
276 (struct kobject *kobj, struct attribute *attr, char *buf) \
277 { \
278 return sprintf(buf, "%u\n", limits.object); \
279 }
280
281static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
282 const char *buf, size_t count)
283{
284 unsigned int input;
285 int ret;
286 ret = sscanf(buf, "%u", &input);
287 if (ret != 1)
288 return -EINVAL;
289 limits.no_turbo = clamp_t(int, input, 0 , 1);
290
291 return count;
292}
293
294static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
295 const char *buf, size_t count)
296{
297 unsigned int input;
298 int ret;
299 ret = sscanf(buf, "%u", &input);
300 if (ret != 1)
301 return -EINVAL;
302
d8f469e9
DB
303 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
304 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
93f0822d
DB
305 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
306 return count;
307}
308
309static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
310 const char *buf, size_t count)
311{
312 unsigned int input;
313 int ret;
314 ret = sscanf(buf, "%u", &input);
315 if (ret != 1)
316 return -EINVAL;
317 limits.min_perf_pct = clamp_t(int, input, 0 , 100);
318 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
319
320 return count;
321}
322
323show_one(no_turbo, no_turbo);
324show_one(max_perf_pct, max_perf_pct);
325show_one(min_perf_pct, min_perf_pct);
326
327define_one_global_rw(no_turbo);
328define_one_global_rw(max_perf_pct);
329define_one_global_rw(min_perf_pct);
330
331static struct attribute *intel_pstate_attributes[] = {
332 &no_turbo.attr,
333 &max_perf_pct.attr,
334 &min_perf_pct.attr,
335 NULL
336};
337
338static struct attribute_group intel_pstate_attr_group = {
339 .attrs = intel_pstate_attributes,
340};
341static struct kobject *intel_pstate_kobject;
342
343static void intel_pstate_sysfs_expose_params(void)
344{
345 int rc;
346
347 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
348 &cpu_subsys.dev_root->kobj);
349 BUG_ON(!intel_pstate_kobject);
350 rc = sysfs_create_group(intel_pstate_kobject,
351 &intel_pstate_attr_group);
352 BUG_ON(rc);
353}
354
355/************************** sysfs end ************************/
19e77c28
DB
356static int byt_get_min_pstate(void)
357{
358 u64 value;
359 rdmsrl(BYT_RATIOS, value);
4042e757 360 return (value >> 8) & 0xFF;
19e77c28
DB
361}
362
363static int byt_get_max_pstate(void)
364{
365 u64 value;
366 rdmsrl(BYT_RATIOS, value);
367 return (value >> 16) & 0xFF;
368}
93f0822d 369
61d8d2ab
DB
370static int byt_get_turbo_pstate(void)
371{
372 u64 value;
373 rdmsrl(BYT_TURBO_RATIOS, value);
374 return value & 0x3F;
375}
376
007bea09
DB
377static void byt_set_pstate(struct cpudata *cpudata, int pstate)
378{
379 u64 val;
380 int32_t vid_fp;
381 u32 vid;
382
383 val = pstate << 8;
384 if (limits.no_turbo)
385 val |= (u64)1 << 32;
386
387 vid_fp = cpudata->vid.min + mul_fp(
388 int_tofp(pstate - cpudata->pstate.min_pstate),
389 cpudata->vid.ratio);
390
391 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
392 vid = fp_toint(vid_fp);
393
394 val |= vid;
395
396 wrmsrl(MSR_IA32_PERF_CTL, val);
397}
398
399static void byt_get_vid(struct cpudata *cpudata)
400{
401 u64 value;
402
403 rdmsrl(BYT_VIDS, value);
404 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
405 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
406 cpudata->vid.ratio = div_fp(
407 cpudata->vid.max - cpudata->vid.min,
408 int_tofp(cpudata->pstate.max_pstate -
409 cpudata->pstate.min_pstate));
410}
411
412
016c8150 413static int core_get_min_pstate(void)
93f0822d
DB
414{
415 u64 value;
05e99c8c 416 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
417 return (value >> 40) & 0xFF;
418}
419
016c8150 420static int core_get_max_pstate(void)
93f0822d
DB
421{
422 u64 value;
05e99c8c 423 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB
424 return (value >> 8) & 0xFF;
425}
426
016c8150 427static int core_get_turbo_pstate(void)
93f0822d
DB
428{
429 u64 value;
430 int nont, ret;
05e99c8c 431 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
016c8150 432 nont = core_get_max_pstate();
93f0822d
DB
433 ret = ((value) & 255);
434 if (ret <= nont)
435 ret = nont;
436 return ret;
437}
438
007bea09 439static void core_set_pstate(struct cpudata *cpudata, int pstate)
016c8150
DB
440{
441 u64 val;
442
443 val = pstate << 8;
444 if (limits.no_turbo)
445 val |= (u64)1 << 32;
446
bb18008f 447 wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val);
016c8150
DB
448}
449
450static struct cpu_defaults core_params = {
451 .pid_policy = {
452 .sample_rate_ms = 10,
453 .deadband = 0,
454 .setpoint = 97,
455 .p_gain_pct = 20,
456 .d_gain_pct = 0,
457 .i_gain_pct = 0,
458 },
459 .funcs = {
460 .get_max = core_get_max_pstate,
461 .get_min = core_get_min_pstate,
462 .get_turbo = core_get_turbo_pstate,
463 .set = core_set_pstate,
464 },
465};
466
19e77c28
DB
467static struct cpu_defaults byt_params = {
468 .pid_policy = {
469 .sample_rate_ms = 10,
470 .deadband = 0,
471 .setpoint = 97,
472 .p_gain_pct = 14,
473 .d_gain_pct = 0,
474 .i_gain_pct = 4,
475 },
476 .funcs = {
477 .get_max = byt_get_max_pstate,
478 .get_min = byt_get_min_pstate,
61d8d2ab 479 .get_turbo = byt_get_turbo_pstate,
007bea09
DB
480 .set = byt_set_pstate,
481 .get_vid = byt_get_vid,
19e77c28
DB
482 },
483};
484
485
93f0822d
DB
486static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
487{
488 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 489 int max_perf_adj;
93f0822d
DB
490 int min_perf;
491 if (limits.no_turbo)
492 max_perf = cpu->pstate.max_pstate;
493
7244cb62
DB
494 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
495 *max = clamp_t(int, max_perf_adj,
93f0822d
DB
496 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
497
498 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
499 *min = clamp_t(int, min_perf,
500 cpu->pstate.min_pstate, max_perf);
501}
502
503static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
504{
505 int max_perf, min_perf;
506
507 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
508
509 pstate = clamp_t(int, pstate, min_perf, max_perf);
510
511 if (pstate == cpu->pstate.current_pstate)
512 return;
513
93f0822d 514 trace_cpu_frequency(pstate * 100000, cpu->cpu);
35363e94 515
93f0822d 516 cpu->pstate.current_pstate = pstate;
93f0822d 517
007bea09 518 pstate_funcs.set(cpu, pstate);
93f0822d
DB
519}
520
521static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
522{
523 int target;
524 target = cpu->pstate.current_pstate + steps;
525
526 intel_pstate_set_pstate(cpu, target);
527}
528
529static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)
530{
531 int target;
532 target = cpu->pstate.current_pstate - steps;
533 intel_pstate_set_pstate(cpu, target);
534}
535
536static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
537{
538 sprintf(cpu->name, "Intel 2nd generation core");
539
016c8150
DB
540 cpu->pstate.min_pstate = pstate_funcs.get_min();
541 cpu->pstate.max_pstate = pstate_funcs.get_max();
542 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
93f0822d 543
007bea09
DB
544 if (pstate_funcs.get_vid)
545 pstate_funcs.get_vid(cpu);
546
93f0822d
DB
547 /*
548 * goto max pstate so we don't slow up boot if we are built-in if we are
549 * a module we will take care of it during normal operation
550 */
551 intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate);
552}
553
6b17ddb2 554static inline void intel_pstate_calc_busy(struct cpudata *cpu)
93f0822d 555{
6b17ddb2 556 struct sample *sample = &cpu->sample;
e66c1768
DB
557 int32_t core_pct;
558 int32_t c0_pct;
93f0822d 559
6b17ddb2 560 core_pct = div_fp(int_tofp(sample->aperf), int_tofp(sample->mperf));
e66c1768
DB
561 core_pct = mul_fp(core_pct, int_tofp(100));
562 FP_ROUNDUP(core_pct);
563
564 c0_pct = div_fp(int_tofp(sample->mperf), int_tofp(sample->tsc));
fcb6a15c 565
fcb6a15c 566 sample->freq = fp_toint(
e66c1768 567 mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct));
fcb6a15c 568
e66c1768 569 sample->core_pct_busy = mul_fp(core_pct, c0_pct);
93f0822d
DB
570}
571
572static inline void intel_pstate_sample(struct cpudata *cpu)
573{
93f0822d 574 u64 aperf, mperf;
fcb6a15c 575 unsigned long long tsc;
93f0822d 576
93f0822d
DB
577 rdmsrl(MSR_IA32_APERF, aperf);
578 rdmsrl(MSR_IA32_MPERF, mperf);
fcb6a15c 579 tsc = native_read_tsc();
b69880f9 580
e66c1768
DB
581 aperf = aperf >> FRAC_BITS;
582 mperf = mperf >> FRAC_BITS;
583 tsc = tsc >> FRAC_BITS;
584
d37e2b76
DB
585 cpu->sample.aperf = aperf;
586 cpu->sample.mperf = mperf;
587 cpu->sample.tsc = tsc;
588 cpu->sample.aperf -= cpu->prev_aperf;
589 cpu->sample.mperf -= cpu->prev_mperf;
590 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 591
6b17ddb2 592 intel_pstate_calc_busy(cpu);
93f0822d 593
93f0822d
DB
594 cpu->prev_aperf = aperf;
595 cpu->prev_mperf = mperf;
fcb6a15c 596 cpu->prev_tsc = tsc;
93f0822d
DB
597}
598
599static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
600{
601 int sample_time, delay;
602
016c8150 603 sample_time = pid_params.sample_rate_ms;
93f0822d 604 delay = msecs_to_jiffies(sample_time);
93f0822d
DB
605 mod_timer_pinned(&cpu->timer, jiffies + delay);
606}
607
d253d2a5 608static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
93f0822d 609{
2134ed4d 610 int32_t core_busy, max_pstate, current_pstate;
93f0822d 611
d37e2b76 612 core_busy = cpu->sample.core_pct_busy;
2134ed4d 613 max_pstate = int_tofp(cpu->pstate.max_pstate);
93f0822d 614 current_pstate = int_tofp(cpu->pstate.current_pstate);
e66c1768
DB
615 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
616 return FP_ROUNDUP(core_busy);
93f0822d
DB
617}
618
619static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
620{
d253d2a5 621 int32_t busy_scaled;
93f0822d
DB
622 struct _pid *pid;
623 signed int ctl = 0;
624 int steps;
625
626 pid = &cpu->pid;
627 busy_scaled = intel_pstate_get_scaled_busy(cpu);
628
629 ctl = pid_calc(pid, busy_scaled);
630
631 steps = abs(ctl);
b69880f9 632
93f0822d
DB
633 if (ctl < 0)
634 intel_pstate_pstate_increase(cpu, steps);
635 else
636 intel_pstate_pstate_decrease(cpu, steps);
637}
638
93f0822d
DB
639static void intel_pstate_timer_func(unsigned long __data)
640{
641 struct cpudata *cpu = (struct cpudata *) __data;
b69880f9 642 struct sample *sample;
93f0822d
DB
643
644 intel_pstate_sample(cpu);
b69880f9 645
d37e2b76 646 sample = &cpu->sample;
b69880f9 647
ca182aee 648 intel_pstate_adjust_busy_pstate(cpu);
b69880f9
DB
649
650 trace_pstate_sample(fp_toint(sample->core_pct_busy),
651 fp_toint(intel_pstate_get_scaled_busy(cpu)),
652 cpu->pstate.current_pstate,
653 sample->mperf,
654 sample->aperf,
b69880f9
DB
655 sample->freq);
656
93f0822d
DB
657 intel_pstate_set_sample_time(cpu);
658}
659
660#define ICPU(model, policy) \
6cbd7ee1
DB
661 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
662 (unsigned long)&policy }
93f0822d
DB
663
664static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
016c8150
DB
665 ICPU(0x2a, core_params),
666 ICPU(0x2d, core_params),
19e77c28 667 ICPU(0x37, byt_params),
016c8150
DB
668 ICPU(0x3a, core_params),
669 ICPU(0x3c, core_params),
670 ICPU(0x3e, core_params),
671 ICPU(0x3f, core_params),
672 ICPU(0x45, core_params),
673 ICPU(0x46, core_params),
93f0822d
DB
674 {}
675};
676MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
677
678static int intel_pstate_init_cpu(unsigned int cpunum)
679{
680
681 const struct x86_cpu_id *id;
682 struct cpudata *cpu;
683
684 id = x86_match_cpu(intel_pstate_cpu_ids);
685 if (!id)
686 return -ENODEV;
687
688 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
689 if (!all_cpu_data[cpunum])
690 return -ENOMEM;
691
692 cpu = all_cpu_data[cpunum];
693
694 intel_pstate_get_cpu_pstates(cpu);
98a947ab
RW
695 if (!cpu->pstate.current_pstate) {
696 all_cpu_data[cpunum] = NULL;
697 kfree(cpu);
698 return -ENODATA;
699 }
93f0822d
DB
700
701 cpu->cpu = cpunum;
016c8150 702
93f0822d
DB
703 init_timer_deferrable(&cpu->timer);
704 cpu->timer.function = intel_pstate_timer_func;
705 cpu->timer.data =
706 (unsigned long)cpu;
707 cpu->timer.expires = jiffies + HZ/100;
708 intel_pstate_busy_pid_reset(cpu);
93f0822d
DB
709 intel_pstate_sample(cpu);
710 intel_pstate_set_pstate(cpu, cpu->pstate.max_pstate);
711
712 add_timer_on(&cpu->timer, cpunum);
713
714 pr_info("Intel pstate controlling: cpu %d\n", cpunum);
715
716 return 0;
717}
718
719static unsigned int intel_pstate_get(unsigned int cpu_num)
720{
721 struct sample *sample;
722 struct cpudata *cpu;
723
724 cpu = all_cpu_data[cpu_num];
725 if (!cpu)
726 return 0;
d37e2b76 727 sample = &cpu->sample;
93f0822d
DB
728 return sample->freq;
729}
730
731static int intel_pstate_set_policy(struct cpufreq_policy *policy)
732{
733 struct cpudata *cpu;
93f0822d
DB
734
735 cpu = all_cpu_data[policy->cpu];
736
d3929b83
DB
737 if (!policy->cpuinfo.max_freq)
738 return -ENODEV;
739
93f0822d
DB
740 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
741 limits.min_perf_pct = 100;
742 limits.min_perf = int_tofp(1);
743 limits.max_perf_pct = 100;
744 limits.max_perf = int_tofp(1);
745 limits.no_turbo = 0;
d1b68485 746 return 0;
93f0822d 747 }
d1b68485
SP
748 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
749 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
750 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
751
d8f469e9
DB
752 limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;
753 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
754 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
d1b68485 755 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
93f0822d
DB
756
757 return 0;
758}
759
760static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
761{
be49e346 762 cpufreq_verify_within_cpu_limits(policy);
93f0822d
DB
763
764 if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
765 (policy->policy != CPUFREQ_POLICY_PERFORMANCE))
766 return -EINVAL;
767
768 return 0;
769}
770
bb18008f 771static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 772{
bb18008f
DB
773 int cpu_num = policy->cpu;
774 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 775
bb18008f
DB
776 pr_info("intel_pstate CPU %d exiting\n", cpu_num);
777
c2294a2f 778 del_timer_sync(&all_cpu_data[cpu_num]->timer);
bb18008f
DB
779 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
780 kfree(all_cpu_data[cpu_num]);
781 all_cpu_data[cpu_num] = NULL;
93f0822d
DB
782}
783
2760984f 784static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 785{
93f0822d 786 struct cpudata *cpu;
52e0a509 787 int rc;
93f0822d
DB
788
789 rc = intel_pstate_init_cpu(policy->cpu);
790 if (rc)
791 return rc;
792
793 cpu = all_cpu_data[policy->cpu];
794
795 if (!limits.no_turbo &&
796 limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
797 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
798 else
799 policy->policy = CPUFREQ_POLICY_POWERSAVE;
800
52e0a509
DB
801 policy->min = cpu->pstate.min_pstate * 100000;
802 policy->max = cpu->pstate.turbo_pstate * 100000;
93f0822d
DB
803
804 /* cpuinfo and default policy values */
805 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000;
806 policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000;
807 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
808 cpumask_set_cpu(policy->cpu, policy->cpus);
809
810 return 0;
811}
812
813static struct cpufreq_driver intel_pstate_driver = {
814 .flags = CPUFREQ_CONST_LOOPS,
815 .verify = intel_pstate_verify_policy,
816 .setpolicy = intel_pstate_set_policy,
817 .get = intel_pstate_get,
818 .init = intel_pstate_cpu_init,
bb18008f 819 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 820 .name = "intel_pstate",
93f0822d
DB
821};
822
6be26498
DB
823static int __initdata no_load;
824
b563b4e3
DB
825static int intel_pstate_msrs_not_valid(void)
826{
827 /* Check that all the msr's we are using are valid. */
828 u64 aperf, mperf, tmp;
829
830 rdmsrl(MSR_IA32_APERF, aperf);
831 rdmsrl(MSR_IA32_MPERF, mperf);
832
016c8150
DB
833 if (!pstate_funcs.get_max() ||
834 !pstate_funcs.get_min() ||
835 !pstate_funcs.get_turbo())
b563b4e3
DB
836 return -ENODEV;
837
838 rdmsrl(MSR_IA32_APERF, tmp);
839 if (!(tmp - aperf))
840 return -ENODEV;
841
842 rdmsrl(MSR_IA32_MPERF, tmp);
843 if (!(tmp - mperf))
844 return -ENODEV;
845
846 return 0;
847}
016c8150 848
e0a261a2 849static void copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB
850{
851 pid_params.sample_rate_ms = policy->sample_rate_ms;
852 pid_params.p_gain_pct = policy->p_gain_pct;
853 pid_params.i_gain_pct = policy->i_gain_pct;
854 pid_params.d_gain_pct = policy->d_gain_pct;
855 pid_params.deadband = policy->deadband;
856 pid_params.setpoint = policy->setpoint;
857}
858
e0a261a2 859static void copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB
860{
861 pstate_funcs.get_max = funcs->get_max;
862 pstate_funcs.get_min = funcs->get_min;
863 pstate_funcs.get_turbo = funcs->get_turbo;
864 pstate_funcs.set = funcs->set;
007bea09 865 pstate_funcs.get_vid = funcs->get_vid;
016c8150
DB
866}
867
fbbcdc07
AH
868#if IS_ENABLED(CONFIG_ACPI)
869#include <acpi/processor.h>
870
871static bool intel_pstate_no_acpi_pss(void)
872{
873 int i;
874
875 for_each_possible_cpu(i) {
876 acpi_status status;
877 union acpi_object *pss;
878 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
879 struct acpi_processor *pr = per_cpu(processors, i);
880
881 if (!pr)
882 continue;
883
884 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
885 if (ACPI_FAILURE(status))
886 continue;
887
888 pss = buffer.pointer;
889 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
890 kfree(pss);
891 return false;
892 }
893
894 kfree(pss);
895 }
896
897 return true;
898}
899
900struct hw_vendor_info {
901 u16 valid;
902 char oem_id[ACPI_OEM_ID_SIZE];
903 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
904};
905
906/* Hardware vendor-specific info that has its own power management modes */
907static struct hw_vendor_info vendor_info[] = {
908 {1, "HP ", "ProLiant"},
909 {0, "", ""},
910};
911
912static bool intel_pstate_platform_pwr_mgmt_exists(void)
913{
914 struct acpi_table_header hdr;
915 struct hw_vendor_info *v_info;
916
917 if (acpi_disabled
918 || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
919 return false;
920
921 for (v_info = vendor_info; v_info->valid; v_info++) {
922 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)
923 && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)
924 && intel_pstate_no_acpi_pss())
925 return true;
926 }
927
928 return false;
929}
930#else /* CONFIG_ACPI not enabled */
931static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
932#endif /* CONFIG_ACPI */
933
93f0822d
DB
934static int __init intel_pstate_init(void)
935{
907cc908 936 int cpu, rc = 0;
93f0822d 937 const struct x86_cpu_id *id;
016c8150 938 struct cpu_defaults *cpu_info;
93f0822d 939
6be26498
DB
940 if (no_load)
941 return -ENODEV;
942
93f0822d
DB
943 id = x86_match_cpu(intel_pstate_cpu_ids);
944 if (!id)
945 return -ENODEV;
946
fbbcdc07
AH
947 /*
948 * The Intel pstate driver will be ignored if the platform
949 * firmware has its own power management modes.
950 */
951 if (intel_pstate_platform_pwr_mgmt_exists())
952 return -ENODEV;
953
016c8150
DB
954 cpu_info = (struct cpu_defaults *)id->driver_data;
955
956 copy_pid_params(&cpu_info->pid_policy);
957 copy_cpu_funcs(&cpu_info->funcs);
958
b563b4e3
DB
959 if (intel_pstate_msrs_not_valid())
960 return -ENODEV;
961
93f0822d
DB
962 pr_info("Intel P-state driver initializing.\n");
963
b57ffac5 964 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB
965 if (!all_cpu_data)
966 return -ENOMEM;
93f0822d
DB
967
968 rc = cpufreq_register_driver(&intel_pstate_driver);
969 if (rc)
970 goto out;
971
972 intel_pstate_debug_expose_params();
973 intel_pstate_sysfs_expose_params();
b69880f9 974
93f0822d
DB
975 return rc;
976out:
907cc908
DB
977 get_online_cpus();
978 for_each_online_cpu(cpu) {
979 if (all_cpu_data[cpu]) {
980 del_timer_sync(&all_cpu_data[cpu]->timer);
981 kfree(all_cpu_data[cpu]);
982 }
983 }
984
985 put_online_cpus();
986 vfree(all_cpu_data);
93f0822d
DB
987 return -ENODEV;
988}
989device_initcall(intel_pstate_init);
990
6be26498
DB
991static int __init intel_pstate_setup(char *str)
992{
993 if (!str)
994 return -EINVAL;
995
996 if (!strcmp(str, "disable"))
997 no_load = 1;
998 return 0;
999}
1000early_param("intel_pstate", intel_pstate_setup);
1001
93f0822d
DB
1002MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1003MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1004MODULE_LICENSE("GPL");