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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
55687da1 | 22 | #include <linux/sched/cpufreq.h> |
93f0822d DB |
23 | #include <linux/list.h> |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
eabd22c6 RW |
40 | #define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC) |
41 | #define INTEL_PSTATE_HWP_SAMPLING_INTERVAL (50 * NSEC_PER_MSEC) | |
42 | ||
001c76f0 RW |
43 | #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000 |
44 | ||
9522a2ff SP |
45 | #ifdef CONFIG_ACPI |
46 | #include <acpi/processor.h> | |
17669006 | 47 | #include <acpi/cppc_acpi.h> |
9522a2ff SP |
48 | #endif |
49 | ||
f0fe3cd7 | 50 | #define FRAC_BITS 8 |
93f0822d DB |
51 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
52 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 53 | |
a1c9787d RW |
54 | #define EXT_BITS 6 |
55 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
d5dd33d9 SP |
56 | #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS) |
57 | #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS) | |
a1c9787d | 58 | |
93f0822d DB |
59 | static inline int32_t mul_fp(int32_t x, int32_t y) |
60 | { | |
61 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
62 | } | |
63 | ||
7180dddf | 64 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 65 | { |
7180dddf | 66 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
67 | } |
68 | ||
d022a65e DB |
69 | static inline int ceiling_fp(int32_t x) |
70 | { | |
71 | int mask, ret; | |
72 | ||
73 | ret = fp_toint(x); | |
74 | mask = (1 << FRAC_BITS) - 1; | |
75 | if (x & mask) | |
76 | ret += 1; | |
77 | return ret; | |
78 | } | |
79 | ||
ff35f02e RW |
80 | static inline int32_t percent_fp(int percent) |
81 | { | |
82 | return div_fp(percent, 100); | |
83 | } | |
84 | ||
a1c9787d RW |
85 | static inline u64 mul_ext_fp(u64 x, u64 y) |
86 | { | |
87 | return (x * y) >> EXT_FRAC_BITS; | |
88 | } | |
89 | ||
90 | static inline u64 div_ext_fp(u64 x, u64 y) | |
91 | { | |
92 | return div64_u64(x << EXT_FRAC_BITS, y); | |
93 | } | |
94 | ||
e4c204ce RW |
95 | static inline int32_t percent_ext_fp(int percent) |
96 | { | |
97 | return div_ext_fp(percent, 100); | |
98 | } | |
99 | ||
13ad7701 SP |
100 | /** |
101 | * struct sample - Store performance sample | |
a1c9787d | 102 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
103 | * performance during last sample period |
104 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 105 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
106 | * to account for cpu idle period |
107 | * @aperf: Difference of actual performance frequency clock count | |
108 | * read from APERF MSR between last and current sample | |
109 | * @mperf: Difference of maximum performance frequency clock count | |
110 | * read from MPERF MSR between last and current sample | |
111 | * @tsc: Difference of time stamp counter between last and | |
112 | * current sample | |
13ad7701 SP |
113 | * @time: Current time from scheduler |
114 | * | |
115 | * This structure is used in the cpudata structure to store performance sample | |
116 | * data for choosing next P State. | |
117 | */ | |
93f0822d | 118 | struct sample { |
a1c9787d | 119 | int32_t core_avg_perf; |
157386b6 | 120 | int32_t busy_scaled; |
93f0822d DB |
121 | u64 aperf; |
122 | u64 mperf; | |
4055fad3 | 123 | u64 tsc; |
a4675fbc | 124 | u64 time; |
93f0822d DB |
125 | }; |
126 | ||
13ad7701 SP |
127 | /** |
128 | * struct pstate_data - Store P state data | |
129 | * @current_pstate: Current requested P state | |
130 | * @min_pstate: Min P state possible for this platform | |
131 | * @max_pstate: Max P state possible for this platform | |
132 | * @max_pstate_physical:This is physical Max P state for a processor | |
133 | * This can be higher than the max_pstate which can | |
134 | * be limited by platform thermal design power limits | |
135 | * @scaling: Scaling factor to convert frequency to cpufreq | |
136 | * frequency units | |
137 | * @turbo_pstate: Max Turbo P state possible for this platform | |
001c76f0 RW |
138 | * @max_freq: @max_pstate frequency in cpufreq units |
139 | * @turbo_freq: @turbo_pstate frequency in cpufreq units | |
13ad7701 SP |
140 | * |
141 | * Stores the per cpu model P state limits and current P state. | |
142 | */ | |
93f0822d DB |
143 | struct pstate_data { |
144 | int current_pstate; | |
145 | int min_pstate; | |
146 | int max_pstate; | |
3bcc6fa9 | 147 | int max_pstate_physical; |
b27580b0 | 148 | int scaling; |
93f0822d | 149 | int turbo_pstate; |
001c76f0 RW |
150 | unsigned int max_freq; |
151 | unsigned int turbo_freq; | |
93f0822d DB |
152 | }; |
153 | ||
13ad7701 SP |
154 | /** |
155 | * struct vid_data - Stores voltage information data | |
156 | * @min: VID data for this platform corresponding to | |
157 | * the lowest P state | |
158 | * @max: VID data corresponding to the highest P State. | |
159 | * @turbo: VID data for turbo P state | |
160 | * @ratio: Ratio of (vid max - vid min) / | |
161 | * (max P state - Min P State) | |
162 | * | |
163 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
164 | * This data is used in Atom platforms, where in addition to target P state, | |
165 | * the voltage data needs to be specified to select next P State. | |
166 | */ | |
007bea09 | 167 | struct vid_data { |
21855ff5 DB |
168 | int min; |
169 | int max; | |
170 | int turbo; | |
007bea09 DB |
171 | int32_t ratio; |
172 | }; | |
173 | ||
13ad7701 SP |
174 | /** |
175 | * struct _pid - Stores PID data | |
176 | * @setpoint: Target set point for busyness or performance | |
177 | * @integral: Storage for accumulated error values | |
178 | * @p_gain: PID proportional gain | |
179 | * @i_gain: PID integral gain | |
180 | * @d_gain: PID derivative gain | |
181 | * @deadband: PID deadband | |
182 | * @last_err: Last error storage for integral part of PID calculation | |
183 | * | |
184 | * Stores PID coefficients and last error for PID controller. | |
185 | */ | |
93f0822d DB |
186 | struct _pid { |
187 | int setpoint; | |
188 | int32_t integral; | |
189 | int32_t p_gain; | |
190 | int32_t i_gain; | |
191 | int32_t d_gain; | |
192 | int deadband; | |
d253d2a5 | 193 | int32_t last_err; |
93f0822d DB |
194 | }; |
195 | ||
c5a2ee7d RW |
196 | /** |
197 | * struct global_params - Global parameters, mostly tunable via sysfs. | |
198 | * @no_turbo: Whether or not to use turbo P-states. | |
199 | * @turbo_disabled: Whethet or not turbo P-states are available at all, | |
200 | * based on the MSR_IA32_MISC_ENABLE value and whether or | |
201 | * not the maximum reported turbo P-state is different from | |
202 | * the maximum reported non-turbo one. | |
203 | * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo | |
204 | * P-state capacity. | |
205 | * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo | |
206 | * P-state capacity. | |
207 | */ | |
208 | struct global_params { | |
209 | bool no_turbo; | |
210 | bool turbo_disabled; | |
211 | int max_perf_pct; | |
212 | int min_perf_pct; | |
eae48f04 SP |
213 | }; |
214 | ||
13ad7701 SP |
215 | /** |
216 | * struct cpudata - Per CPU instance data storage | |
217 | * @cpu: CPU number for this instance data | |
2f1d407a | 218 | * @policy: CPUFreq policy value |
13ad7701 | 219 | * @update_util: CPUFreq utility callback information |
4578ee7e | 220 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
221 | * @iowait_boost: iowait-related boost fraction |
222 | * @last_update: Time of the last update. | |
13ad7701 SP |
223 | * @pstate: Stores P state limits for this CPU |
224 | * @vid: Stores VID limits for this CPU | |
225 | * @pid: Stores PID parameters for this CPU | |
226 | * @last_sample_time: Last Sample time | |
227 | * @prev_aperf: Last APERF value read from APERF MSR | |
228 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
229 | * @prev_tsc: Last timestamp counter (TSC) value | |
230 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
231 | * current sample | |
232 | * @sample: Storage for storing last Sample data | |
e14cf885 RW |
233 | * @min_perf: Minimum capacity limit as a fraction of the maximum |
234 | * turbo P-state capacity. | |
235 | * @max_perf: Maximum capacity limit as a fraction of the maximum | |
236 | * turbo P-state capacity. | |
9522a2ff SP |
237 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
238 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
984edbdc SP |
239 | * @epp_powersave: Last saved HWP energy performance preference |
240 | * (EPP) or energy performance bias (EPB), | |
241 | * when policy switched to performance | |
8442885f | 242 | * @epp_policy: Last saved policy used to set EPP/EPB |
984edbdc SP |
243 | * @epp_default: Power on default HWP energy performance |
244 | * preference/bias | |
245 | * @epp_saved: Saved EPP/EPB during system suspend or CPU offline | |
246 | * operation | |
13ad7701 SP |
247 | * |
248 | * This structure stores per CPU instance data for all CPUs. | |
249 | */ | |
93f0822d DB |
250 | struct cpudata { |
251 | int cpu; | |
252 | ||
2f1d407a | 253 | unsigned int policy; |
a4675fbc | 254 | struct update_util_data update_util; |
4578ee7e | 255 | bool update_util_set; |
93f0822d | 256 | |
93f0822d | 257 | struct pstate_data pstate; |
007bea09 | 258 | struct vid_data vid; |
93f0822d | 259 | struct _pid pid; |
93f0822d | 260 | |
09c448d3 | 261 | u64 last_update; |
a4675fbc | 262 | u64 last_sample_time; |
93f0822d DB |
263 | u64 prev_aperf; |
264 | u64 prev_mperf; | |
4055fad3 | 265 | u64 prev_tsc; |
63d1d656 | 266 | u64 prev_cummulative_iowait; |
d37e2b76 | 267 | struct sample sample; |
e14cf885 RW |
268 | int32_t min_perf; |
269 | int32_t max_perf; | |
9522a2ff SP |
270 | #ifdef CONFIG_ACPI |
271 | struct acpi_processor_performance acpi_perf_data; | |
272 | bool valid_pss_table; | |
273 | #endif | |
09c448d3 | 274 | unsigned int iowait_boost; |
984edbdc | 275 | s16 epp_powersave; |
8442885f | 276 | s16 epp_policy; |
984edbdc SP |
277 | s16 epp_default; |
278 | s16 epp_saved; | |
93f0822d DB |
279 | }; |
280 | ||
281 | static struct cpudata **all_cpu_data; | |
13ad7701 SP |
282 | |
283 | /** | |
3954517e | 284 | * struct pstate_adjust_policy - Stores static PID configuration data |
13ad7701 SP |
285 | * @sample_rate_ms: PID calculation sample rate in ms |
286 | * @sample_rate_ns: Sample rate calculation in ns | |
287 | * @deadband: PID deadband | |
288 | * @setpoint: PID Setpoint | |
289 | * @p_gain_pct: PID proportional gain | |
290 | * @i_gain_pct: PID integral gain | |
291 | * @d_gain_pct: PID derivative gain | |
292 | * | |
293 | * Stores per CPU model static PID configuration data. | |
294 | */ | |
93f0822d DB |
295 | struct pstate_adjust_policy { |
296 | int sample_rate_ms; | |
a4675fbc | 297 | s64 sample_rate_ns; |
93f0822d DB |
298 | int deadband; |
299 | int setpoint; | |
300 | int p_gain_pct; | |
301 | int d_gain_pct; | |
302 | int i_gain_pct; | |
303 | }; | |
304 | ||
13ad7701 SP |
305 | /** |
306 | * struct pstate_funcs - Per CPU model specific callbacks | |
307 | * @get_max: Callback to get maximum non turbo effective P state | |
308 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
309 | * @get_min: Callback to get minimum P state | |
310 | * @get_turbo: Callback to get turbo P state | |
311 | * @get_scaling: Callback to get frequency scaling factor | |
312 | * @get_val: Callback to convert P state to actual MSR write value | |
313 | * @get_vid: Callback to get VID data for Atom platforms | |
67dd9bf4 | 314 | * @update_util: Active mode utilization update callback. |
13ad7701 SP |
315 | * |
316 | * Core and Atom CPU models have different way to get P State limits. This | |
317 | * structure is used to store those callbacks. | |
318 | */ | |
016c8150 DB |
319 | struct pstate_funcs { |
320 | int (*get_max)(void); | |
3bcc6fa9 | 321 | int (*get_max_physical)(void); |
016c8150 DB |
322 | int (*get_min)(void); |
323 | int (*get_turbo)(void); | |
b27580b0 | 324 | int (*get_scaling)(void); |
fdfdb2b1 | 325 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 326 | void (*get_vid)(struct cpudata *); |
67dd9bf4 RW |
327 | void (*update_util)(struct update_util_data *data, u64 time, |
328 | unsigned int flags); | |
93f0822d DB |
329 | }; |
330 | ||
13ad7701 SP |
331 | /** |
332 | * struct cpu_defaults- Per CPU model default config data | |
13ad7701 SP |
333 | * @funcs: Callback function data |
334 | */ | |
016c8150 | 335 | struct cpu_defaults { |
016c8150 | 336 | struct pstate_funcs funcs; |
93f0822d DB |
337 | }; |
338 | ||
4a7cb7a9 | 339 | static struct pstate_funcs pstate_funcs __read_mostly; |
5c439053 RW |
340 | static struct pstate_adjust_policy pid_params __read_mostly = { |
341 | .sample_rate_ms = 10, | |
342 | .sample_rate_ns = 10 * NSEC_PER_MSEC, | |
343 | .deadband = 0, | |
344 | .setpoint = 97, | |
345 | .p_gain_pct = 20, | |
346 | .d_gain_pct = 0, | |
347 | .i_gain_pct = 0, | |
348 | }; | |
349 | ||
4a7cb7a9 | 350 | static int hwp_active __read_mostly; |
eae48f04 | 351 | static bool per_cpu_limits __read_mostly; |
016c8150 | 352 | |
ee8df89a | 353 | static struct cpufreq_driver *intel_pstate_driver __read_mostly; |
0c30b65b | 354 | |
9522a2ff SP |
355 | #ifdef CONFIG_ACPI |
356 | static bool acpi_ppc; | |
357 | #endif | |
13ad7701 | 358 | |
c5a2ee7d | 359 | static struct global_params global; |
93f0822d | 360 | |
0c30b65b | 361 | static DEFINE_MUTEX(intel_pstate_driver_lock); |
a410c03d SP |
362 | static DEFINE_MUTEX(intel_pstate_limits_lock); |
363 | ||
9522a2ff | 364 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
365 | |
366 | static bool intel_pstate_get_ppc_enable_status(void) | |
367 | { | |
368 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
369 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
370 | return true; | |
371 | ||
372 | return acpi_ppc; | |
373 | } | |
374 | ||
17669006 RW |
375 | #ifdef CONFIG_ACPI_CPPC_LIB |
376 | ||
377 | /* The work item is needed to avoid CPU hotplug locking issues */ | |
378 | static void intel_pstste_sched_itmt_work_fn(struct work_struct *work) | |
379 | { | |
380 | sched_set_itmt_support(); | |
381 | } | |
382 | ||
383 | static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn); | |
384 | ||
385 | static void intel_pstate_set_itmt_prio(int cpu) | |
386 | { | |
387 | struct cppc_perf_caps cppc_perf; | |
388 | static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; | |
389 | int ret; | |
390 | ||
391 | ret = cppc_get_perf_caps(cpu, &cppc_perf); | |
392 | if (ret) | |
393 | return; | |
394 | ||
395 | /* | |
396 | * The priorities can be set regardless of whether or not | |
397 | * sched_set_itmt_support(true) has been called and it is valid to | |
398 | * update them at any time after it has been called. | |
399 | */ | |
400 | sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu); | |
401 | ||
402 | if (max_highest_perf <= min_highest_perf) { | |
403 | if (cppc_perf.highest_perf > max_highest_perf) | |
404 | max_highest_perf = cppc_perf.highest_perf; | |
405 | ||
406 | if (cppc_perf.highest_perf < min_highest_perf) | |
407 | min_highest_perf = cppc_perf.highest_perf; | |
408 | ||
409 | if (max_highest_perf > min_highest_perf) { | |
410 | /* | |
411 | * This code can be run during CPU online under the | |
412 | * CPU hotplug locks, so sched_set_itmt_support() | |
413 | * cannot be called from here. Queue up a work item | |
414 | * to invoke it. | |
415 | */ | |
416 | schedule_work(&sched_itmt_work); | |
417 | } | |
418 | } | |
419 | } | |
420 | #else | |
421 | static void intel_pstate_set_itmt_prio(int cpu) | |
422 | { | |
423 | } | |
424 | #endif | |
425 | ||
9522a2ff SP |
426 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
427 | { | |
428 | struct cpudata *cpu; | |
9522a2ff SP |
429 | int ret; |
430 | int i; | |
431 | ||
17669006 RW |
432 | if (hwp_active) { |
433 | intel_pstate_set_itmt_prio(policy->cpu); | |
e59a8f7f | 434 | return; |
17669006 | 435 | } |
e59a8f7f | 436 | |
2b3ec765 | 437 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
438 | return; |
439 | ||
440 | cpu = all_cpu_data[policy->cpu]; | |
441 | ||
442 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
443 | policy->cpu); | |
444 | if (ret) | |
445 | return; | |
446 | ||
447 | /* | |
448 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
449 | * guarantee that the states returned by it map to the states in our | |
450 | * list directly. | |
451 | */ | |
452 | if (cpu->acpi_perf_data.control_register.space_id != | |
453 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
454 | goto err; | |
455 | ||
456 | /* | |
457 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
458 | * usual without taking _PSS into account | |
459 | */ | |
460 | if (cpu->acpi_perf_data.state_count < 2) | |
461 | goto err; | |
462 | ||
463 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
464 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
465 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
466 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
467 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
468 | (u32) cpu->acpi_perf_data.states[i].power, | |
469 | (u32) cpu->acpi_perf_data.states[i].control); | |
470 | } | |
471 | ||
472 | /* | |
473 | * The _PSS table doesn't contain whole turbo frequency range. | |
474 | * This just contains +1 MHZ above the max non turbo frequency, | |
475 | * with control value corresponding to max turbo ratio. But | |
476 | * when cpufreq set policy is called, it will call with this | |
477 | * max frequency, which will cause a reduced performance as | |
478 | * this driver uses real max turbo frequency as the max | |
479 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 480 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
481 | * Also need to convert to MHz as _PSS freq is in MHz. |
482 | */ | |
7de32556 | 483 | if (!global.turbo_disabled) |
9522a2ff SP |
484 | cpu->acpi_perf_data.states[0].core_frequency = |
485 | policy->cpuinfo.max_freq / 1000; | |
486 | cpu->valid_pss_table = true; | |
6cacd115 | 487 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
488 | |
489 | return; | |
490 | ||
491 | err: | |
492 | cpu->valid_pss_table = false; | |
493 | acpi_processor_unregister_performance(policy->cpu); | |
494 | } | |
495 | ||
496 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
497 | { | |
498 | struct cpudata *cpu; | |
499 | ||
500 | cpu = all_cpu_data[policy->cpu]; | |
501 | if (!cpu->valid_pss_table) | |
502 | return; | |
503 | ||
504 | acpi_processor_unregister_performance(policy->cpu); | |
505 | } | |
9522a2ff | 506 | #else |
7a3ba767 | 507 | static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
508 | { |
509 | } | |
510 | ||
7a3ba767 | 511 | static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) |
9522a2ff SP |
512 | { |
513 | } | |
514 | #endif | |
515 | ||
d253d2a5 | 516 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 517 | { |
d253d2a5 | 518 | signed int result; |
93f0822d DB |
519 | int32_t pterm, dterm, fp_error; |
520 | int32_t integral_limit; | |
521 | ||
b54a0dfd | 522 | fp_error = pid->setpoint - busy; |
93f0822d | 523 | |
b54a0dfd | 524 | if (abs(fp_error) <= pid->deadband) |
93f0822d DB |
525 | return 0; |
526 | ||
527 | pterm = mul_fp(pid->p_gain, fp_error); | |
528 | ||
529 | pid->integral += fp_error; | |
530 | ||
e0d4c8f8 KCA |
531 | /* |
532 | * We limit the integral here so that it will never | |
533 | * get higher than 30. This prevents it from becoming | |
534 | * too large an input over long periods of time and allows | |
535 | * it to get factored out sooner. | |
536 | * | |
537 | * The value of 30 was chosen through experimentation. | |
538 | */ | |
93f0822d DB |
539 | integral_limit = int_tofp(30); |
540 | if (pid->integral > integral_limit) | |
541 | pid->integral = integral_limit; | |
542 | if (pid->integral < -integral_limit) | |
543 | pid->integral = -integral_limit; | |
544 | ||
d253d2a5 BS |
545 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
546 | pid->last_err = fp_error; | |
93f0822d DB |
547 | |
548 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 549 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
550 | return (signed int)fp_toint(result); |
551 | } | |
552 | ||
ff35f02e | 553 | static inline void intel_pstate_pid_reset(struct cpudata *cpu) |
93f0822d | 554 | { |
ff35f02e | 555 | struct _pid *pid = &cpu->pid; |
93f0822d | 556 | |
ff35f02e RW |
557 | pid->p_gain = percent_fp(pid_params.p_gain_pct); |
558 | pid->d_gain = percent_fp(pid_params.d_gain_pct); | |
559 | pid->i_gain = percent_fp(pid_params.i_gain_pct); | |
560 | pid->setpoint = int_tofp(pid_params.setpoint); | |
561 | pid->last_err = pid->setpoint - int_tofp(100); | |
562 | pid->deadband = int_tofp(pid_params.deadband); | |
563 | pid->integral = 0; | |
93f0822d DB |
564 | } |
565 | ||
4521e1a0 GM |
566 | static inline void update_turbo_state(void) |
567 | { | |
568 | u64 misc_en; | |
569 | struct cpudata *cpu; | |
570 | ||
571 | cpu = all_cpu_data[0]; | |
572 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
7de32556 | 573 | global.turbo_disabled = |
4521e1a0 GM |
574 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
575 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
576 | } | |
577 | ||
c5a2ee7d RW |
578 | static int min_perf_pct_min(void) |
579 | { | |
580 | struct cpudata *cpu = all_cpu_data[0]; | |
581 | ||
582 | return DIV_ROUND_UP(cpu->pstate.min_pstate * 100, | |
583 | cpu->pstate.turbo_pstate); | |
584 | } | |
585 | ||
8442885f SP |
586 | static s16 intel_pstate_get_epb(struct cpudata *cpu_data) |
587 | { | |
588 | u64 epb; | |
589 | int ret; | |
590 | ||
591 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
592 | return -ENXIO; | |
593 | ||
594 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); | |
595 | if (ret) | |
596 | return (s16)ret; | |
597 | ||
598 | return (s16)(epb & 0x0f); | |
599 | } | |
600 | ||
601 | static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data) | |
602 | { | |
603 | s16 epp; | |
604 | ||
984edbdc SP |
605 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
606 | /* | |
607 | * When hwp_req_data is 0, means that caller didn't read | |
608 | * MSR_HWP_REQUEST, so need to read and get EPP. | |
609 | */ | |
610 | if (!hwp_req_data) { | |
611 | epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, | |
612 | &hwp_req_data); | |
613 | if (epp) | |
614 | return epp; | |
615 | } | |
8442885f | 616 | epp = (hwp_req_data >> 24) & 0xff; |
984edbdc | 617 | } else { |
8442885f SP |
618 | /* When there is no EPP present, HWP uses EPB settings */ |
619 | epp = intel_pstate_get_epb(cpu_data); | |
984edbdc | 620 | } |
8442885f SP |
621 | |
622 | return epp; | |
623 | } | |
624 | ||
984edbdc | 625 | static int intel_pstate_set_epb(int cpu, s16 pref) |
8442885f SP |
626 | { |
627 | u64 epb; | |
984edbdc | 628 | int ret; |
8442885f SP |
629 | |
630 | if (!static_cpu_has(X86_FEATURE_EPB)) | |
984edbdc | 631 | return -ENXIO; |
8442885f | 632 | |
984edbdc SP |
633 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb); |
634 | if (ret) | |
635 | return ret; | |
8442885f SP |
636 | |
637 | epb = (epb & ~0x0f) | pref; | |
638 | wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb); | |
984edbdc SP |
639 | |
640 | return 0; | |
8442885f SP |
641 | } |
642 | ||
984edbdc SP |
643 | /* |
644 | * EPP/EPB display strings corresponding to EPP index in the | |
645 | * energy_perf_strings[] | |
646 | * index String | |
647 | *------------------------------------- | |
648 | * 0 default | |
649 | * 1 performance | |
650 | * 2 balance_performance | |
651 | * 3 balance_power | |
652 | * 4 power | |
653 | */ | |
654 | static const char * const energy_perf_strings[] = { | |
655 | "default", | |
656 | "performance", | |
657 | "balance_performance", | |
658 | "balance_power", | |
659 | "power", | |
660 | NULL | |
661 | }; | |
662 | ||
663 | static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data) | |
664 | { | |
665 | s16 epp; | |
666 | int index = -EINVAL; | |
667 | ||
668 | epp = intel_pstate_get_epp(cpu_data, 0); | |
669 | if (epp < 0) | |
670 | return epp; | |
671 | ||
672 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
673 | /* | |
674 | * Range: | |
675 | * 0x00-0x3F : Performance | |
676 | * 0x40-0x7F : Balance performance | |
677 | * 0x80-0xBF : Balance power | |
678 | * 0xC0-0xFF : Power | |
679 | * The EPP is a 8 bit value, but our ranges restrict the | |
680 | * value which can be set. Here only using top two bits | |
681 | * effectively. | |
682 | */ | |
683 | index = (epp >> 6) + 1; | |
684 | } else if (static_cpu_has(X86_FEATURE_EPB)) { | |
685 | /* | |
686 | * Range: | |
687 | * 0x00-0x03 : Performance | |
688 | * 0x04-0x07 : Balance performance | |
689 | * 0x08-0x0B : Balance power | |
690 | * 0x0C-0x0F : Power | |
691 | * The EPB is a 4 bit value, but our ranges restrict the | |
692 | * value which can be set. Here only using top two bits | |
693 | * effectively. | |
694 | */ | |
695 | index = (epp >> 2) + 1; | |
696 | } | |
697 | ||
698 | return index; | |
699 | } | |
700 | ||
701 | static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data, | |
702 | int pref_index) | |
703 | { | |
704 | int epp = -EINVAL; | |
705 | int ret; | |
706 | ||
707 | if (!pref_index) | |
708 | epp = cpu_data->epp_default; | |
709 | ||
710 | mutex_lock(&intel_pstate_limits_lock); | |
711 | ||
712 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { | |
713 | u64 value; | |
714 | ||
715 | ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value); | |
716 | if (ret) | |
717 | goto return_pref; | |
718 | ||
719 | value &= ~GENMASK_ULL(31, 24); | |
720 | ||
721 | /* | |
722 | * If epp is not default, convert from index into | |
723 | * energy_perf_strings to epp value, by shifting 6 | |
724 | * bits left to use only top two bits in epp. | |
725 | * The resultant epp need to shifted by 24 bits to | |
726 | * epp position in MSR_HWP_REQUEST. | |
727 | */ | |
728 | if (epp == -EINVAL) | |
729 | epp = (pref_index - 1) << 6; | |
730 | ||
731 | value |= (u64)epp << 24; | |
732 | ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value); | |
733 | } else { | |
734 | if (epp == -EINVAL) | |
735 | epp = (pref_index - 1) << 2; | |
736 | ret = intel_pstate_set_epb(cpu_data->cpu, epp); | |
737 | } | |
738 | return_pref: | |
739 | mutex_unlock(&intel_pstate_limits_lock); | |
740 | ||
741 | return ret; | |
742 | } | |
743 | ||
744 | static ssize_t show_energy_performance_available_preferences( | |
745 | struct cpufreq_policy *policy, char *buf) | |
746 | { | |
747 | int i = 0; | |
748 | int ret = 0; | |
749 | ||
750 | while (energy_perf_strings[i] != NULL) | |
751 | ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); | |
752 | ||
753 | ret += sprintf(&buf[ret], "\n"); | |
754 | ||
755 | return ret; | |
756 | } | |
757 | ||
758 | cpufreq_freq_attr_ro(energy_performance_available_preferences); | |
759 | ||
760 | static ssize_t store_energy_performance_preference( | |
761 | struct cpufreq_policy *policy, const char *buf, size_t count) | |
762 | { | |
763 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
764 | char str_preference[21]; | |
765 | int ret, i = 0; | |
766 | ||
767 | ret = sscanf(buf, "%20s", str_preference); | |
768 | if (ret != 1) | |
769 | return -EINVAL; | |
770 | ||
771 | while (energy_perf_strings[i] != NULL) { | |
772 | if (!strcmp(str_preference, energy_perf_strings[i])) { | |
773 | intel_pstate_set_energy_pref_index(cpu_data, i); | |
774 | return count; | |
775 | } | |
776 | ++i; | |
777 | } | |
778 | ||
779 | return -EINVAL; | |
780 | } | |
781 | ||
782 | static ssize_t show_energy_performance_preference( | |
783 | struct cpufreq_policy *policy, char *buf) | |
784 | { | |
785 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
786 | int preference; | |
787 | ||
788 | preference = intel_pstate_get_energy_pref_index(cpu_data); | |
789 | if (preference < 0) | |
790 | return preference; | |
791 | ||
792 | return sprintf(buf, "%s\n", energy_perf_strings[preference]); | |
793 | } | |
794 | ||
795 | cpufreq_freq_attr_rw(energy_performance_preference); | |
796 | ||
797 | static struct freq_attr *hwp_cpufreq_attrs[] = { | |
798 | &energy_performance_preference, | |
799 | &energy_performance_available_preferences, | |
800 | NULL, | |
801 | }; | |
802 | ||
111b8b3f | 803 | static void intel_pstate_hwp_set(struct cpufreq_policy *policy) |
2f86dc4c | 804 | { |
3f8ed54a | 805 | int min, hw_min, max, hw_max, cpu; |
74da56ce KCA |
806 | u64 value, cap; |
807 | ||
111b8b3f | 808 | for_each_cpu(cpu, policy->cpus) { |
8442885f SP |
809 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
810 | s16 epp; | |
eae48f04 | 811 | |
f9f4872d SP |
812 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
813 | hw_min = HWP_LOWEST_PERF(cap); | |
7de32556 | 814 | if (global.no_turbo) |
4e5d3f71 SP |
815 | hw_max = HWP_GUARANTEED_PERF(cap); |
816 | else | |
817 | hw_max = HWP_HIGHEST_PERF(cap); | |
f9f4872d | 818 | |
e14cf885 | 819 | max = fp_ext_toint(hw_max * cpu_data->max_perf); |
7de32556 RW |
820 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) |
821 | min = max; | |
822 | else | |
e14cf885 | 823 | min = fp_ext_toint(hw_max * cpu_data->min_perf); |
eae48f04 | 824 | |
2f86dc4c | 825 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
3f8ed54a | 826 | |
2f86dc4c DB |
827 | value &= ~HWP_MIN_PERF(~0L); |
828 | value |= HWP_MIN_PERF(min); | |
829 | ||
2f86dc4c DB |
830 | value &= ~HWP_MAX_PERF(~0L); |
831 | value |= HWP_MAX_PERF(max); | |
8442885f SP |
832 | |
833 | if (cpu_data->epp_policy == cpu_data->policy) | |
834 | goto skip_epp; | |
835 | ||
836 | cpu_data->epp_policy = cpu_data->policy; | |
837 | ||
984edbdc SP |
838 | if (cpu_data->epp_saved >= 0) { |
839 | epp = cpu_data->epp_saved; | |
840 | cpu_data->epp_saved = -EINVAL; | |
841 | goto update_epp; | |
842 | } | |
843 | ||
8442885f SP |
844 | if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) { |
845 | epp = intel_pstate_get_epp(cpu_data, value); | |
984edbdc | 846 | cpu_data->epp_powersave = epp; |
8442885f | 847 | /* If EPP read was failed, then don't try to write */ |
984edbdc | 848 | if (epp < 0) |
8442885f | 849 | goto skip_epp; |
8442885f | 850 | |
8442885f SP |
851 | |
852 | epp = 0; | |
853 | } else { | |
854 | /* skip setting EPP, when saved value is invalid */ | |
984edbdc | 855 | if (cpu_data->epp_powersave < 0) |
8442885f SP |
856 | goto skip_epp; |
857 | ||
858 | /* | |
859 | * No need to restore EPP when it is not zero. This | |
860 | * means: | |
861 | * - Policy is not changed | |
862 | * - user has manually changed | |
863 | * - Error reading EPB | |
864 | */ | |
865 | epp = intel_pstate_get_epp(cpu_data, value); | |
866 | if (epp) | |
867 | goto skip_epp; | |
868 | ||
984edbdc | 869 | epp = cpu_data->epp_powersave; |
8442885f | 870 | } |
984edbdc | 871 | update_epp: |
8442885f SP |
872 | if (static_cpu_has(X86_FEATURE_HWP_EPP)) { |
873 | value &= ~GENMASK_ULL(31, 24); | |
874 | value |= (u64)epp << 24; | |
875 | } else { | |
876 | intel_pstate_set_epb(cpu, epp); | |
877 | } | |
878 | skip_epp: | |
2f86dc4c DB |
879 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); |
880 | } | |
41cfd64c | 881 | } |
2f86dc4c | 882 | |
984edbdc SP |
883 | static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy) |
884 | { | |
885 | struct cpudata *cpu_data = all_cpu_data[policy->cpu]; | |
886 | ||
887 | if (!hwp_active) | |
888 | return 0; | |
889 | ||
890 | cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0); | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
8442885f SP |
895 | static int intel_pstate_resume(struct cpufreq_policy *policy) |
896 | { | |
897 | if (!hwp_active) | |
898 | return 0; | |
899 | ||
aa439248 RW |
900 | mutex_lock(&intel_pstate_limits_lock); |
901 | ||
8442885f | 902 | all_cpu_data[policy->cpu]->epp_policy = 0; |
5f98ced1 | 903 | intel_pstate_hwp_set(policy); |
aa439248 RW |
904 | |
905 | mutex_unlock(&intel_pstate_limits_lock); | |
906 | ||
5f98ced1 | 907 | return 0; |
8442885f SP |
908 | } |
909 | ||
111b8b3f | 910 | static void intel_pstate_update_policies(void) |
41cfd64c | 911 | { |
111b8b3f RW |
912 | int cpu; |
913 | ||
914 | for_each_possible_cpu(cpu) | |
915 | cpufreq_update_policy(cpu); | |
2f86dc4c DB |
916 | } |
917 | ||
93f0822d DB |
918 | /************************** debugfs begin ************************/ |
919 | static int pid_param_set(void *data, u64 val) | |
920 | { | |
4ddd0146 RW |
921 | unsigned int cpu; |
922 | ||
93f0822d | 923 | *(u32 *)data = val; |
6e7408ac | 924 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
4ddd0146 RW |
925 | for_each_possible_cpu(cpu) |
926 | if (all_cpu_data[cpu]) | |
ff35f02e | 927 | intel_pstate_pid_reset(all_cpu_data[cpu]); |
4ddd0146 | 928 | |
93f0822d DB |
929 | return 0; |
930 | } | |
845c1cbe | 931 | |
93f0822d DB |
932 | static int pid_param_get(void *data, u64 *val) |
933 | { | |
934 | *val = *(u32 *)data; | |
935 | return 0; | |
936 | } | |
2d8d1f18 | 937 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d | 938 | |
fb1fe104 RW |
939 | static struct dentry *debugfs_parent; |
940 | ||
93f0822d DB |
941 | struct pid_param { |
942 | char *name; | |
943 | void *value; | |
fb1fe104 | 944 | struct dentry *dentry; |
93f0822d DB |
945 | }; |
946 | ||
947 | static struct pid_param pid_files[] = { | |
fb1fe104 RW |
948 | {"sample_rate_ms", &pid_params.sample_rate_ms, }, |
949 | {"d_gain_pct", &pid_params.d_gain_pct, }, | |
950 | {"i_gain_pct", &pid_params.i_gain_pct, }, | |
951 | {"deadband", &pid_params.deadband, }, | |
952 | {"setpoint", &pid_params.setpoint, }, | |
953 | {"p_gain_pct", &pid_params.p_gain_pct, }, | |
954 | {NULL, NULL, } | |
93f0822d DB |
955 | }; |
956 | ||
fb1fe104 | 957 | static void intel_pstate_debug_expose_params(void) |
93f0822d | 958 | { |
fb1fe104 | 959 | int i; |
93f0822d DB |
960 | |
961 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); | |
962 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
963 | return; | |
fb1fe104 RW |
964 | |
965 | for (i = 0; pid_files[i].name; i++) { | |
966 | struct dentry *dentry; | |
967 | ||
968 | dentry = debugfs_create_file(pid_files[i].name, 0660, | |
969 | debugfs_parent, pid_files[i].value, | |
970 | &fops_pid_param); | |
971 | if (!IS_ERR(dentry)) | |
972 | pid_files[i].dentry = dentry; | |
93f0822d DB |
973 | } |
974 | } | |
975 | ||
fb1fe104 RW |
976 | static void intel_pstate_debug_hide_params(void) |
977 | { | |
978 | int i; | |
979 | ||
980 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
981 | return; | |
982 | ||
983 | for (i = 0; pid_files[i].name; i++) { | |
984 | debugfs_remove(pid_files[i].dentry); | |
985 | pid_files[i].dentry = NULL; | |
93f0822d | 986 | } |
fb1fe104 RW |
987 | |
988 | debugfs_remove(debugfs_parent); | |
989 | debugfs_parent = NULL; | |
93f0822d DB |
990 | } |
991 | ||
992 | /************************** debugfs end ************************/ | |
993 | ||
994 | /************************** sysfs begin ************************/ | |
995 | #define show_one(file_name, object) \ | |
996 | static ssize_t show_##file_name \ | |
997 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
998 | { \ | |
7de32556 | 999 | return sprintf(buf, "%u\n", global.object); \ |
93f0822d DB |
1000 | } |
1001 | ||
fb1fe104 RW |
1002 | static ssize_t intel_pstate_show_status(char *buf); |
1003 | static int intel_pstate_update_status(const char *buf, size_t size); | |
1004 | ||
1005 | static ssize_t show_status(struct kobject *kobj, | |
1006 | struct attribute *attr, char *buf) | |
1007 | { | |
1008 | ssize_t ret; | |
1009 | ||
1010 | mutex_lock(&intel_pstate_driver_lock); | |
1011 | ret = intel_pstate_show_status(buf); | |
1012 | mutex_unlock(&intel_pstate_driver_lock); | |
1013 | ||
1014 | return ret; | |
1015 | } | |
1016 | ||
1017 | static ssize_t store_status(struct kobject *a, struct attribute *b, | |
1018 | const char *buf, size_t count) | |
1019 | { | |
1020 | char *p = memchr(buf, '\n', count); | |
1021 | int ret; | |
1022 | ||
1023 | mutex_lock(&intel_pstate_driver_lock); | |
1024 | ret = intel_pstate_update_status(buf, p ? p - buf : count); | |
1025 | mutex_unlock(&intel_pstate_driver_lock); | |
1026 | ||
1027 | return ret < 0 ? ret : count; | |
1028 | } | |
1029 | ||
d01b1f48 KCA |
1030 | static ssize_t show_turbo_pct(struct kobject *kobj, |
1031 | struct attribute *attr, char *buf) | |
1032 | { | |
1033 | struct cpudata *cpu; | |
1034 | int total, no_turbo, turbo_pct; | |
1035 | uint32_t turbo_fp; | |
1036 | ||
0c30b65b RW |
1037 | mutex_lock(&intel_pstate_driver_lock); |
1038 | ||
ee8df89a | 1039 | if (!intel_pstate_driver) { |
0c30b65b RW |
1040 | mutex_unlock(&intel_pstate_driver_lock); |
1041 | return -EAGAIN; | |
1042 | } | |
1043 | ||
d01b1f48 KCA |
1044 | cpu = all_cpu_data[0]; |
1045 | ||
1046 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
1047 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 1048 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 | 1049 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
0c30b65b RW |
1050 | |
1051 | mutex_unlock(&intel_pstate_driver_lock); | |
1052 | ||
d01b1f48 KCA |
1053 | return sprintf(buf, "%u\n", turbo_pct); |
1054 | } | |
1055 | ||
0522424e KCA |
1056 | static ssize_t show_num_pstates(struct kobject *kobj, |
1057 | struct attribute *attr, char *buf) | |
1058 | { | |
1059 | struct cpudata *cpu; | |
1060 | int total; | |
1061 | ||
0c30b65b RW |
1062 | mutex_lock(&intel_pstate_driver_lock); |
1063 | ||
ee8df89a | 1064 | if (!intel_pstate_driver) { |
0c30b65b RW |
1065 | mutex_unlock(&intel_pstate_driver_lock); |
1066 | return -EAGAIN; | |
1067 | } | |
1068 | ||
0522424e KCA |
1069 | cpu = all_cpu_data[0]; |
1070 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
0c30b65b RW |
1071 | |
1072 | mutex_unlock(&intel_pstate_driver_lock); | |
1073 | ||
0522424e KCA |
1074 | return sprintf(buf, "%u\n", total); |
1075 | } | |
1076 | ||
4521e1a0 GM |
1077 | static ssize_t show_no_turbo(struct kobject *kobj, |
1078 | struct attribute *attr, char *buf) | |
1079 | { | |
1080 | ssize_t ret; | |
1081 | ||
0c30b65b RW |
1082 | mutex_lock(&intel_pstate_driver_lock); |
1083 | ||
ee8df89a | 1084 | if (!intel_pstate_driver) { |
0c30b65b RW |
1085 | mutex_unlock(&intel_pstate_driver_lock); |
1086 | return -EAGAIN; | |
1087 | } | |
1088 | ||
4521e1a0 | 1089 | update_turbo_state(); |
7de32556 RW |
1090 | if (global.turbo_disabled) |
1091 | ret = sprintf(buf, "%u\n", global.turbo_disabled); | |
4521e1a0 | 1092 | else |
7de32556 | 1093 | ret = sprintf(buf, "%u\n", global.no_turbo); |
4521e1a0 | 1094 | |
0c30b65b RW |
1095 | mutex_unlock(&intel_pstate_driver_lock); |
1096 | ||
4521e1a0 GM |
1097 | return ret; |
1098 | } | |
1099 | ||
93f0822d | 1100 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 1101 | const char *buf, size_t count) |
93f0822d DB |
1102 | { |
1103 | unsigned int input; | |
1104 | int ret; | |
845c1cbe | 1105 | |
93f0822d DB |
1106 | ret = sscanf(buf, "%u", &input); |
1107 | if (ret != 1) | |
1108 | return -EINVAL; | |
4521e1a0 | 1109 | |
0c30b65b RW |
1110 | mutex_lock(&intel_pstate_driver_lock); |
1111 | ||
ee8df89a | 1112 | if (!intel_pstate_driver) { |
0c30b65b RW |
1113 | mutex_unlock(&intel_pstate_driver_lock); |
1114 | return -EAGAIN; | |
1115 | } | |
1116 | ||
a410c03d SP |
1117 | mutex_lock(&intel_pstate_limits_lock); |
1118 | ||
4521e1a0 | 1119 | update_turbo_state(); |
7de32556 | 1120 | if (global.turbo_disabled) { |
4836df17 | 1121 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
a410c03d | 1122 | mutex_unlock(&intel_pstate_limits_lock); |
0c30b65b | 1123 | mutex_unlock(&intel_pstate_driver_lock); |
4521e1a0 | 1124 | return -EPERM; |
dd5fbf70 | 1125 | } |
2f86dc4c | 1126 | |
7de32556 | 1127 | global.no_turbo = clamp_t(int, input, 0, 1); |
111b8b3f | 1128 | |
c5a2ee7d RW |
1129 | if (global.no_turbo) { |
1130 | struct cpudata *cpu = all_cpu_data[0]; | |
1131 | int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate; | |
1132 | ||
1133 | /* Squash the global minimum into the permitted range. */ | |
1134 | if (global.min_perf_pct > pct) | |
1135 | global.min_perf_pct = pct; | |
1136 | } | |
1137 | ||
cd59b4be RW |
1138 | mutex_unlock(&intel_pstate_limits_lock); |
1139 | ||
7de32556 RW |
1140 | intel_pstate_update_policies(); |
1141 | ||
0c30b65b RW |
1142 | mutex_unlock(&intel_pstate_driver_lock); |
1143 | ||
93f0822d DB |
1144 | return count; |
1145 | } | |
1146 | ||
1147 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 1148 | const char *buf, size_t count) |
93f0822d DB |
1149 | { |
1150 | unsigned int input; | |
1151 | int ret; | |
845c1cbe | 1152 | |
93f0822d DB |
1153 | ret = sscanf(buf, "%u", &input); |
1154 | if (ret != 1) | |
1155 | return -EINVAL; | |
1156 | ||
0c30b65b RW |
1157 | mutex_lock(&intel_pstate_driver_lock); |
1158 | ||
ee8df89a | 1159 | if (!intel_pstate_driver) { |
0c30b65b RW |
1160 | mutex_unlock(&intel_pstate_driver_lock); |
1161 | return -EAGAIN; | |
1162 | } | |
1163 | ||
a410c03d SP |
1164 | mutex_lock(&intel_pstate_limits_lock); |
1165 | ||
c5a2ee7d | 1166 | global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100); |
111b8b3f | 1167 | |
cd59b4be RW |
1168 | mutex_unlock(&intel_pstate_limits_lock); |
1169 | ||
7de32556 RW |
1170 | intel_pstate_update_policies(); |
1171 | ||
0c30b65b RW |
1172 | mutex_unlock(&intel_pstate_driver_lock); |
1173 | ||
93f0822d DB |
1174 | return count; |
1175 | } | |
1176 | ||
1177 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 1178 | const char *buf, size_t count) |
93f0822d DB |
1179 | { |
1180 | unsigned int input; | |
1181 | int ret; | |
845c1cbe | 1182 | |
93f0822d DB |
1183 | ret = sscanf(buf, "%u", &input); |
1184 | if (ret != 1) | |
1185 | return -EINVAL; | |
a0475992 | 1186 | |
0c30b65b RW |
1187 | mutex_lock(&intel_pstate_driver_lock); |
1188 | ||
ee8df89a | 1189 | if (!intel_pstate_driver) { |
0c30b65b RW |
1190 | mutex_unlock(&intel_pstate_driver_lock); |
1191 | return -EAGAIN; | |
1192 | } | |
1193 | ||
a410c03d SP |
1194 | mutex_lock(&intel_pstate_limits_lock); |
1195 | ||
c5a2ee7d RW |
1196 | global.min_perf_pct = clamp_t(int, input, |
1197 | min_perf_pct_min(), global.max_perf_pct); | |
111b8b3f | 1198 | |
cd59b4be RW |
1199 | mutex_unlock(&intel_pstate_limits_lock); |
1200 | ||
7de32556 RW |
1201 | intel_pstate_update_policies(); |
1202 | ||
0c30b65b RW |
1203 | mutex_unlock(&intel_pstate_driver_lock); |
1204 | ||
93f0822d DB |
1205 | return count; |
1206 | } | |
1207 | ||
93f0822d DB |
1208 | show_one(max_perf_pct, max_perf_pct); |
1209 | show_one(min_perf_pct, min_perf_pct); | |
1210 | ||
fb1fe104 | 1211 | define_one_global_rw(status); |
93f0822d DB |
1212 | define_one_global_rw(no_turbo); |
1213 | define_one_global_rw(max_perf_pct); | |
1214 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 1215 | define_one_global_ro(turbo_pct); |
0522424e | 1216 | define_one_global_ro(num_pstates); |
93f0822d DB |
1217 | |
1218 | static struct attribute *intel_pstate_attributes[] = { | |
fb1fe104 | 1219 | &status.attr, |
93f0822d | 1220 | &no_turbo.attr, |
d01b1f48 | 1221 | &turbo_pct.attr, |
0522424e | 1222 | &num_pstates.attr, |
93f0822d DB |
1223 | NULL |
1224 | }; | |
1225 | ||
1226 | static struct attribute_group intel_pstate_attr_group = { | |
1227 | .attrs = intel_pstate_attributes, | |
1228 | }; | |
93f0822d | 1229 | |
317dd50e | 1230 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 1231 | { |
317dd50e | 1232 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
1233 | int rc; |
1234 | ||
1235 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
1236 | &cpu_subsys.dev_root->kobj); | |
eae48f04 SP |
1237 | if (WARN_ON(!intel_pstate_kobject)) |
1238 | return; | |
1239 | ||
2d8d1f18 | 1240 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
eae48f04 SP |
1241 | if (WARN_ON(rc)) |
1242 | return; | |
1243 | ||
1244 | /* | |
1245 | * If per cpu limits are enforced there are no global limits, so | |
1246 | * return without creating max/min_perf_pct attributes | |
1247 | */ | |
1248 | if (per_cpu_limits) | |
1249 | return; | |
1250 | ||
1251 | rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr); | |
1252 | WARN_ON(rc); | |
1253 | ||
1254 | rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr); | |
1255 | WARN_ON(rc); | |
1256 | ||
93f0822d | 1257 | } |
93f0822d | 1258 | /************************** sysfs end ************************/ |
2f86dc4c | 1259 | |
ba88d433 | 1260 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 1261 | { |
f05c9665 | 1262 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
1263 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
1264 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 1265 | |
ba88d433 | 1266 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
8442885f | 1267 | cpudata->epp_policy = 0; |
984edbdc SP |
1268 | if (cpudata->epp_default == -EINVAL) |
1269 | cpudata->epp_default = intel_pstate_get_epp(cpudata, 0); | |
2f86dc4c DB |
1270 | } |
1271 | ||
6e978b22 SP |
1272 | #define MSR_IA32_POWER_CTL_BIT_EE 19 |
1273 | ||
1274 | /* Disable energy efficiency optimization */ | |
1275 | static void intel_pstate_disable_ee(int cpu) | |
1276 | { | |
1277 | u64 power_ctl; | |
1278 | int ret; | |
1279 | ||
1280 | ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl); | |
1281 | if (ret) | |
1282 | return; | |
1283 | ||
1284 | if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) { | |
1285 | pr_info("Disabling energy efficiency optimization\n"); | |
1286 | power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE); | |
1287 | wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl); | |
1288 | } | |
1289 | } | |
1290 | ||
938d21a2 | 1291 | static int atom_get_min_pstate(void) |
19e77c28 DB |
1292 | { |
1293 | u64 value; | |
845c1cbe | 1294 | |
92134bdb | 1295 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1296 | return (value >> 8) & 0x7F; |
19e77c28 DB |
1297 | } |
1298 | ||
938d21a2 | 1299 | static int atom_get_max_pstate(void) |
19e77c28 DB |
1300 | { |
1301 | u64 value; | |
845c1cbe | 1302 | |
92134bdb | 1303 | rdmsrl(MSR_ATOM_CORE_RATIOS, value); |
c16ed060 | 1304 | return (value >> 16) & 0x7F; |
19e77c28 | 1305 | } |
93f0822d | 1306 | |
938d21a2 | 1307 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
1308 | { |
1309 | u64 value; | |
845c1cbe | 1310 | |
92134bdb | 1311 | rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value); |
c16ed060 | 1312 | return value & 0x7F; |
61d8d2ab DB |
1313 | } |
1314 | ||
fdfdb2b1 | 1315 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
1316 | { |
1317 | u64 val; | |
1318 | int32_t vid_fp; | |
1319 | u32 vid; | |
1320 | ||
144c8e17 | 1321 | val = (u64)pstate << 8; |
7de32556 | 1322 | if (global.no_turbo && !global.turbo_disabled) |
007bea09 DB |
1323 | val |= (u64)1 << 32; |
1324 | ||
1325 | vid_fp = cpudata->vid.min + mul_fp( | |
1326 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
1327 | cpudata->vid.ratio); | |
1328 | ||
1329 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 1330 | vid = ceiling_fp(vid_fp); |
007bea09 | 1331 | |
21855ff5 DB |
1332 | if (pstate > cpudata->pstate.max_pstate) |
1333 | vid = cpudata->vid.turbo; | |
1334 | ||
fdfdb2b1 | 1335 | return val | vid; |
007bea09 DB |
1336 | } |
1337 | ||
1421df63 | 1338 | static int silvermont_get_scaling(void) |
b27580b0 DB |
1339 | { |
1340 | u64 value; | |
1341 | int i; | |
1421df63 PL |
1342 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
1343 | static int silvermont_freq_table[] = { | |
1344 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
1345 | |
1346 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
1347 | i = value & 0x7; |
1348 | WARN_ON(i > 4); | |
b27580b0 | 1349 | |
1421df63 PL |
1350 | return silvermont_freq_table[i]; |
1351 | } | |
b27580b0 | 1352 | |
1421df63 PL |
1353 | static int airmont_get_scaling(void) |
1354 | { | |
1355 | u64 value; | |
1356 | int i; | |
1357 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
1358 | static int airmont_freq_table[] = { | |
1359 | 83300, 100000, 133300, 116700, 80000, | |
1360 | 93300, 90000, 88900, 87500}; | |
1361 | ||
1362 | rdmsrl(MSR_FSB_FREQ, value); | |
1363 | i = value & 0xF; | |
1364 | WARN_ON(i > 8); | |
1365 | ||
1366 | return airmont_freq_table[i]; | |
b27580b0 DB |
1367 | } |
1368 | ||
938d21a2 | 1369 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
1370 | { |
1371 | u64 value; | |
1372 | ||
92134bdb | 1373 | rdmsrl(MSR_ATOM_CORE_VIDS, value); |
c16ed060 DB |
1374 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
1375 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
1376 | cpudata->vid.ratio = div_fp( |
1377 | cpudata->vid.max - cpudata->vid.min, | |
1378 | int_tofp(cpudata->pstate.max_pstate - | |
1379 | cpudata->pstate.min_pstate)); | |
21855ff5 | 1380 | |
92134bdb | 1381 | rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value); |
21855ff5 | 1382 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
1383 | } |
1384 | ||
016c8150 | 1385 | static int core_get_min_pstate(void) |
93f0822d DB |
1386 | { |
1387 | u64 value; | |
845c1cbe | 1388 | |
05e99c8c | 1389 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1390 | return (value >> 40) & 0xFF; |
1391 | } | |
1392 | ||
3bcc6fa9 | 1393 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
1394 | { |
1395 | u64 value; | |
845c1cbe | 1396 | |
05e99c8c | 1397 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
1398 | return (value >> 8) & 0xFF; |
1399 | } | |
1400 | ||
8fc7554a SP |
1401 | static int core_get_tdp_ratio(u64 plat_info) |
1402 | { | |
1403 | /* Check how many TDP levels present */ | |
1404 | if (plat_info & 0x600000000) { | |
1405 | u64 tdp_ctrl; | |
1406 | u64 tdp_ratio; | |
1407 | int tdp_msr; | |
1408 | int err; | |
1409 | ||
1410 | /* Get the TDP level (0, 1, 2) to get ratios */ | |
1411 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
1412 | if (err) | |
1413 | return err; | |
1414 | ||
1415 | /* TDP MSR are continuous starting at 0x648 */ | |
1416 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03); | |
1417 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
1418 | if (err) | |
1419 | return err; | |
1420 | ||
1421 | /* For level 1 and 2, bits[23:16] contain the ratio */ | |
1422 | if (tdp_ctrl & 0x03) | |
1423 | tdp_ratio >>= 16; | |
1424 | ||
1425 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
1426 | pr_debug("tdp_ratio %x\n", (int)tdp_ratio); | |
1427 | ||
1428 | return (int)tdp_ratio; | |
1429 | } | |
1430 | ||
1431 | return -ENXIO; | |
1432 | } | |
1433 | ||
016c8150 | 1434 | static int core_get_max_pstate(void) |
93f0822d | 1435 | { |
6a35fc2d SP |
1436 | u64 tar; |
1437 | u64 plat_info; | |
1438 | int max_pstate; | |
8fc7554a | 1439 | int tdp_ratio; |
6a35fc2d SP |
1440 | int err; |
1441 | ||
1442 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
1443 | max_pstate = (plat_info >> 8) & 0xFF; | |
1444 | ||
8fc7554a SP |
1445 | tdp_ratio = core_get_tdp_ratio(plat_info); |
1446 | if (tdp_ratio <= 0) | |
1447 | return max_pstate; | |
1448 | ||
1449 | if (hwp_active) { | |
1450 | /* Turbo activation ratio is not used on HWP platforms */ | |
1451 | return tdp_ratio; | |
1452 | } | |
1453 | ||
6a35fc2d SP |
1454 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); |
1455 | if (!err) { | |
8fc7554a SP |
1456 | int tar_levels; |
1457 | ||
6a35fc2d | 1458 | /* Do some sanity checking for safety */ |
8fc7554a SP |
1459 | tar_levels = tar & 0xff; |
1460 | if (tdp_ratio - 1 == tar_levels) { | |
1461 | max_pstate = tar_levels; | |
1462 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
6a35fc2d SP |
1463 | } |
1464 | } | |
845c1cbe | 1465 | |
6a35fc2d | 1466 | return max_pstate; |
93f0822d DB |
1467 | } |
1468 | ||
016c8150 | 1469 | static int core_get_turbo_pstate(void) |
93f0822d DB |
1470 | { |
1471 | u64 value; | |
1472 | int nont, ret; | |
845c1cbe | 1473 | |
100cf6f2 | 1474 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 1475 | nont = core_get_max_pstate(); |
285cb990 | 1476 | ret = (value) & 255; |
93f0822d DB |
1477 | if (ret <= nont) |
1478 | ret = nont; | |
1479 | return ret; | |
1480 | } | |
1481 | ||
b27580b0 DB |
1482 | static inline int core_get_scaling(void) |
1483 | { | |
1484 | return 100000; | |
1485 | } | |
1486 | ||
fdfdb2b1 | 1487 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
1488 | { |
1489 | u64 val; | |
1490 | ||
144c8e17 | 1491 | val = (u64)pstate << 8; |
7de32556 | 1492 | if (global.no_turbo && !global.turbo_disabled) |
016c8150 DB |
1493 | val |= (u64)1 << 32; |
1494 | ||
fdfdb2b1 | 1495 | return val; |
016c8150 DB |
1496 | } |
1497 | ||
b34ef932 DC |
1498 | static int knl_get_turbo_pstate(void) |
1499 | { | |
1500 | u64 value; | |
1501 | int nont, ret; | |
1502 | ||
100cf6f2 | 1503 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1504 | nont = core_get_max_pstate(); |
1505 | ret = (((value) >> 8) & 0xFF); | |
1506 | if (ret <= nont) | |
1507 | ret = nont; | |
1508 | return ret; | |
1509 | } | |
1510 | ||
67dd9bf4 RW |
1511 | static void intel_pstate_update_util_pid(struct update_util_data *data, |
1512 | u64 time, unsigned int flags); | |
1513 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, | |
1514 | unsigned int flags); | |
1515 | ||
016c8150 | 1516 | static struct cpu_defaults core_params = { |
016c8150 DB |
1517 | .funcs = { |
1518 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1519 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
1520 | .get_min = core_get_min_pstate, |
1521 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 1522 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1523 | .get_val = core_get_val, |
67dd9bf4 | 1524 | .update_util = intel_pstate_update_util_pid, |
016c8150 DB |
1525 | }, |
1526 | }; | |
1527 | ||
42ce8921 | 1528 | static const struct cpu_defaults silvermont_params = { |
1421df63 PL |
1529 | .funcs = { |
1530 | .get_max = atom_get_max_pstate, | |
1531 | .get_max_physical = atom_get_max_pstate, | |
1532 | .get_min = atom_get_min_pstate, | |
1533 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1534 | .get_val = atom_get_val, |
1421df63 PL |
1535 | .get_scaling = silvermont_get_scaling, |
1536 | .get_vid = atom_get_vid, | |
67dd9bf4 | 1537 | .update_util = intel_pstate_update_util, |
1421df63 PL |
1538 | }, |
1539 | }; | |
1540 | ||
42ce8921 | 1541 | static const struct cpu_defaults airmont_params = { |
19e77c28 | 1542 | .funcs = { |
938d21a2 PL |
1543 | .get_max = atom_get_max_pstate, |
1544 | .get_max_physical = atom_get_max_pstate, | |
1545 | .get_min = atom_get_min_pstate, | |
1546 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1547 | .get_val = atom_get_val, |
1421df63 | 1548 | .get_scaling = airmont_get_scaling, |
938d21a2 | 1549 | .get_vid = atom_get_vid, |
67dd9bf4 | 1550 | .update_util = intel_pstate_update_util, |
19e77c28 DB |
1551 | }, |
1552 | }; | |
1553 | ||
42ce8921 | 1554 | static const struct cpu_defaults knl_params = { |
b34ef932 DC |
1555 | .funcs = { |
1556 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1557 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
1558 | .get_min = core_get_min_pstate, |
1559 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 1560 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1561 | .get_val = core_get_val, |
67dd9bf4 | 1562 | .update_util = intel_pstate_update_util_pid, |
b34ef932 DC |
1563 | }, |
1564 | }; | |
1565 | ||
42ce8921 | 1566 | static const struct cpu_defaults bxt_params = { |
41bad47f SP |
1567 | .funcs = { |
1568 | .get_max = core_get_max_pstate, | |
1569 | .get_max_physical = core_get_max_pstate_physical, | |
1570 | .get_min = core_get_min_pstate, | |
1571 | .get_turbo = core_get_turbo_pstate, | |
1572 | .get_scaling = core_get_scaling, | |
1573 | .get_val = core_get_val, | |
67dd9bf4 | 1574 | .update_util = intel_pstate_update_util, |
41bad47f SP |
1575 | }, |
1576 | }; | |
1577 | ||
93f0822d DB |
1578 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
1579 | { | |
1580 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 1581 | int max_perf_adj; |
93f0822d | 1582 | int min_perf; |
845c1cbe | 1583 | |
7de32556 | 1584 | if (global.no_turbo || global.turbo_disabled) |
93f0822d DB |
1585 | max_perf = cpu->pstate.max_pstate; |
1586 | ||
e0d4c8f8 KCA |
1587 | /* |
1588 | * performance can be limited by user through sysfs, by cpufreq | |
1589 | * policy, or by cpu specific default values determined through | |
1590 | * experimentation. | |
1591 | */ | |
e14cf885 | 1592 | max_perf_adj = fp_ext_toint(max_perf * cpu->max_perf); |
799281a3 RW |
1593 | *max = clamp_t(int, max_perf_adj, |
1594 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 1595 | |
e14cf885 | 1596 | min_perf = fp_ext_toint(max_perf * cpu->min_perf); |
799281a3 | 1597 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
1598 | } |
1599 | ||
a6c6ead1 | 1600 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) |
fdfdb2b1 | 1601 | { |
bc95a454 RW |
1602 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1603 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1604 | /* |
1605 | * Generally, there is no guarantee that this code will always run on | |
1606 | * the CPU being updated, so force the register update to run on the | |
1607 | * right CPU. | |
1608 | */ | |
1609 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1610 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1611 | } |
1612 | ||
a6c6ead1 RW |
1613 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1614 | { | |
1615 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); | |
1616 | } | |
1617 | ||
1618 | static void intel_pstate_max_within_limits(struct cpudata *cpu) | |
1619 | { | |
1620 | int min_pstate, max_pstate; | |
1621 | ||
1622 | update_turbo_state(); | |
1623 | intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate); | |
1624 | intel_pstate_set_pstate(cpu, max_pstate); | |
1625 | } | |
1626 | ||
93f0822d DB |
1627 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1628 | { | |
016c8150 DB |
1629 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1630 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1631 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1632 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1633 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
001c76f0 RW |
1634 | cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling; |
1635 | cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d | 1636 | |
007bea09 DB |
1637 | if (pstate_funcs.get_vid) |
1638 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1639 | |
1640 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1641 | } |
1642 | ||
a1c9787d | 1643 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1644 | { |
6b17ddb2 | 1645 | struct sample *sample = &cpu->sample; |
e66c1768 | 1646 | |
a1c9787d | 1647 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1648 | } |
1649 | ||
4fec7ad5 | 1650 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1651 | { |
93f0822d | 1652 | u64 aperf, mperf; |
4ab60c3f | 1653 | unsigned long flags; |
4055fad3 | 1654 | u64 tsc; |
93f0822d | 1655 | |
4ab60c3f | 1656 | local_irq_save(flags); |
93f0822d DB |
1657 | rdmsrl(MSR_IA32_APERF, aperf); |
1658 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1659 | tsc = rdtsc(); |
4fec7ad5 | 1660 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1661 | local_irq_restore(flags); |
4fec7ad5 | 1662 | return false; |
8e601a9f | 1663 | } |
4ab60c3f | 1664 | local_irq_restore(flags); |
b69880f9 | 1665 | |
c4ee841f | 1666 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1667 | cpu->sample.time = time; |
d37e2b76 DB |
1668 | cpu->sample.aperf = aperf; |
1669 | cpu->sample.mperf = mperf; | |
4055fad3 | 1670 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1671 | cpu->sample.aperf -= cpu->prev_aperf; |
1672 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1673 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1674 | |
93f0822d DB |
1675 | cpu->prev_aperf = aperf; |
1676 | cpu->prev_mperf = mperf; | |
4055fad3 | 1677 | cpu->prev_tsc = tsc; |
febce40f RW |
1678 | /* |
1679 | * First time this function is invoked in a given cycle, all of the | |
1680 | * previous sample data fields are equal to zero or stale and they must | |
1681 | * be populated with meaningful numbers for things to work, so assume | |
1682 | * that sample.time will always be reset before setting the utilization | |
1683 | * update hook and make the caller skip the sample then. | |
1684 | */ | |
eabd22c6 RW |
1685 | if (cpu->last_sample_time) { |
1686 | intel_pstate_calc_avg_perf(cpu); | |
1687 | return true; | |
1688 | } | |
1689 | return false; | |
93f0822d DB |
1690 | } |
1691 | ||
8fa520af PL |
1692 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1693 | { | |
a1c9787d RW |
1694 | return mul_ext_fp(cpu->sample.core_avg_perf, |
1695 | cpu->pstate.max_pstate_physical * cpu->pstate.scaling); | |
8fa520af PL |
1696 | } |
1697 | ||
bdcaa23f PL |
1698 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1699 | { | |
8edb0a6e RW |
1700 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1701 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1702 | } |
1703 | ||
e70eed2b PL |
1704 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
1705 | { | |
1706 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1707 | int32_t busy_frac, boost; |
0843e83c | 1708 | int target, avg_pstate; |
e70eed2b | 1709 | |
67dd9bf4 RW |
1710 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) |
1711 | return cpu->pstate.turbo_pstate; | |
1712 | ||
09c448d3 | 1713 | busy_frac = div_fp(sample->mperf, sample->tsc); |
63d1d656 | 1714 | |
09c448d3 RW |
1715 | boost = cpu->iowait_boost; |
1716 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1717 | |
09c448d3 RW |
1718 | if (busy_frac < boost) |
1719 | busy_frac = boost; | |
63d1d656 | 1720 | |
09c448d3 | 1721 | sample->busy_scaled = busy_frac * 100; |
0843e83c | 1722 | |
7de32556 | 1723 | target = global.no_turbo || global.turbo_disabled ? |
0843e83c RW |
1724 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
1725 | target += target >> 2; | |
1726 | target = mul_fp(target, busy_frac); | |
1727 | if (target < cpu->pstate.min_pstate) | |
1728 | target = cpu->pstate.min_pstate; | |
1729 | ||
1730 | /* | |
1731 | * If the average P-state during the previous cycle was higher than the | |
1732 | * current target, add 50% of the difference to the target to reduce | |
1733 | * possible performance oscillations and offset possible performance | |
1734 | * loss related to moving the workload from one CPU to another within | |
1735 | * a package/module. | |
1736 | */ | |
1737 | avg_pstate = get_avg_pstate(cpu); | |
1738 | if (avg_pstate > target) | |
1739 | target += (avg_pstate - target) >> 1; | |
1740 | ||
1741 | return target; | |
e70eed2b PL |
1742 | } |
1743 | ||
157386b6 | 1744 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 1745 | { |
1aa7a6e2 | 1746 | int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; |
a4675fbc | 1747 | u64 duration_ns; |
93f0822d | 1748 | |
67dd9bf4 RW |
1749 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) |
1750 | return cpu->pstate.turbo_pstate; | |
1751 | ||
e0d4c8f8 | 1752 | /* |
f00593a4 RW |
1753 | * perf_scaled is the ratio of the average P-state during the last |
1754 | * sampling period to the P-state requested last time (in percent). | |
1755 | * | |
1756 | * That measures the system's response to the previous P-state | |
1757 | * selection. | |
e0d4c8f8 | 1758 | */ |
22590efb RW |
1759 | max_pstate = cpu->pstate.max_pstate_physical; |
1760 | current_pstate = cpu->pstate.current_pstate; | |
1aa7a6e2 | 1761 | perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, |
a1c9787d | 1762 | div_fp(100 * max_pstate, current_pstate)); |
c4ee841f | 1763 | |
e0d4c8f8 | 1764 | /* |
a4675fbc RW |
1765 | * Since our utilization update callback will not run unless we are |
1766 | * in C0, check if the actual elapsed time is significantly greater (3x) | |
1767 | * than our sample interval. If it is, then we were idle for a long | |
1aa7a6e2 | 1768 | * enough period of time to adjust our performance metric. |
e0d4c8f8 | 1769 | */ |
a4675fbc | 1770 | duration_ns = cpu->sample.time - cpu->last_sample_time; |
febce40f | 1771 | if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { |
22590efb | 1772 | sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); |
1aa7a6e2 | 1773 | perf_scaled = mul_fp(perf_scaled, sample_ratio); |
ffb81056 RW |
1774 | } else { |
1775 | sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); | |
1776 | if (sample_ratio < int_tofp(1)) | |
1aa7a6e2 | 1777 | perf_scaled = 0; |
c4ee841f DB |
1778 | } |
1779 | ||
1aa7a6e2 RW |
1780 | cpu->sample.busy_scaled = perf_scaled; |
1781 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); | |
93f0822d DB |
1782 | } |
1783 | ||
001c76f0 | 1784 | static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate) |
fdfdb2b1 RW |
1785 | { |
1786 | int max_perf, min_perf; | |
1787 | ||
fdfdb2b1 RW |
1788 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
1789 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
001c76f0 RW |
1790 | return pstate; |
1791 | } | |
1792 | ||
1793 | static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) | |
1794 | { | |
fdfdb2b1 RW |
1795 | if (pstate == cpu->pstate.current_pstate) |
1796 | return; | |
1797 | ||
bc95a454 | 1798 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1799 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1800 | } | |
1801 | ||
67dd9bf4 | 1802 | static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate) |
93f0822d | 1803 | { |
67dd9bf4 | 1804 | int from = cpu->pstate.current_pstate; |
4055fad3 DS |
1805 | struct sample *sample; |
1806 | ||
001c76f0 RW |
1807 | update_turbo_state(); |
1808 | ||
64078299 RW |
1809 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
1810 | trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu); | |
fdfdb2b1 | 1811 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1812 | |
1813 | sample = &cpu->sample; | |
a1c9787d | 1814 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1815 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1816 | from, |
1817 | cpu->pstate.current_pstate, | |
1818 | sample->mperf, | |
1819 | sample->aperf, | |
1820 | sample->tsc, | |
3ba7bcaa SP |
1821 | get_avg_frequency(cpu), |
1822 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1823 | } |
1824 | ||
eabd22c6 RW |
1825 | static void intel_pstate_update_util_hwp(struct update_util_data *data, |
1826 | u64 time, unsigned int flags) | |
1827 | { | |
1828 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); | |
1829 | u64 delta_ns = time - cpu->sample.time; | |
1830 | ||
1831 | if ((s64)delta_ns >= INTEL_PSTATE_HWP_SAMPLING_INTERVAL) | |
1832 | intel_pstate_sample(cpu, time); | |
1833 | } | |
1834 | ||
1835 | static void intel_pstate_update_util_pid(struct update_util_data *data, | |
1836 | u64 time, unsigned int flags) | |
1837 | { | |
1838 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); | |
1839 | u64 delta_ns = time - cpu->sample.time; | |
1840 | ||
1841 | if ((s64)delta_ns < pid_params.sample_rate_ns) | |
1842 | return; | |
1843 | ||
67dd9bf4 RW |
1844 | if (intel_pstate_sample(cpu, time)) { |
1845 | int target_pstate; | |
1846 | ||
1847 | target_pstate = get_target_pstate_use_performance(cpu); | |
1848 | intel_pstate_adjust_pstate(cpu, target_pstate); | |
1849 | } | |
eabd22c6 RW |
1850 | } |
1851 | ||
a4675fbc | 1852 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1853 | unsigned int flags) |
93f0822d | 1854 | { |
a4675fbc | 1855 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1856 | u64 delta_ns; |
1857 | ||
eabd22c6 RW |
1858 | if (flags & SCHED_CPUFREQ_IOWAIT) { |
1859 | cpu->iowait_boost = int_tofp(1); | |
1860 | } else if (cpu->iowait_boost) { | |
1861 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1862 | delta_ns = time - cpu->last_update; | |
1863 | if (delta_ns > TICK_NSEC) | |
1864 | cpu->iowait_boost = 0; | |
09c448d3 | 1865 | } |
eabd22c6 | 1866 | cpu->last_update = time; |
09c448d3 | 1867 | delta_ns = time - cpu->sample.time; |
eabd22c6 RW |
1868 | if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL) |
1869 | return; | |
4fec7ad5 | 1870 | |
67dd9bf4 RW |
1871 | if (intel_pstate_sample(cpu, time)) { |
1872 | int target_pstate; | |
93f0822d | 1873 | |
67dd9bf4 RW |
1874 | target_pstate = get_target_pstate_use_cpu_load(cpu); |
1875 | intel_pstate_adjust_pstate(cpu, target_pstate); | |
1876 | } | |
1877 | } | |
eabd22c6 | 1878 | |
93f0822d | 1879 | #define ICPU(model, policy) \ |
6cbd7ee1 DB |
1880 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1881 | (unsigned long)&policy } | |
93f0822d DB |
1882 | |
1883 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
5b20c944 DH |
1884 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), |
1885 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), | |
1886 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), | |
1887 | ICPU(INTEL_FAM6_IVYBRIDGE, core_params), | |
1888 | ICPU(INTEL_FAM6_HASWELL_CORE, core_params), | |
1889 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), | |
1890 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), | |
1891 | ICPU(INTEL_FAM6_HASWELL_X, core_params), | |
1892 | ICPU(INTEL_FAM6_HASWELL_ULT, core_params), | |
1893 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), | |
1894 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), | |
1895 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), | |
1896 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), | |
1897 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), | |
1898 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), | |
1899 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), | |
1900 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), | |
58bf4542 | 1901 | ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params), |
41bad47f | 1902 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), |
93f0822d DB |
1903 | {} |
1904 | }; | |
1905 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1906 | ||
29327c84 | 1907 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
5b20c944 | 1908 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), |
65c1262f SP |
1909 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), |
1910 | ICPU(INTEL_FAM6_SKYLAKE_X, core_params), | |
2f86dc4c DB |
1911 | {} |
1912 | }; | |
1913 | ||
6e978b22 SP |
1914 | static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = { |
1915 | ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params), | |
1916 | {} | |
1917 | }; | |
1918 | ||
93f0822d DB |
1919 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1920 | { | |
93f0822d DB |
1921 | struct cpudata *cpu; |
1922 | ||
eae48f04 SP |
1923 | cpu = all_cpu_data[cpunum]; |
1924 | ||
1925 | if (!cpu) { | |
c5a2ee7d | 1926 | cpu = kzalloc(sizeof(*cpu), GFP_KERNEL); |
eae48f04 SP |
1927 | if (!cpu) |
1928 | return -ENOMEM; | |
1929 | ||
1930 | all_cpu_data[cpunum] = cpu; | |
eae48f04 | 1931 | |
984edbdc SP |
1932 | cpu->epp_default = -EINVAL; |
1933 | cpu->epp_powersave = -EINVAL; | |
1934 | cpu->epp_saved = -EINVAL; | |
eae48f04 | 1935 | } |
93f0822d DB |
1936 | |
1937 | cpu = all_cpu_data[cpunum]; | |
1938 | ||
93f0822d | 1939 | cpu->cpu = cpunum; |
ba88d433 | 1940 | |
a4675fbc | 1941 | if (hwp_active) { |
6e978b22 SP |
1942 | const struct x86_cpu_id *id; |
1943 | ||
1944 | id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids); | |
1945 | if (id) | |
1946 | intel_pstate_disable_ee(cpunum); | |
1947 | ||
ba88d433 | 1948 | intel_pstate_hwp_enable(cpu); |
67dd9bf4 | 1949 | } else if (pstate_funcs.update_util == intel_pstate_update_util_pid) { |
694cb173 | 1950 | intel_pstate_pid_reset(cpu); |
a4675fbc | 1951 | } |
ba88d433 | 1952 | |
179e8471 | 1953 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1954 | |
4836df17 | 1955 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
1956 | |
1957 | return 0; | |
1958 | } | |
1959 | ||
1960 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1961 | { | |
f96fd0c8 | 1962 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
93f0822d | 1963 | |
f96fd0c8 | 1964 | return cpu ? get_avg_frequency(cpu) : 0; |
93f0822d DB |
1965 | } |
1966 | ||
febce40f | 1967 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1968 | { |
febce40f RW |
1969 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1970 | ||
5ab666e0 RW |
1971 | if (cpu->update_util_set) |
1972 | return; | |
1973 | ||
febce40f RW |
1974 | /* Prevent intel_pstate_update_util() from using stale data. */ |
1975 | cpu->sample.time = 0; | |
67dd9bf4 RW |
1976 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
1977 | pstate_funcs.update_util); | |
4578ee7e | 1978 | cpu->update_util_set = true; |
bb6ab52f RW |
1979 | } |
1980 | ||
1981 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1982 | { | |
4578ee7e CY |
1983 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
1984 | ||
1985 | if (!cpu_data->update_util_set) | |
1986 | return; | |
1987 | ||
0bed612b | 1988 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 1989 | cpu_data->update_util_set = false; |
bb6ab52f RW |
1990 | synchronize_sched(); |
1991 | } | |
1992 | ||
80b120ca RW |
1993 | static int intel_pstate_get_max_freq(struct cpudata *cpu) |
1994 | { | |
1995 | return global.turbo_disabled || global.no_turbo ? | |
1996 | cpu->pstate.max_freq : cpu->pstate.turbo_freq; | |
1997 | } | |
1998 | ||
eae48f04 | 1999 | static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy, |
c5a2ee7d | 2000 | struct cpudata *cpu) |
eae48f04 | 2001 | { |
80b120ca | 2002 | int max_freq = intel_pstate_get_max_freq(cpu); |
e4c204ce | 2003 | int32_t max_policy_perf, min_policy_perf; |
a410c03d | 2004 | |
80b120ca | 2005 | max_policy_perf = div_ext_fp(policy->max, max_freq); |
e4c204ce | 2006 | max_policy_perf = clamp_t(int32_t, max_policy_perf, 0, int_ext_tofp(1)); |
5879f877 | 2007 | if (policy->max == policy->min) { |
e4c204ce | 2008 | min_policy_perf = max_policy_perf; |
5879f877 | 2009 | } else { |
80b120ca | 2010 | min_policy_perf = div_ext_fp(policy->min, max_freq); |
e4c204ce RW |
2011 | min_policy_perf = clamp_t(int32_t, min_policy_perf, |
2012 | 0, max_policy_perf); | |
5879f877 | 2013 | } |
eae48f04 | 2014 | |
e4c204ce | 2015 | /* Normalize user input to [min_perf, max_perf] */ |
c5a2ee7d | 2016 | if (per_cpu_limits) { |
e14cf885 RW |
2017 | cpu->min_perf = min_policy_perf; |
2018 | cpu->max_perf = max_policy_perf; | |
c5a2ee7d RW |
2019 | } else { |
2020 | int32_t global_min, global_max; | |
2021 | ||
2022 | /* Global limits are in percent of the maximum turbo P-state. */ | |
2023 | global_max = percent_ext_fp(global.max_perf_pct); | |
2024 | global_min = percent_ext_fp(global.min_perf_pct); | |
80b120ca | 2025 | if (max_freq != cpu->pstate.turbo_freq) { |
c5a2ee7d RW |
2026 | int32_t turbo_factor; |
2027 | ||
2028 | turbo_factor = div_ext_fp(cpu->pstate.turbo_pstate, | |
2029 | cpu->pstate.max_pstate); | |
2030 | global_min = mul_ext_fp(global_min, turbo_factor); | |
2031 | global_max = mul_ext_fp(global_max, turbo_factor); | |
2032 | } | |
2033 | global_min = clamp_t(int32_t, global_min, 0, global_max); | |
eae48f04 | 2034 | |
e14cf885 RW |
2035 | cpu->min_perf = max(min_policy_perf, global_min); |
2036 | cpu->min_perf = min(cpu->min_perf, max_policy_perf); | |
2037 | cpu->max_perf = min(max_policy_perf, global_max); | |
2038 | cpu->max_perf = max(min_policy_perf, cpu->max_perf); | |
c5a2ee7d RW |
2039 | |
2040 | /* Make sure min_perf <= max_perf */ | |
e14cf885 | 2041 | cpu->min_perf = min(cpu->min_perf, cpu->max_perf); |
c5a2ee7d | 2042 | } |
eae48f04 | 2043 | |
e14cf885 RW |
2044 | cpu->max_perf = round_up(cpu->max_perf, EXT_FRAC_BITS); |
2045 | cpu->min_perf = round_up(cpu->min_perf, EXT_FRAC_BITS); | |
eae48f04 SP |
2046 | |
2047 | pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu, | |
e14cf885 RW |
2048 | fp_ext_toint(cpu->max_perf * 100), |
2049 | fp_ext_toint(cpu->min_perf * 100)); | |
eae48f04 SP |
2050 | } |
2051 | ||
93f0822d DB |
2052 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
2053 | { | |
3be9200d SP |
2054 | struct cpudata *cpu; |
2055 | ||
d3929b83 DB |
2056 | if (!policy->cpuinfo.max_freq) |
2057 | return -ENODEV; | |
2058 | ||
2c2c1af4 SP |
2059 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
2060 | policy->cpuinfo.max_freq, policy->max); | |
2061 | ||
a6c6ead1 | 2062 | cpu = all_cpu_data[policy->cpu]; |
2f1d407a RW |
2063 | cpu->policy = policy->policy; |
2064 | ||
b59fe540 SP |
2065 | mutex_lock(&intel_pstate_limits_lock); |
2066 | ||
c5a2ee7d | 2067 | intel_pstate_update_perf_limits(policy, cpu); |
a240c4aa | 2068 | |
2f1d407a | 2069 | if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) { |
a6c6ead1 RW |
2070 | /* |
2071 | * NOHZ_FULL CPUs need this as the governor callback may not | |
2072 | * be invoked on them. | |
2073 | */ | |
2074 | intel_pstate_clear_update_util_hook(policy->cpu); | |
2075 | intel_pstate_max_within_limits(cpu); | |
2076 | } | |
2077 | ||
bb6ab52f RW |
2078 | intel_pstate_set_update_util_hook(policy->cpu); |
2079 | ||
5f98ced1 RW |
2080 | if (hwp_active) |
2081 | intel_pstate_hwp_set(policy); | |
2f86dc4c | 2082 | |
b59fe540 SP |
2083 | mutex_unlock(&intel_pstate_limits_lock); |
2084 | ||
93f0822d DB |
2085 | return 0; |
2086 | } | |
2087 | ||
80b120ca RW |
2088 | static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy, |
2089 | struct cpudata *cpu) | |
2090 | { | |
2091 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && | |
2092 | policy->max < policy->cpuinfo.max_freq && | |
2093 | policy->max > cpu->pstate.max_freq) { | |
2094 | pr_debug("policy->max > max non turbo frequency\n"); | |
2095 | policy->max = policy->cpuinfo.max_freq; | |
2096 | } | |
2097 | } | |
2098 | ||
93f0822d DB |
2099 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) |
2100 | { | |
7d9a8a9f | 2101 | struct cpudata *cpu = all_cpu_data[policy->cpu]; |
7d9a8a9f SP |
2102 | |
2103 | update_turbo_state(); | |
80b120ca RW |
2104 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
2105 | intel_pstate_get_max_freq(cpu)); | |
93f0822d | 2106 | |
285cb990 | 2107 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 2108 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
2109 | return -EINVAL; |
2110 | ||
80b120ca RW |
2111 | intel_pstate_adjust_policy_max(policy, cpu); |
2112 | ||
93f0822d DB |
2113 | return 0; |
2114 | } | |
2115 | ||
001c76f0 RW |
2116 | static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
2117 | { | |
2118 | intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]); | |
2119 | } | |
2120 | ||
bb18008f | 2121 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 2122 | { |
001c76f0 | 2123 | pr_debug("CPU %d exiting\n", policy->cpu); |
93f0822d | 2124 | |
001c76f0 | 2125 | intel_pstate_clear_update_util_hook(policy->cpu); |
984edbdc SP |
2126 | if (hwp_active) |
2127 | intel_pstate_hwp_save_state(policy); | |
2128 | else | |
001c76f0 RW |
2129 | intel_cpufreq_stop_cpu(policy); |
2130 | } | |
bb18008f | 2131 | |
001c76f0 RW |
2132 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
2133 | { | |
2134 | intel_pstate_exit_perf_limits(policy); | |
a4675fbc | 2135 | |
001c76f0 | 2136 | policy->fast_switch_possible = false; |
2f86dc4c | 2137 | |
001c76f0 | 2138 | return 0; |
93f0822d DB |
2139 | } |
2140 | ||
001c76f0 | 2141 | static int __intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 2142 | { |
93f0822d | 2143 | struct cpudata *cpu; |
52e0a509 | 2144 | int rc; |
93f0822d DB |
2145 | |
2146 | rc = intel_pstate_init_cpu(policy->cpu); | |
2147 | if (rc) | |
2148 | return rc; | |
2149 | ||
2150 | cpu = all_cpu_data[policy->cpu]; | |
2151 | ||
e14cf885 RW |
2152 | cpu->max_perf = int_ext_tofp(1); |
2153 | cpu->min_perf = 0; | |
93f0822d | 2154 | |
b27580b0 DB |
2155 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
2156 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
2157 | |
2158 | /* cpuinfo and default policy values */ | |
b27580b0 | 2159 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e | 2160 | update_turbo_state(); |
7de32556 | 2161 | policy->cpuinfo.max_freq = global.turbo_disabled ? |
983e600e SP |
2162 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; |
2163 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
2164 | ||
9522a2ff | 2165 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d DB |
2166 | cpumask_set_cpu(policy->cpu, policy->cpus); |
2167 | ||
001c76f0 RW |
2168 | policy->fast_switch_possible = true; |
2169 | ||
93f0822d DB |
2170 | return 0; |
2171 | } | |
2172 | ||
001c76f0 | 2173 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
9522a2ff | 2174 | { |
001c76f0 RW |
2175 | int ret = __intel_pstate_cpu_init(policy); |
2176 | ||
2177 | if (ret) | |
2178 | return ret; | |
2179 | ||
2180 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
7de32556 | 2181 | if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE)) |
001c76f0 RW |
2182 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
2183 | else | |
2184 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
9522a2ff SP |
2185 | |
2186 | return 0; | |
2187 | } | |
2188 | ||
001c76f0 | 2189 | static struct cpufreq_driver intel_pstate = { |
93f0822d DB |
2190 | .flags = CPUFREQ_CONST_LOOPS, |
2191 | .verify = intel_pstate_verify_policy, | |
2192 | .setpolicy = intel_pstate_set_policy, | |
984edbdc | 2193 | .suspend = intel_pstate_hwp_save_state, |
8442885f | 2194 | .resume = intel_pstate_resume, |
93f0822d DB |
2195 | .get = intel_pstate_get, |
2196 | .init = intel_pstate_cpu_init, | |
9522a2ff | 2197 | .exit = intel_pstate_cpu_exit, |
bb18008f | 2198 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 2199 | .name = "intel_pstate", |
93f0822d DB |
2200 | }; |
2201 | ||
001c76f0 RW |
2202 | static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy) |
2203 | { | |
2204 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
001c76f0 RW |
2205 | |
2206 | update_turbo_state(); | |
80b120ca RW |
2207 | cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, |
2208 | intel_pstate_get_max_freq(cpu)); | |
001c76f0 | 2209 | |
80b120ca | 2210 | intel_pstate_adjust_policy_max(policy, cpu); |
001c76f0 | 2211 | |
c5a2ee7d RW |
2212 | intel_pstate_update_perf_limits(policy, cpu); |
2213 | ||
001c76f0 RW |
2214 | return 0; |
2215 | } | |
2216 | ||
001c76f0 RW |
2217 | static int intel_cpufreq_target(struct cpufreq_policy *policy, |
2218 | unsigned int target_freq, | |
2219 | unsigned int relation) | |
2220 | { | |
2221 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2222 | struct cpufreq_freqs freqs; | |
2223 | int target_pstate; | |
2224 | ||
64897b20 RW |
2225 | update_turbo_state(); |
2226 | ||
001c76f0 | 2227 | freqs.old = policy->cur; |
64897b20 | 2228 | freqs.new = target_freq; |
001c76f0 RW |
2229 | |
2230 | cpufreq_freq_transition_begin(policy, &freqs); | |
2231 | switch (relation) { | |
2232 | case CPUFREQ_RELATION_L: | |
2233 | target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling); | |
2234 | break; | |
2235 | case CPUFREQ_RELATION_H: | |
2236 | target_pstate = freqs.new / cpu->pstate.scaling; | |
2237 | break; | |
2238 | default: | |
2239 | target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling); | |
2240 | break; | |
2241 | } | |
2242 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); | |
2243 | if (target_pstate != cpu->pstate.current_pstate) { | |
2244 | cpu->pstate.current_pstate = target_pstate; | |
2245 | wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL, | |
2246 | pstate_funcs.get_val(cpu, target_pstate)); | |
2247 | } | |
64078299 | 2248 | freqs.new = target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2249 | cpufreq_freq_transition_end(policy, &freqs, false); |
2250 | ||
2251 | return 0; | |
2252 | } | |
2253 | ||
2254 | static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy, | |
2255 | unsigned int target_freq) | |
2256 | { | |
2257 | struct cpudata *cpu = all_cpu_data[policy->cpu]; | |
2258 | int target_pstate; | |
2259 | ||
64897b20 RW |
2260 | update_turbo_state(); |
2261 | ||
001c76f0 | 2262 | target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling); |
64078299 | 2263 | target_pstate = intel_pstate_prepare_request(cpu, target_pstate); |
001c76f0 | 2264 | intel_pstate_update_pstate(cpu, target_pstate); |
64078299 | 2265 | return target_pstate * cpu->pstate.scaling; |
001c76f0 RW |
2266 | } |
2267 | ||
2268 | static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
2269 | { | |
2270 | int ret = __intel_pstate_cpu_init(policy); | |
2271 | ||
2272 | if (ret) | |
2273 | return ret; | |
2274 | ||
2275 | policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY; | |
2276 | /* This reflects the intel_pstate_get_cpu_pstates() setting. */ | |
2277 | policy->cur = policy->cpuinfo.min_freq; | |
2278 | ||
2279 | return 0; | |
2280 | } | |
2281 | ||
2282 | static struct cpufreq_driver intel_cpufreq = { | |
2283 | .flags = CPUFREQ_CONST_LOOPS, | |
2284 | .verify = intel_cpufreq_verify_policy, | |
2285 | .target = intel_cpufreq_target, | |
2286 | .fast_switch = intel_cpufreq_fast_switch, | |
2287 | .init = intel_cpufreq_cpu_init, | |
2288 | .exit = intel_pstate_cpu_exit, | |
2289 | .stop_cpu = intel_cpufreq_stop_cpu, | |
2290 | .name = "intel_cpufreq", | |
2291 | }; | |
2292 | ||
ee8df89a | 2293 | static struct cpufreq_driver *default_driver = &intel_pstate; |
001c76f0 | 2294 | |
fb1fe104 RW |
2295 | static void intel_pstate_driver_cleanup(void) |
2296 | { | |
2297 | unsigned int cpu; | |
2298 | ||
2299 | get_online_cpus(); | |
2300 | for_each_online_cpu(cpu) { | |
2301 | if (all_cpu_data[cpu]) { | |
2302 | if (intel_pstate_driver == &intel_pstate) | |
2303 | intel_pstate_clear_update_util_hook(cpu); | |
2304 | ||
2305 | kfree(all_cpu_data[cpu]); | |
2306 | all_cpu_data[cpu] = NULL; | |
2307 | } | |
2308 | } | |
2309 | put_online_cpus(); | |
ee8df89a | 2310 | intel_pstate_driver = NULL; |
fb1fe104 RW |
2311 | } |
2312 | ||
ee8df89a | 2313 | static int intel_pstate_register_driver(struct cpufreq_driver *driver) |
fb1fe104 RW |
2314 | { |
2315 | int ret; | |
2316 | ||
c5a2ee7d RW |
2317 | memset(&global, 0, sizeof(global)); |
2318 | global.max_perf_pct = 100; | |
c3a49c89 | 2319 | |
ee8df89a | 2320 | intel_pstate_driver = driver; |
fb1fe104 RW |
2321 | ret = cpufreq_register_driver(intel_pstate_driver); |
2322 | if (ret) { | |
2323 | intel_pstate_driver_cleanup(); | |
2324 | return ret; | |
2325 | } | |
2326 | ||
c5a2ee7d RW |
2327 | global.min_perf_pct = min_perf_pct_min(); |
2328 | ||
fb1fe104 | 2329 | if (intel_pstate_driver == &intel_pstate && !hwp_active && |
67dd9bf4 | 2330 | pstate_funcs.update_util == intel_pstate_update_util_pid) |
fb1fe104 RW |
2331 | intel_pstate_debug_expose_params(); |
2332 | ||
2333 | return 0; | |
2334 | } | |
2335 | ||
2336 | static int intel_pstate_unregister_driver(void) | |
2337 | { | |
2338 | if (hwp_active) | |
2339 | return -EBUSY; | |
2340 | ||
67dd9bf4 RW |
2341 | if (intel_pstate_driver == &intel_pstate && |
2342 | pstate_funcs.update_util == intel_pstate_update_util_pid) | |
fb1fe104 RW |
2343 | intel_pstate_debug_hide_params(); |
2344 | ||
fb1fe104 RW |
2345 | cpufreq_unregister_driver(intel_pstate_driver); |
2346 | intel_pstate_driver_cleanup(); | |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
2351 | static ssize_t intel_pstate_show_status(char *buf) | |
2352 | { | |
ee8df89a | 2353 | if (!intel_pstate_driver) |
fb1fe104 RW |
2354 | return sprintf(buf, "off\n"); |
2355 | ||
2356 | return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ? | |
2357 | "active" : "passive"); | |
2358 | } | |
2359 | ||
2360 | static int intel_pstate_update_status(const char *buf, size_t size) | |
2361 | { | |
2362 | int ret; | |
2363 | ||
2364 | if (size == 3 && !strncmp(buf, "off", size)) | |
ee8df89a | 2365 | return intel_pstate_driver ? |
fb1fe104 RW |
2366 | intel_pstate_unregister_driver() : -EINVAL; |
2367 | ||
2368 | if (size == 6 && !strncmp(buf, "active", size)) { | |
ee8df89a | 2369 | if (intel_pstate_driver) { |
fb1fe104 RW |
2370 | if (intel_pstate_driver == &intel_pstate) |
2371 | return 0; | |
2372 | ||
2373 | ret = intel_pstate_unregister_driver(); | |
2374 | if (ret) | |
2375 | return ret; | |
2376 | } | |
2377 | ||
ee8df89a | 2378 | return intel_pstate_register_driver(&intel_pstate); |
fb1fe104 RW |
2379 | } |
2380 | ||
2381 | if (size == 7 && !strncmp(buf, "passive", size)) { | |
ee8df89a | 2382 | if (intel_pstate_driver) { |
0042b2c0 | 2383 | if (intel_pstate_driver == &intel_cpufreq) |
fb1fe104 RW |
2384 | return 0; |
2385 | ||
2386 | ret = intel_pstate_unregister_driver(); | |
2387 | if (ret) | |
2388 | return ret; | |
2389 | } | |
2390 | ||
ee8df89a | 2391 | return intel_pstate_register_driver(&intel_cpufreq); |
fb1fe104 RW |
2392 | } |
2393 | ||
2394 | return -EINVAL; | |
2395 | } | |
2396 | ||
eed43609 JZ |
2397 | static int no_load __initdata; |
2398 | static int no_hwp __initdata; | |
2399 | static int hwp_only __initdata; | |
29327c84 | 2400 | static unsigned int force_load __initdata; |
6be26498 | 2401 | |
29327c84 | 2402 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 2403 | { |
016c8150 | 2404 | if (!pstate_funcs.get_max() || |
c410833a SK |
2405 | !pstate_funcs.get_min() || |
2406 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
2407 | return -ENODEV; |
2408 | ||
b563b4e3 DB |
2409 | return 0; |
2410 | } | |
016c8150 | 2411 | |
7f7a516e SP |
2412 | #ifdef CONFIG_ACPI |
2413 | static void intel_pstate_use_acpi_profile(void) | |
2414 | { | |
55395345 RW |
2415 | switch (acpi_gbl_FADT.preferred_profile) { |
2416 | case PM_MOBILE: | |
2417 | case PM_TABLET: | |
2418 | case PM_APPLIANCE_PC: | |
2419 | case PM_DESKTOP: | |
2420 | case PM_WORKSTATION: | |
67dd9bf4 | 2421 | pstate_funcs.update_util = intel_pstate_update_util; |
55395345 | 2422 | } |
7f7a516e SP |
2423 | } |
2424 | #else | |
2425 | static void intel_pstate_use_acpi_profile(void) | |
2426 | { | |
2427 | } | |
2428 | #endif | |
2429 | ||
29327c84 | 2430 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
2431 | { |
2432 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 2433 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
2434 | pstate_funcs.get_min = funcs->get_min; |
2435 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 2436 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 2437 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 2438 | pstate_funcs.get_vid = funcs->get_vid; |
67dd9bf4 | 2439 | pstate_funcs.update_util = funcs->update_util; |
157386b6 | 2440 | |
7f7a516e | 2441 | intel_pstate_use_acpi_profile(); |
016c8150 DB |
2442 | } |
2443 | ||
9522a2ff | 2444 | #ifdef CONFIG_ACPI |
fbbcdc07 | 2445 | |
29327c84 | 2446 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
2447 | { |
2448 | int i; | |
2449 | ||
2450 | for_each_possible_cpu(i) { | |
2451 | acpi_status status; | |
2452 | union acpi_object *pss; | |
2453 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
2454 | struct acpi_processor *pr = per_cpu(processors, i); | |
2455 | ||
2456 | if (!pr) | |
2457 | continue; | |
2458 | ||
2459 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
2460 | if (ACPI_FAILURE(status)) | |
2461 | continue; | |
2462 | ||
2463 | pss = buffer.pointer; | |
2464 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
2465 | kfree(pss); | |
2466 | return false; | |
2467 | } | |
2468 | ||
2469 | kfree(pss); | |
2470 | } | |
2471 | ||
2472 | return true; | |
2473 | } | |
2474 | ||
29327c84 | 2475 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 2476 | { |
2477 | int i; | |
2478 | ||
2479 | for_each_possible_cpu(i) { | |
2480 | struct acpi_processor *pr = per_cpu(processors, i); | |
2481 | ||
2482 | if (!pr) | |
2483 | continue; | |
2484 | if (acpi_has_method(pr->handle, "_PPC")) | |
2485 | return true; | |
2486 | } | |
2487 | return false; | |
2488 | } | |
2489 | ||
2490 | enum { | |
2491 | PSS, | |
2492 | PPC, | |
2493 | }; | |
2494 | ||
fbbcdc07 AH |
2495 | struct hw_vendor_info { |
2496 | u16 valid; | |
2497 | char oem_id[ACPI_OEM_ID_SIZE]; | |
2498 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 2499 | int oem_pwr_table; |
fbbcdc07 AH |
2500 | }; |
2501 | ||
2502 | /* Hardware vendor-specific info that has its own power management modes */ | |
29327c84 | 2503 | static struct hw_vendor_info vendor_info[] __initdata = { |
966916ea | 2504 | {1, "HP ", "ProLiant", PSS}, |
2505 | {1, "ORACLE", "X4-2 ", PPC}, | |
2506 | {1, "ORACLE", "X4-2L ", PPC}, | |
2507 | {1, "ORACLE", "X4-2B ", PPC}, | |
2508 | {1, "ORACLE", "X3-2 ", PPC}, | |
2509 | {1, "ORACLE", "X3-2L ", PPC}, | |
2510 | {1, "ORACLE", "X3-2B ", PPC}, | |
2511 | {1, "ORACLE", "X4470M2 ", PPC}, | |
2512 | {1, "ORACLE", "X4270M3 ", PPC}, | |
2513 | {1, "ORACLE", "X4270M2 ", PPC}, | |
2514 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
2515 | {1, "ORACLE", "X4170 M3", PPC}, |
2516 | {1, "ORACLE", "X4275 M3", PPC}, | |
2517 | {1, "ORACLE", "X6-2 ", PPC}, | |
2518 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
2519 | {0, "", ""}, |
2520 | }; | |
2521 | ||
29327c84 | 2522 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 AH |
2523 | { |
2524 | struct acpi_table_header hdr; | |
2525 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
2526 | const struct x86_cpu_id *id; |
2527 | u64 misc_pwr; | |
2528 | ||
2529 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
2530 | if (id) { | |
2531 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
2532 | if ( misc_pwr & (1 << 8)) | |
2533 | return true; | |
2534 | } | |
fbbcdc07 | 2535 | |
c410833a SK |
2536 | if (acpi_disabled || |
2537 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
2538 | return false; |
2539 | ||
2540 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 2541 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 2542 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
2543 | ACPI_OEM_TABLE_ID_SIZE)) | |
2544 | switch (v_info->oem_pwr_table) { | |
2545 | case PSS: | |
2546 | return intel_pstate_no_acpi_pss(); | |
2547 | case PPC: | |
aa4ea34d EZ |
2548 | return intel_pstate_has_acpi_ppc() && |
2549 | (!force_load); | |
966916ea | 2550 | } |
fbbcdc07 AH |
2551 | } |
2552 | ||
2553 | return false; | |
2554 | } | |
d0ea59e1 RW |
2555 | |
2556 | static void intel_pstate_request_control_from_smm(void) | |
2557 | { | |
2558 | /* | |
2559 | * It may be unsafe to request P-states control from SMM if _PPC support | |
2560 | * has not been enabled. | |
2561 | */ | |
2562 | if (acpi_ppc) | |
2563 | acpi_processor_pstate_control(); | |
2564 | } | |
fbbcdc07 AH |
2565 | #else /* CONFIG_ACPI not enabled */ |
2566 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 2567 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
d0ea59e1 | 2568 | static inline void intel_pstate_request_control_from_smm(void) {} |
fbbcdc07 AH |
2569 | #endif /* CONFIG_ACPI */ |
2570 | ||
7791e4aa SP |
2571 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
2572 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
2573 | {} | |
2574 | }; | |
2575 | ||
93f0822d DB |
2576 | static int __init intel_pstate_init(void) |
2577 | { | |
eb5139d1 | 2578 | int rc; |
93f0822d | 2579 | |
6be26498 DB |
2580 | if (no_load) |
2581 | return -ENODEV; | |
2582 | ||
eb5139d1 | 2583 | if (x86_match_cpu(hwp_support_ids)) { |
7791e4aa | 2584 | copy_cpu_funcs(&core_params.funcs); |
eb5139d1 | 2585 | if (no_hwp) { |
67dd9bf4 | 2586 | pstate_funcs.update_util = intel_pstate_update_util; |
eb5139d1 RW |
2587 | } else { |
2588 | hwp_active++; | |
2589 | intel_pstate.attr = hwp_cpufreq_attrs; | |
67dd9bf4 | 2590 | pstate_funcs.update_util = intel_pstate_update_util_hwp; |
eb5139d1 RW |
2591 | goto hwp_cpu_matched; |
2592 | } | |
2593 | } else { | |
2594 | const struct x86_cpu_id *id; | |
2595 | struct cpu_defaults *cpu_def; | |
7791e4aa | 2596 | |
eb5139d1 RW |
2597 | id = x86_match_cpu(intel_pstate_cpu_ids); |
2598 | if (!id) | |
2599 | return -ENODEV; | |
93f0822d | 2600 | |
eb5139d1 | 2601 | cpu_def = (struct cpu_defaults *)id->driver_data; |
eb5139d1 RW |
2602 | copy_cpu_funcs(&cpu_def->funcs); |
2603 | } | |
016c8150 | 2604 | |
b563b4e3 DB |
2605 | if (intel_pstate_msrs_not_valid()) |
2606 | return -ENODEV; | |
2607 | ||
7791e4aa SP |
2608 | hwp_cpu_matched: |
2609 | /* | |
2610 | * The Intel pstate driver will be ignored if the platform | |
2611 | * firmware has its own power management modes. | |
2612 | */ | |
2613 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
2614 | return -ENODEV; | |
2615 | ||
fb1fe104 RW |
2616 | if (!hwp_active && hwp_only) |
2617 | return -ENOTSUPP; | |
2618 | ||
4836df17 | 2619 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 2620 | |
b57ffac5 | 2621 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
2622 | if (!all_cpu_data) |
2623 | return -ENOMEM; | |
93f0822d | 2624 | |
d0ea59e1 RW |
2625 | intel_pstate_request_control_from_smm(); |
2626 | ||
93f0822d | 2627 | intel_pstate_sysfs_expose_params(); |
b69880f9 | 2628 | |
0c30b65b | 2629 | mutex_lock(&intel_pstate_driver_lock); |
ee8df89a | 2630 | rc = intel_pstate_register_driver(default_driver); |
0c30b65b | 2631 | mutex_unlock(&intel_pstate_driver_lock); |
fb1fe104 RW |
2632 | if (rc) |
2633 | return rc; | |
366430b5 | 2634 | |
7791e4aa | 2635 | if (hwp_active) |
4836df17 | 2636 | pr_info("HWP enabled\n"); |
7791e4aa | 2637 | |
fb1fe104 | 2638 | return 0; |
93f0822d DB |
2639 | } |
2640 | device_initcall(intel_pstate_init); | |
2641 | ||
6be26498 DB |
2642 | static int __init intel_pstate_setup(char *str) |
2643 | { | |
2644 | if (!str) | |
2645 | return -EINVAL; | |
2646 | ||
001c76f0 | 2647 | if (!strcmp(str, "disable")) { |
6be26498 | 2648 | no_load = 1; |
001c76f0 RW |
2649 | } else if (!strcmp(str, "passive")) { |
2650 | pr_info("Passive mode enabled\n"); | |
ee8df89a | 2651 | default_driver = &intel_cpufreq; |
001c76f0 RW |
2652 | no_hwp = 1; |
2653 | } | |
539342f6 | 2654 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 2655 | pr_info("HWP disabled\n"); |
2f86dc4c | 2656 | no_hwp = 1; |
539342f6 | 2657 | } |
aa4ea34d EZ |
2658 | if (!strcmp(str, "force")) |
2659 | force_load = 1; | |
d64c3b0b KCA |
2660 | if (!strcmp(str, "hwp_only")) |
2661 | hwp_only = 1; | |
eae48f04 SP |
2662 | if (!strcmp(str, "per_cpu_perf_limits")) |
2663 | per_cpu_limits = true; | |
9522a2ff SP |
2664 | |
2665 | #ifdef CONFIG_ACPI | |
2666 | if (!strcmp(str, "support_acpi_ppc")) | |
2667 | acpi_ppc = true; | |
2668 | #endif | |
2669 | ||
6be26498 DB |
2670 | return 0; |
2671 | } | |
2672 | early_param("intel_pstate", intel_pstate_setup); | |
2673 | ||
93f0822d DB |
2674 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
2675 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
2676 | MODULE_LICENSE("GPL"); |