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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
d6472302 | 29 | #include <linux/vmalloc.h> |
93f0822d DB |
30 | #include <trace/events/power.h> |
31 | ||
32 | #include <asm/div64.h> | |
33 | #include <asm/msr.h> | |
34 | #include <asm/cpu_device_id.h> | |
64df1fdf | 35 | #include <asm/cpufeature.h> |
93f0822d | 36 | |
61d8d2ab DB |
37 | #define BYT_RATIOS 0x66a |
38 | #define BYT_VIDS 0x66b | |
39 | #define BYT_TURBO_RATIOS 0x66c | |
21855ff5 | 40 | #define BYT_TURBO_VIDS 0x66d |
61d8d2ab | 41 | |
f0fe3cd7 | 42 | #define FRAC_BITS 8 |
93f0822d DB |
43 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
44 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 45 | |
93f0822d DB |
46 | static inline int32_t mul_fp(int32_t x, int32_t y) |
47 | { | |
48 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
49 | } | |
50 | ||
7180dddf | 51 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 52 | { |
7180dddf | 53 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
54 | } |
55 | ||
d022a65e DB |
56 | static inline int ceiling_fp(int32_t x) |
57 | { | |
58 | int mask, ret; | |
59 | ||
60 | ret = fp_toint(x); | |
61 | mask = (1 << FRAC_BITS) - 1; | |
62 | if (x & mask) | |
63 | ret += 1; | |
64 | return ret; | |
65 | } | |
66 | ||
93f0822d | 67 | struct sample { |
d253d2a5 | 68 | int32_t core_pct_busy; |
93f0822d DB |
69 | u64 aperf; |
70 | u64 mperf; | |
4055fad3 | 71 | u64 tsc; |
93f0822d | 72 | int freq; |
c4ee841f | 73 | ktime_t time; |
93f0822d DB |
74 | }; |
75 | ||
76 | struct pstate_data { | |
77 | int current_pstate; | |
78 | int min_pstate; | |
79 | int max_pstate; | |
b27580b0 | 80 | int scaling; |
93f0822d DB |
81 | int turbo_pstate; |
82 | }; | |
83 | ||
007bea09 | 84 | struct vid_data { |
21855ff5 DB |
85 | int min; |
86 | int max; | |
87 | int turbo; | |
007bea09 DB |
88 | int32_t ratio; |
89 | }; | |
90 | ||
93f0822d DB |
91 | struct _pid { |
92 | int setpoint; | |
93 | int32_t integral; | |
94 | int32_t p_gain; | |
95 | int32_t i_gain; | |
96 | int32_t d_gain; | |
97 | int deadband; | |
d253d2a5 | 98 | int32_t last_err; |
93f0822d DB |
99 | }; |
100 | ||
101 | struct cpudata { | |
102 | int cpu; | |
103 | ||
93f0822d DB |
104 | struct timer_list timer; |
105 | ||
93f0822d | 106 | struct pstate_data pstate; |
007bea09 | 107 | struct vid_data vid; |
93f0822d | 108 | struct _pid pid; |
93f0822d | 109 | |
c4ee841f | 110 | ktime_t last_sample_time; |
93f0822d DB |
111 | u64 prev_aperf; |
112 | u64 prev_mperf; | |
4055fad3 | 113 | u64 prev_tsc; |
d37e2b76 | 114 | struct sample sample; |
93f0822d DB |
115 | }; |
116 | ||
117 | static struct cpudata **all_cpu_data; | |
118 | struct pstate_adjust_policy { | |
119 | int sample_rate_ms; | |
120 | int deadband; | |
121 | int setpoint; | |
122 | int p_gain_pct; | |
123 | int d_gain_pct; | |
124 | int i_gain_pct; | |
125 | }; | |
126 | ||
016c8150 DB |
127 | struct pstate_funcs { |
128 | int (*get_max)(void); | |
129 | int (*get_min)(void); | |
130 | int (*get_turbo)(void); | |
b27580b0 | 131 | int (*get_scaling)(void); |
007bea09 DB |
132 | void (*set)(struct cpudata*, int pstate); |
133 | void (*get_vid)(struct cpudata *); | |
93f0822d DB |
134 | }; |
135 | ||
016c8150 DB |
136 | struct cpu_defaults { |
137 | struct pstate_adjust_policy pid_policy; | |
138 | struct pstate_funcs funcs; | |
93f0822d DB |
139 | }; |
140 | ||
016c8150 DB |
141 | static struct pstate_adjust_policy pid_params; |
142 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 143 | static int hwp_active; |
016c8150 | 144 | |
93f0822d DB |
145 | struct perf_limits { |
146 | int no_turbo; | |
dd5fbf70 | 147 | int turbo_disabled; |
93f0822d DB |
148 | int max_perf_pct; |
149 | int min_perf_pct; | |
150 | int32_t max_perf; | |
151 | int32_t min_perf; | |
d8f469e9 DB |
152 | int max_policy_pct; |
153 | int max_sysfs_pct; | |
a0475992 KCA |
154 | int min_policy_pct; |
155 | int min_sysfs_pct; | |
93f0822d DB |
156 | }; |
157 | ||
158 | static struct perf_limits limits = { | |
159 | .no_turbo = 0, | |
4521e1a0 | 160 | .turbo_disabled = 0, |
93f0822d DB |
161 | .max_perf_pct = 100, |
162 | .max_perf = int_tofp(1), | |
163 | .min_perf_pct = 0, | |
164 | .min_perf = 0, | |
d8f469e9 DB |
165 | .max_policy_pct = 100, |
166 | .max_sysfs_pct = 100, | |
a0475992 KCA |
167 | .min_policy_pct = 0, |
168 | .min_sysfs_pct = 0, | |
93f0822d DB |
169 | }; |
170 | ||
171 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
c410833a | 172 | int deadband, int integral) { |
93f0822d DB |
173 | pid->setpoint = setpoint; |
174 | pid->deadband = deadband; | |
175 | pid->integral = int_tofp(integral); | |
d98d099b | 176 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
177 | } |
178 | ||
179 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
180 | { | |
181 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
182 | } | |
183 | ||
184 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
185 | { | |
186 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
187 | } | |
188 | ||
189 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
190 | { | |
93f0822d DB |
191 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
192 | } | |
193 | ||
d253d2a5 | 194 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 195 | { |
d253d2a5 | 196 | signed int result; |
93f0822d DB |
197 | int32_t pterm, dterm, fp_error; |
198 | int32_t integral_limit; | |
199 | ||
d253d2a5 | 200 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 201 | |
d253d2a5 | 202 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
203 | return 0; |
204 | ||
205 | pterm = mul_fp(pid->p_gain, fp_error); | |
206 | ||
207 | pid->integral += fp_error; | |
208 | ||
e0d4c8f8 KCA |
209 | /* |
210 | * We limit the integral here so that it will never | |
211 | * get higher than 30. This prevents it from becoming | |
212 | * too large an input over long periods of time and allows | |
213 | * it to get factored out sooner. | |
214 | * | |
215 | * The value of 30 was chosen through experimentation. | |
216 | */ | |
93f0822d DB |
217 | integral_limit = int_tofp(30); |
218 | if (pid->integral > integral_limit) | |
219 | pid->integral = integral_limit; | |
220 | if (pid->integral < -integral_limit) | |
221 | pid->integral = -integral_limit; | |
222 | ||
d253d2a5 BS |
223 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
224 | pid->last_err = fp_error; | |
93f0822d DB |
225 | |
226 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 227 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
228 | return (signed int)fp_toint(result); |
229 | } | |
230 | ||
231 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
232 | { | |
016c8150 DB |
233 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
234 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
235 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 236 | |
2d8d1f18 | 237 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
238 | } |
239 | ||
93f0822d DB |
240 | static inline void intel_pstate_reset_all_pid(void) |
241 | { | |
242 | unsigned int cpu; | |
845c1cbe | 243 | |
93f0822d DB |
244 | for_each_online_cpu(cpu) { |
245 | if (all_cpu_data[cpu]) | |
246 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
247 | } | |
248 | } | |
249 | ||
4521e1a0 GM |
250 | static inline void update_turbo_state(void) |
251 | { | |
252 | u64 misc_en; | |
253 | struct cpudata *cpu; | |
254 | ||
255 | cpu = all_cpu_data[0]; | |
256 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
257 | limits.turbo_disabled = | |
258 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || | |
259 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
260 | } | |
261 | ||
2f86dc4c DB |
262 | static void intel_pstate_hwp_set(void) |
263 | { | |
74da56ce KCA |
264 | int min, hw_min, max, hw_max, cpu, range, adj_range; |
265 | u64 value, cap; | |
266 | ||
267 | rdmsrl(MSR_HWP_CAPABILITIES, cap); | |
268 | hw_min = HWP_LOWEST_PERF(cap); | |
269 | hw_max = HWP_HIGHEST_PERF(cap); | |
270 | range = hw_max - hw_min; | |
2f86dc4c DB |
271 | |
272 | get_online_cpus(); | |
273 | ||
274 | for_each_online_cpu(cpu) { | |
275 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
74da56ce KCA |
276 | adj_range = limits.min_perf_pct * range / 100; |
277 | min = hw_min + adj_range; | |
2f86dc4c DB |
278 | value &= ~HWP_MIN_PERF(~0L); |
279 | value |= HWP_MIN_PERF(min); | |
280 | ||
74da56ce KCA |
281 | adj_range = limits.max_perf_pct * range / 100; |
282 | max = hw_min + adj_range; | |
2f86dc4c | 283 | if (limits.no_turbo) { |
74da56ce KCA |
284 | hw_max = HWP_GUARANTEED_PERF(cap); |
285 | if (hw_max < max) | |
286 | max = hw_max; | |
2f86dc4c DB |
287 | } |
288 | ||
289 | value &= ~HWP_MAX_PERF(~0L); | |
290 | value |= HWP_MAX_PERF(max); | |
291 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
292 | } | |
293 | ||
294 | put_online_cpus(); | |
295 | } | |
296 | ||
93f0822d DB |
297 | /************************** debugfs begin ************************/ |
298 | static int pid_param_set(void *data, u64 val) | |
299 | { | |
300 | *(u32 *)data = val; | |
301 | intel_pstate_reset_all_pid(); | |
302 | return 0; | |
303 | } | |
845c1cbe | 304 | |
93f0822d DB |
305 | static int pid_param_get(void *data, u64 *val) |
306 | { | |
307 | *val = *(u32 *)data; | |
308 | return 0; | |
309 | } | |
2d8d1f18 | 310 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
311 | |
312 | struct pid_param { | |
313 | char *name; | |
314 | void *value; | |
315 | }; | |
316 | ||
317 | static struct pid_param pid_files[] = { | |
016c8150 DB |
318 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
319 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
320 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
321 | {"deadband", &pid_params.deadband}, | |
322 | {"setpoint", &pid_params.setpoint}, | |
323 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
324 | {NULL, NULL} |
325 | }; | |
326 | ||
317dd50e | 327 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 328 | { |
317dd50e | 329 | struct dentry *debugfs_parent; |
93f0822d DB |
330 | int i = 0; |
331 | ||
2f86dc4c DB |
332 | if (hwp_active) |
333 | return; | |
93f0822d DB |
334 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
335 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
336 | return; | |
337 | while (pid_files[i].name) { | |
338 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
339 | debugfs_parent, pid_files[i].value, |
340 | &fops_pid_param); | |
93f0822d DB |
341 | i++; |
342 | } | |
343 | } | |
344 | ||
345 | /************************** debugfs end ************************/ | |
346 | ||
347 | /************************** sysfs begin ************************/ | |
348 | #define show_one(file_name, object) \ | |
349 | static ssize_t show_##file_name \ | |
350 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
351 | { \ | |
352 | return sprintf(buf, "%u\n", limits.object); \ | |
353 | } | |
354 | ||
d01b1f48 KCA |
355 | static ssize_t show_turbo_pct(struct kobject *kobj, |
356 | struct attribute *attr, char *buf) | |
357 | { | |
358 | struct cpudata *cpu; | |
359 | int total, no_turbo, turbo_pct; | |
360 | uint32_t turbo_fp; | |
361 | ||
362 | cpu = all_cpu_data[0]; | |
363 | ||
364 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
365 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
366 | turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); | |
367 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); | |
368 | return sprintf(buf, "%u\n", turbo_pct); | |
369 | } | |
370 | ||
0522424e KCA |
371 | static ssize_t show_num_pstates(struct kobject *kobj, |
372 | struct attribute *attr, char *buf) | |
373 | { | |
374 | struct cpudata *cpu; | |
375 | int total; | |
376 | ||
377 | cpu = all_cpu_data[0]; | |
378 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
379 | return sprintf(buf, "%u\n", total); | |
380 | } | |
381 | ||
4521e1a0 GM |
382 | static ssize_t show_no_turbo(struct kobject *kobj, |
383 | struct attribute *attr, char *buf) | |
384 | { | |
385 | ssize_t ret; | |
386 | ||
387 | update_turbo_state(); | |
388 | if (limits.turbo_disabled) | |
389 | ret = sprintf(buf, "%u\n", limits.turbo_disabled); | |
390 | else | |
391 | ret = sprintf(buf, "%u\n", limits.no_turbo); | |
392 | ||
393 | return ret; | |
394 | } | |
395 | ||
93f0822d | 396 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 397 | const char *buf, size_t count) |
93f0822d DB |
398 | { |
399 | unsigned int input; | |
400 | int ret; | |
845c1cbe | 401 | |
93f0822d DB |
402 | ret = sscanf(buf, "%u", &input); |
403 | if (ret != 1) | |
404 | return -EINVAL; | |
4521e1a0 GM |
405 | |
406 | update_turbo_state(); | |
dd5fbf70 | 407 | if (limits.turbo_disabled) { |
f16255eb | 408 | pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n"); |
4521e1a0 | 409 | return -EPERM; |
dd5fbf70 | 410 | } |
2f86dc4c | 411 | |
4521e1a0 GM |
412 | limits.no_turbo = clamp_t(int, input, 0, 1); |
413 | ||
2f86dc4c DB |
414 | if (hwp_active) |
415 | intel_pstate_hwp_set(); | |
416 | ||
93f0822d DB |
417 | return count; |
418 | } | |
419 | ||
420 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 421 | const char *buf, size_t count) |
93f0822d DB |
422 | { |
423 | unsigned int input; | |
424 | int ret; | |
845c1cbe | 425 | |
93f0822d DB |
426 | ret = sscanf(buf, "%u", &input); |
427 | if (ret != 1) | |
428 | return -EINVAL; | |
429 | ||
d8f469e9 DB |
430 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
431 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
43717aad CY |
432 | limits.max_perf_pct = max(limits.min_policy_pct, limits.max_perf_pct); |
433 | limits.max_perf_pct = max(limits.min_perf_pct, limits.max_perf_pct); | |
93f0822d | 434 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
845c1cbe | 435 | |
2f86dc4c DB |
436 | if (hwp_active) |
437 | intel_pstate_hwp_set(); | |
93f0822d DB |
438 | return count; |
439 | } | |
440 | ||
441 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 442 | const char *buf, size_t count) |
93f0822d DB |
443 | { |
444 | unsigned int input; | |
445 | int ret; | |
845c1cbe | 446 | |
93f0822d DB |
447 | ret = sscanf(buf, "%u", &input); |
448 | if (ret != 1) | |
449 | return -EINVAL; | |
a0475992 KCA |
450 | |
451 | limits.min_sysfs_pct = clamp_t(int, input, 0 , 100); | |
452 | limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); | |
43717aad CY |
453 | limits.min_perf_pct = min(limits.max_policy_pct, limits.min_perf_pct); |
454 | limits.min_perf_pct = min(limits.max_perf_pct, limits.min_perf_pct); | |
93f0822d DB |
455 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); |
456 | ||
2f86dc4c DB |
457 | if (hwp_active) |
458 | intel_pstate_hwp_set(); | |
93f0822d DB |
459 | return count; |
460 | } | |
461 | ||
93f0822d DB |
462 | show_one(max_perf_pct, max_perf_pct); |
463 | show_one(min_perf_pct, min_perf_pct); | |
464 | ||
465 | define_one_global_rw(no_turbo); | |
466 | define_one_global_rw(max_perf_pct); | |
467 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 468 | define_one_global_ro(turbo_pct); |
0522424e | 469 | define_one_global_ro(num_pstates); |
93f0822d DB |
470 | |
471 | static struct attribute *intel_pstate_attributes[] = { | |
472 | &no_turbo.attr, | |
473 | &max_perf_pct.attr, | |
474 | &min_perf_pct.attr, | |
d01b1f48 | 475 | &turbo_pct.attr, |
0522424e | 476 | &num_pstates.attr, |
93f0822d DB |
477 | NULL |
478 | }; | |
479 | ||
480 | static struct attribute_group intel_pstate_attr_group = { | |
481 | .attrs = intel_pstate_attributes, | |
482 | }; | |
93f0822d | 483 | |
317dd50e | 484 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 485 | { |
317dd50e | 486 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
487 | int rc; |
488 | ||
489 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
490 | &cpu_subsys.dev_root->kobj); | |
491 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 492 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
493 | BUG_ON(rc); |
494 | } | |
93f0822d | 495 | /************************** sysfs end ************************/ |
2f86dc4c | 496 | |
ba88d433 | 497 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 498 | { |
f16255eb | 499 | pr_info("intel_pstate: HWP enabled\n"); |
2f86dc4c | 500 | |
ba88d433 | 501 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
502 | } |
503 | ||
19e77c28 DB |
504 | static int byt_get_min_pstate(void) |
505 | { | |
506 | u64 value; | |
845c1cbe | 507 | |
19e77c28 | 508 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 509 | return (value >> 8) & 0x7F; |
19e77c28 DB |
510 | } |
511 | ||
512 | static int byt_get_max_pstate(void) | |
513 | { | |
514 | u64 value; | |
845c1cbe | 515 | |
19e77c28 | 516 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 517 | return (value >> 16) & 0x7F; |
19e77c28 | 518 | } |
93f0822d | 519 | |
61d8d2ab DB |
520 | static int byt_get_turbo_pstate(void) |
521 | { | |
522 | u64 value; | |
845c1cbe | 523 | |
61d8d2ab | 524 | rdmsrl(BYT_TURBO_RATIOS, value); |
c16ed060 | 525 | return value & 0x7F; |
61d8d2ab DB |
526 | } |
527 | ||
007bea09 DB |
528 | static void byt_set_pstate(struct cpudata *cpudata, int pstate) |
529 | { | |
530 | u64 val; | |
531 | int32_t vid_fp; | |
532 | u32 vid; | |
533 | ||
144c8e17 | 534 | val = (u64)pstate << 8; |
dd5fbf70 | 535 | if (limits.no_turbo && !limits.turbo_disabled) |
007bea09 DB |
536 | val |= (u64)1 << 32; |
537 | ||
538 | vid_fp = cpudata->vid.min + mul_fp( | |
539 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
540 | cpudata->vid.ratio); | |
541 | ||
542 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 543 | vid = ceiling_fp(vid_fp); |
007bea09 | 544 | |
21855ff5 DB |
545 | if (pstate > cpudata->pstate.max_pstate) |
546 | vid = cpudata->vid.turbo; | |
547 | ||
007bea09 DB |
548 | val |= vid; |
549 | ||
0dd23f94 | 550 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
007bea09 DB |
551 | } |
552 | ||
b27580b0 DB |
553 | #define BYT_BCLK_FREQS 5 |
554 | static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; | |
555 | ||
556 | static int byt_get_scaling(void) | |
557 | { | |
558 | u64 value; | |
559 | int i; | |
560 | ||
561 | rdmsrl(MSR_FSB_FREQ, value); | |
562 | i = value & 0x3; | |
563 | ||
564 | BUG_ON(i > BYT_BCLK_FREQS); | |
565 | ||
566 | return byt_freq_table[i] * 100; | |
567 | } | |
568 | ||
007bea09 DB |
569 | static void byt_get_vid(struct cpudata *cpudata) |
570 | { | |
571 | u64 value; | |
572 | ||
573 | rdmsrl(BYT_VIDS, value); | |
c16ed060 DB |
574 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
575 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
576 | cpudata->vid.ratio = div_fp( |
577 | cpudata->vid.max - cpudata->vid.min, | |
578 | int_tofp(cpudata->pstate.max_pstate - | |
579 | cpudata->pstate.min_pstate)); | |
21855ff5 DB |
580 | |
581 | rdmsrl(BYT_TURBO_VIDS, value); | |
582 | cpudata->vid.turbo = value & 0x7f; | |
007bea09 DB |
583 | } |
584 | ||
016c8150 | 585 | static int core_get_min_pstate(void) |
93f0822d DB |
586 | { |
587 | u64 value; | |
845c1cbe | 588 | |
05e99c8c | 589 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
590 | return (value >> 40) & 0xFF; |
591 | } | |
592 | ||
016c8150 | 593 | static int core_get_max_pstate(void) |
93f0822d | 594 | { |
6a35fc2d SP |
595 | u64 tar; |
596 | u64 plat_info; | |
597 | int max_pstate; | |
598 | int err; | |
599 | ||
600 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
601 | max_pstate = (plat_info >> 8) & 0xFF; | |
602 | ||
603 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); | |
604 | if (!err) { | |
605 | /* Do some sanity checking for safety */ | |
606 | if (plat_info & 0x600000000) { | |
607 | u64 tdp_ctrl; | |
608 | u64 tdp_ratio; | |
609 | int tdp_msr; | |
610 | ||
611 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
612 | if (err) | |
613 | goto skip_tar; | |
614 | ||
615 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; | |
616 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
617 | if (err) | |
618 | goto skip_tar; | |
619 | ||
620 | if (tdp_ratio - 1 == tar) { | |
621 | max_pstate = tar; | |
622 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
623 | } else { | |
624 | goto skip_tar; | |
625 | } | |
626 | } | |
627 | } | |
845c1cbe | 628 | |
6a35fc2d SP |
629 | skip_tar: |
630 | return max_pstate; | |
93f0822d DB |
631 | } |
632 | ||
016c8150 | 633 | static int core_get_turbo_pstate(void) |
93f0822d DB |
634 | { |
635 | u64 value; | |
636 | int nont, ret; | |
845c1cbe | 637 | |
05e99c8c | 638 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 639 | nont = core_get_max_pstate(); |
285cb990 | 640 | ret = (value) & 255; |
93f0822d DB |
641 | if (ret <= nont) |
642 | ret = nont; | |
643 | return ret; | |
644 | } | |
645 | ||
b27580b0 DB |
646 | static inline int core_get_scaling(void) |
647 | { | |
648 | return 100000; | |
649 | } | |
650 | ||
007bea09 | 651 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
652 | { |
653 | u64 val; | |
654 | ||
144c8e17 | 655 | val = (u64)pstate << 8; |
dd5fbf70 | 656 | if (limits.no_turbo && !limits.turbo_disabled) |
016c8150 DB |
657 | val |= (u64)1 << 32; |
658 | ||
bb18008f | 659 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
660 | } |
661 | ||
b34ef932 DC |
662 | static int knl_get_turbo_pstate(void) |
663 | { | |
664 | u64 value; | |
665 | int nont, ret; | |
666 | ||
667 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); | |
668 | nont = core_get_max_pstate(); | |
669 | ret = (((value) >> 8) & 0xFF); | |
670 | if (ret <= nont) | |
671 | ret = nont; | |
672 | return ret; | |
673 | } | |
674 | ||
016c8150 DB |
675 | static struct cpu_defaults core_params = { |
676 | .pid_policy = { | |
677 | .sample_rate_ms = 10, | |
678 | .deadband = 0, | |
679 | .setpoint = 97, | |
680 | .p_gain_pct = 20, | |
681 | .d_gain_pct = 0, | |
682 | .i_gain_pct = 0, | |
683 | }, | |
684 | .funcs = { | |
685 | .get_max = core_get_max_pstate, | |
686 | .get_min = core_get_min_pstate, | |
687 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 688 | .get_scaling = core_get_scaling, |
016c8150 DB |
689 | .set = core_set_pstate, |
690 | }, | |
691 | }; | |
692 | ||
19e77c28 DB |
693 | static struct cpu_defaults byt_params = { |
694 | .pid_policy = { | |
695 | .sample_rate_ms = 10, | |
696 | .deadband = 0, | |
6a82ba6d | 697 | .setpoint = 60, |
19e77c28 DB |
698 | .p_gain_pct = 14, |
699 | .d_gain_pct = 0, | |
700 | .i_gain_pct = 4, | |
701 | }, | |
702 | .funcs = { | |
703 | .get_max = byt_get_max_pstate, | |
704 | .get_min = byt_get_min_pstate, | |
61d8d2ab | 705 | .get_turbo = byt_get_turbo_pstate, |
007bea09 | 706 | .set = byt_set_pstate, |
b27580b0 | 707 | .get_scaling = byt_get_scaling, |
007bea09 | 708 | .get_vid = byt_get_vid, |
19e77c28 DB |
709 | }, |
710 | }; | |
711 | ||
b34ef932 DC |
712 | static struct cpu_defaults knl_params = { |
713 | .pid_policy = { | |
714 | .sample_rate_ms = 10, | |
715 | .deadband = 0, | |
716 | .setpoint = 97, | |
717 | .p_gain_pct = 20, | |
718 | .d_gain_pct = 0, | |
719 | .i_gain_pct = 0, | |
720 | }, | |
721 | .funcs = { | |
722 | .get_max = core_get_max_pstate, | |
723 | .get_min = core_get_min_pstate, | |
724 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 725 | .get_scaling = core_get_scaling, |
b34ef932 DC |
726 | .set = core_set_pstate, |
727 | }, | |
728 | }; | |
729 | ||
93f0822d DB |
730 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
731 | { | |
732 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 733 | int max_perf_adj; |
93f0822d | 734 | int min_perf; |
845c1cbe | 735 | |
4521e1a0 | 736 | if (limits.no_turbo || limits.turbo_disabled) |
93f0822d DB |
737 | max_perf = cpu->pstate.max_pstate; |
738 | ||
e0d4c8f8 KCA |
739 | /* |
740 | * performance can be limited by user through sysfs, by cpufreq | |
741 | * policy, or by cpu specific default values determined through | |
742 | * experimentation. | |
743 | */ | |
7244cb62 DB |
744 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
745 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
746 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
747 | ||
748 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
2d8d1f18 | 749 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
750 | } |
751 | ||
6c1e4591 | 752 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate, bool force) |
93f0822d DB |
753 | { |
754 | int max_perf, min_perf; | |
755 | ||
6c1e4591 DS |
756 | if (force) { |
757 | update_turbo_state(); | |
93f0822d | 758 | |
6c1e4591 | 759 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
93f0822d | 760 | |
6c1e4591 | 761 | pstate = clamp_t(int, pstate, min_perf, max_perf); |
93f0822d | 762 | |
6c1e4591 DS |
763 | if (pstate == cpu->pstate.current_pstate) |
764 | return; | |
765 | } | |
b27580b0 | 766 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 767 | |
93f0822d | 768 | cpu->pstate.current_pstate = pstate; |
93f0822d | 769 | |
007bea09 | 770 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
771 | } |
772 | ||
93f0822d DB |
773 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
774 | { | |
016c8150 DB |
775 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
776 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
777 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
b27580b0 | 778 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 779 | |
007bea09 DB |
780 | if (pstate_funcs.get_vid) |
781 | pstate_funcs.get_vid(cpu); | |
6c1e4591 | 782 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
783 | } |
784 | ||
6b17ddb2 | 785 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 786 | { |
6b17ddb2 | 787 | struct sample *sample = &cpu->sample; |
bf810222 | 788 | int64_t core_pct; |
93f0822d | 789 | |
bf810222 | 790 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 791 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 792 | |
fcb6a15c | 793 | sample->freq = fp_toint( |
b27580b0 DB |
794 | mul_fp(int_tofp( |
795 | cpu->pstate.max_pstate * cpu->pstate.scaling / 100), | |
796 | core_pct)); | |
fcb6a15c | 797 | |
bf810222 | 798 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
799 | } |
800 | ||
801 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
802 | { | |
93f0822d | 803 | u64 aperf, mperf; |
4ab60c3f | 804 | unsigned long flags; |
4055fad3 | 805 | u64 tsc; |
93f0822d | 806 | |
4ab60c3f | 807 | local_irq_save(flags); |
93f0822d DB |
808 | rdmsrl(MSR_IA32_APERF, aperf); |
809 | rdmsrl(MSR_IA32_MPERF, mperf); | |
4ea1636b | 810 | tsc = rdtsc(); |
4ab60c3f | 811 | local_irq_restore(flags); |
b69880f9 | 812 | |
c4ee841f DB |
813 | cpu->last_sample_time = cpu->sample.time; |
814 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
815 | cpu->sample.aperf = aperf; |
816 | cpu->sample.mperf = mperf; | |
4055fad3 | 817 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
818 | cpu->sample.aperf -= cpu->prev_aperf; |
819 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 820 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 821 | |
6b17ddb2 | 822 | intel_pstate_calc_busy(cpu); |
93f0822d | 823 | |
93f0822d DB |
824 | cpu->prev_aperf = aperf; |
825 | cpu->prev_mperf = mperf; | |
4055fad3 | 826 | cpu->prev_tsc = tsc; |
93f0822d DB |
827 | } |
828 | ||
2f86dc4c DB |
829 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
830 | { | |
831 | int delay; | |
832 | ||
833 | delay = msecs_to_jiffies(50); | |
834 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
835 | } | |
836 | ||
93f0822d DB |
837 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
838 | { | |
abf013bf | 839 | int delay; |
93f0822d | 840 | |
abf013bf | 841 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
842 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
843 | } | |
844 | ||
d253d2a5 | 845 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 846 | { |
c4ee841f | 847 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
7180dddf | 848 | s64 duration_us; |
c4ee841f | 849 | u32 sample_time; |
93f0822d | 850 | |
e0d4c8f8 KCA |
851 | /* |
852 | * core_busy is the ratio of actual performance to max | |
853 | * max_pstate is the max non turbo pstate available | |
854 | * current_pstate was the pstate that was requested during | |
855 | * the last sample period. | |
856 | * | |
857 | * We normalize core_busy, which was our actual percent | |
858 | * performance to what we requested during the last sample | |
859 | * period. The result will be a percentage of busy at a | |
860 | * specified pstate. | |
861 | */ | |
d37e2b76 | 862 | core_busy = cpu->sample.core_pct_busy; |
2134ed4d | 863 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 864 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 865 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 866 | |
e0d4c8f8 KCA |
867 | /* |
868 | * Since we have a deferred timer, it will not fire unless | |
869 | * we are in C0. So, determine if the actual elapsed time | |
870 | * is significantly greater (3x) than our sample interval. If it | |
871 | * is, then we were idle for a long enough period of time | |
872 | * to adjust our busyness. | |
873 | */ | |
285cb990 | 874 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
7180dddf PB |
875 | duration_us = ktime_us_delta(cpu->sample.time, |
876 | cpu->last_sample_time); | |
c4ee841f DB |
877 | if (duration_us > sample_time * 3) { |
878 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 879 | int_tofp(duration_us)); |
c4ee841f DB |
880 | core_busy = mul_fp(core_busy, sample_ratio); |
881 | } | |
882 | ||
f0fe3cd7 | 883 | return core_busy; |
93f0822d DB |
884 | } |
885 | ||
886 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
887 | { | |
d253d2a5 | 888 | int32_t busy_scaled; |
93f0822d | 889 | struct _pid *pid; |
4b707c89 | 890 | signed int ctl; |
4055fad3 DS |
891 | int from; |
892 | struct sample *sample; | |
893 | ||
894 | from = cpu->pstate.current_pstate; | |
93f0822d DB |
895 | |
896 | pid = &cpu->pid; | |
897 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
898 | ||
899 | ctl = pid_calc(pid, busy_scaled); | |
900 | ||
4b707c89 | 901 | /* Negative values of ctl increase the pstate and vice versa */ |
6c1e4591 | 902 | intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl, true); |
4055fad3 DS |
903 | |
904 | sample = &cpu->sample; | |
905 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
906 | fp_toint(busy_scaled), | |
907 | from, | |
908 | cpu->pstate.current_pstate, | |
909 | sample->mperf, | |
910 | sample->aperf, | |
911 | sample->tsc, | |
912 | sample->freq); | |
93f0822d DB |
913 | } |
914 | ||
2f86dc4c DB |
915 | static void intel_hwp_timer_func(unsigned long __data) |
916 | { | |
917 | struct cpudata *cpu = (struct cpudata *) __data; | |
918 | ||
919 | intel_pstate_sample(cpu); | |
920 | intel_hwp_set_sample_time(cpu); | |
921 | } | |
922 | ||
93f0822d DB |
923 | static void intel_pstate_timer_func(unsigned long __data) |
924 | { | |
925 | struct cpudata *cpu = (struct cpudata *) __data; | |
926 | ||
927 | intel_pstate_sample(cpu); | |
b69880f9 | 928 | |
ca182aee | 929 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 | 930 | |
93f0822d DB |
931 | intel_pstate_set_sample_time(cpu); |
932 | } | |
933 | ||
934 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
935 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
936 | (unsigned long)&policy } | |
93f0822d DB |
937 | |
938 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
939 | ICPU(0x2a, core_params), |
940 | ICPU(0x2d, core_params), | |
19e77c28 | 941 | ICPU(0x37, byt_params), |
016c8150 DB |
942 | ICPU(0x3a, core_params), |
943 | ICPU(0x3c, core_params), | |
c7e241df | 944 | ICPU(0x3d, core_params), |
016c8150 DB |
945 | ICPU(0x3e, core_params), |
946 | ICPU(0x3f, core_params), | |
947 | ICPU(0x45, core_params), | |
948 | ICPU(0x46, core_params), | |
43f8a966 | 949 | ICPU(0x47, core_params), |
16405f98 | 950 | ICPU(0x4c, byt_params), |
7ab0256e | 951 | ICPU(0x4e, core_params), |
c7e241df | 952 | ICPU(0x4f, core_params), |
1c939123 | 953 | ICPU(0x5e, core_params), |
c7e241df | 954 | ICPU(0x56, core_params), |
b34ef932 | 955 | ICPU(0x57, knl_params), |
93f0822d DB |
956 | {} |
957 | }; | |
958 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
959 | ||
2f86dc4c DB |
960 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
961 | ICPU(0x56, core_params), | |
962 | {} | |
963 | }; | |
964 | ||
93f0822d DB |
965 | static int intel_pstate_init_cpu(unsigned int cpunum) |
966 | { | |
93f0822d DB |
967 | struct cpudata *cpu; |
968 | ||
c0348717 DB |
969 | if (!all_cpu_data[cpunum]) |
970 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
971 | GFP_KERNEL); | |
93f0822d DB |
972 | if (!all_cpu_data[cpunum]) |
973 | return -ENOMEM; | |
974 | ||
975 | cpu = all_cpu_data[cpunum]; | |
976 | ||
93f0822d | 977 | cpu->cpu = cpunum; |
ba88d433 KCA |
978 | |
979 | if (hwp_active) | |
980 | intel_pstate_hwp_enable(cpu); | |
981 | ||
179e8471 | 982 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 983 | |
93f0822d | 984 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 985 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 986 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
987 | |
988 | if (!hwp_active) | |
989 | cpu->timer.function = intel_pstate_timer_func; | |
990 | else | |
991 | cpu->timer.function = intel_hwp_timer_func; | |
992 | ||
93f0822d | 993 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 994 | intel_pstate_sample(cpu); |
93f0822d DB |
995 | |
996 | add_timer_on(&cpu->timer, cpunum); | |
997 | ||
f16255eb | 998 | pr_debug("intel_pstate: controlling: cpu %d\n", cpunum); |
93f0822d DB |
999 | |
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1004 | { | |
1005 | struct sample *sample; | |
1006 | struct cpudata *cpu; | |
1007 | ||
1008 | cpu = all_cpu_data[cpu_num]; | |
1009 | if (!cpu) | |
1010 | return 0; | |
d37e2b76 | 1011 | sample = &cpu->sample; |
93f0822d DB |
1012 | return sample->freq; |
1013 | } | |
1014 | ||
1015 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
1016 | { | |
d3929b83 DB |
1017 | if (!policy->cpuinfo.max_freq) |
1018 | return -ENODEV; | |
1019 | ||
630ec286 SP |
1020 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && |
1021 | policy->max >= policy->cpuinfo.max_freq) { | |
a0475992 | 1022 | limits.min_policy_pct = 100; |
93f0822d DB |
1023 | limits.min_perf_pct = 100; |
1024 | limits.min_perf = int_tofp(1); | |
36b4bed5 | 1025 | limits.max_policy_pct = 100; |
93f0822d DB |
1026 | limits.max_perf_pct = 100; |
1027 | limits.max_perf = int_tofp(1); | |
4521e1a0 | 1028 | limits.no_turbo = 0; |
d1b68485 | 1029 | return 0; |
93f0822d | 1030 | } |
2f86dc4c | 1031 | |
a0475992 KCA |
1032 | limits.min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
1033 | limits.min_policy_pct = clamp_t(int, limits.min_policy_pct, 0 , 100); | |
285cb990 | 1034 | limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; |
d8f469e9 | 1035 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); |
43717aad CY |
1036 | |
1037 | /* Normalize user input to [min_policy_pct, max_policy_pct] */ | |
1038 | limits.min_perf_pct = max(limits.min_policy_pct, limits.min_sysfs_pct); | |
1039 | limits.min_perf_pct = min(limits.max_policy_pct, limits.min_perf_pct); | |
d8f469e9 | 1040 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); |
43717aad CY |
1041 | limits.max_perf_pct = max(limits.min_policy_pct, limits.max_perf_pct); |
1042 | ||
1043 | /* Make sure min_perf_pct <= max_perf_pct */ | |
1044 | limits.min_perf_pct = min(limits.max_perf_pct, limits.min_perf_pct); | |
1045 | ||
1046 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
d1b68485 | 1047 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d | 1048 | |
2f86dc4c DB |
1049 | if (hwp_active) |
1050 | intel_pstate_hwp_set(); | |
1051 | ||
93f0822d DB |
1052 | return 0; |
1053 | } | |
1054 | ||
1055 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1056 | { | |
be49e346 | 1057 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1058 | |
285cb990 | 1059 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1060 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1061 | return -EINVAL; |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
bb18008f | 1066 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1067 | { |
bb18008f DB |
1068 | int cpu_num = policy->cpu; |
1069 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1070 | |
f16255eb | 1071 | pr_debug("intel_pstate: CPU %d exiting\n", cpu_num); |
bb18008f | 1072 | |
c2294a2f | 1073 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
1074 | if (hwp_active) |
1075 | return; | |
1076 | ||
6c1e4591 | 1077 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
1078 | } |
1079 | ||
2760984f | 1080 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1081 | { |
93f0822d | 1082 | struct cpudata *cpu; |
52e0a509 | 1083 | int rc; |
93f0822d DB |
1084 | |
1085 | rc = intel_pstate_init_cpu(policy->cpu); | |
1086 | if (rc) | |
1087 | return rc; | |
1088 | ||
1089 | cpu = all_cpu_data[policy->cpu]; | |
1090 | ||
dd5fbf70 | 1091 | if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) |
93f0822d DB |
1092 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1093 | else | |
1094 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1095 | ||
b27580b0 DB |
1096 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1097 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1098 | |
1099 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
1100 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1101 | policy->cpuinfo.max_freq = | |
1102 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1103 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1104 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1105 | ||
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static struct cpufreq_driver intel_pstate_driver = { | |
1110 | .flags = CPUFREQ_CONST_LOOPS, | |
1111 | .verify = intel_pstate_verify_policy, | |
1112 | .setpolicy = intel_pstate_set_policy, | |
1113 | .get = intel_pstate_get, | |
1114 | .init = intel_pstate_cpu_init, | |
bb18008f | 1115 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1116 | .name = "intel_pstate", |
93f0822d DB |
1117 | }; |
1118 | ||
6be26498 | 1119 | static int __initdata no_load; |
2f86dc4c | 1120 | static int __initdata no_hwp; |
d64c3b0b | 1121 | static int __initdata hwp_only; |
aa4ea34d | 1122 | static unsigned int force_load; |
6be26498 | 1123 | |
b563b4e3 DB |
1124 | static int intel_pstate_msrs_not_valid(void) |
1125 | { | |
016c8150 | 1126 | if (!pstate_funcs.get_max() || |
c410833a SK |
1127 | !pstate_funcs.get_min() || |
1128 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1129 | return -ENODEV; |
1130 | ||
b563b4e3 DB |
1131 | return 0; |
1132 | } | |
016c8150 | 1133 | |
e0a261a2 | 1134 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1135 | { |
1136 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
1137 | pid_params.p_gain_pct = policy->p_gain_pct; | |
1138 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1139 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1140 | pid_params.deadband = policy->deadband; | |
1141 | pid_params.setpoint = policy->setpoint; | |
1142 | } | |
1143 | ||
e0a261a2 | 1144 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1145 | { |
1146 | pstate_funcs.get_max = funcs->get_max; | |
1147 | pstate_funcs.get_min = funcs->get_min; | |
1148 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1149 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 1150 | pstate_funcs.set = funcs->set; |
007bea09 | 1151 | pstate_funcs.get_vid = funcs->get_vid; |
016c8150 DB |
1152 | } |
1153 | ||
fbbcdc07 AH |
1154 | #if IS_ENABLED(CONFIG_ACPI) |
1155 | #include <acpi/processor.h> | |
1156 | ||
1157 | static bool intel_pstate_no_acpi_pss(void) | |
1158 | { | |
1159 | int i; | |
1160 | ||
1161 | for_each_possible_cpu(i) { | |
1162 | acpi_status status; | |
1163 | union acpi_object *pss; | |
1164 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1165 | struct acpi_processor *pr = per_cpu(processors, i); | |
1166 | ||
1167 | if (!pr) | |
1168 | continue; | |
1169 | ||
1170 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1171 | if (ACPI_FAILURE(status)) | |
1172 | continue; | |
1173 | ||
1174 | pss = buffer.pointer; | |
1175 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1176 | kfree(pss); | |
1177 | return false; | |
1178 | } | |
1179 | ||
1180 | kfree(pss); | |
1181 | } | |
1182 | ||
1183 | return true; | |
1184 | } | |
1185 | ||
966916ea | 1186 | static bool intel_pstate_has_acpi_ppc(void) |
1187 | { | |
1188 | int i; | |
1189 | ||
1190 | for_each_possible_cpu(i) { | |
1191 | struct acpi_processor *pr = per_cpu(processors, i); | |
1192 | ||
1193 | if (!pr) | |
1194 | continue; | |
1195 | if (acpi_has_method(pr->handle, "_PPC")) | |
1196 | return true; | |
1197 | } | |
1198 | return false; | |
1199 | } | |
1200 | ||
1201 | enum { | |
1202 | PSS, | |
1203 | PPC, | |
1204 | }; | |
1205 | ||
fbbcdc07 AH |
1206 | struct hw_vendor_info { |
1207 | u16 valid; | |
1208 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1209 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1210 | int oem_pwr_table; |
fbbcdc07 AH |
1211 | }; |
1212 | ||
1213 | /* Hardware vendor-specific info that has its own power management modes */ | |
1214 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1215 | {1, "HP ", "ProLiant", PSS}, |
1216 | {1, "ORACLE", "X4-2 ", PPC}, | |
1217 | {1, "ORACLE", "X4-2L ", PPC}, | |
1218 | {1, "ORACLE", "X4-2B ", PPC}, | |
1219 | {1, "ORACLE", "X3-2 ", PPC}, | |
1220 | {1, "ORACLE", "X3-2L ", PPC}, | |
1221 | {1, "ORACLE", "X3-2B ", PPC}, | |
1222 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1223 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1224 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1225 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
1226 | {1, "ORACLE", "X4170 M3", PPC}, |
1227 | {1, "ORACLE", "X4275 M3", PPC}, | |
1228 | {1, "ORACLE", "X6-2 ", PPC}, | |
1229 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
1230 | {0, "", ""}, |
1231 | }; | |
1232 | ||
1233 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1234 | { | |
1235 | struct acpi_table_header hdr; | |
1236 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1237 | const struct x86_cpu_id *id; |
1238 | u64 misc_pwr; | |
1239 | ||
1240 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1241 | if (id) { | |
1242 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1243 | if ( misc_pwr & (1 << 8)) | |
1244 | return true; | |
1245 | } | |
fbbcdc07 | 1246 | |
c410833a SK |
1247 | if (acpi_disabled || |
1248 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1249 | return false; |
1250 | ||
1251 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1252 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1253 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1254 | ACPI_OEM_TABLE_ID_SIZE)) | |
1255 | switch (v_info->oem_pwr_table) { | |
1256 | case PSS: | |
1257 | return intel_pstate_no_acpi_pss(); | |
1258 | case PPC: | |
aa4ea34d EZ |
1259 | return intel_pstate_has_acpi_ppc() && |
1260 | (!force_load); | |
966916ea | 1261 | } |
fbbcdc07 AH |
1262 | } |
1263 | ||
1264 | return false; | |
1265 | } | |
1266 | #else /* CONFIG_ACPI not enabled */ | |
1267 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1268 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1269 | #endif /* CONFIG_ACPI */ |
1270 | ||
93f0822d DB |
1271 | static int __init intel_pstate_init(void) |
1272 | { | |
907cc908 | 1273 | int cpu, rc = 0; |
93f0822d | 1274 | const struct x86_cpu_id *id; |
64df1fdf | 1275 | struct cpu_defaults *cpu_def; |
93f0822d | 1276 | |
6be26498 DB |
1277 | if (no_load) |
1278 | return -ENODEV; | |
1279 | ||
93f0822d DB |
1280 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1281 | if (!id) | |
1282 | return -ENODEV; | |
1283 | ||
fbbcdc07 AH |
1284 | /* |
1285 | * The Intel pstate driver will be ignored if the platform | |
1286 | * firmware has its own power management modes. | |
1287 | */ | |
1288 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1289 | return -ENODEV; | |
1290 | ||
64df1fdf | 1291 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1292 | |
64df1fdf BP |
1293 | copy_pid_params(&cpu_def->pid_policy); |
1294 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1295 | |
b563b4e3 DB |
1296 | if (intel_pstate_msrs_not_valid()) |
1297 | return -ENODEV; | |
1298 | ||
93f0822d DB |
1299 | pr_info("Intel P-state driver initializing.\n"); |
1300 | ||
b57ffac5 | 1301 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1302 | if (!all_cpu_data) |
1303 | return -ENOMEM; | |
93f0822d | 1304 | |
64df1fdf | 1305 | if (static_cpu_has_safe(X86_FEATURE_HWP) && !no_hwp) |
ba88d433 | 1306 | hwp_active++; |
2f86dc4c | 1307 | |
d64c3b0b KCA |
1308 | if (!hwp_active && hwp_only) |
1309 | goto out; | |
1310 | ||
93f0822d DB |
1311 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1312 | if (rc) | |
1313 | goto out; | |
1314 | ||
1315 | intel_pstate_debug_expose_params(); | |
1316 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1317 | |
93f0822d DB |
1318 | return rc; |
1319 | out: | |
907cc908 DB |
1320 | get_online_cpus(); |
1321 | for_each_online_cpu(cpu) { | |
1322 | if (all_cpu_data[cpu]) { | |
1323 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1324 | kfree(all_cpu_data[cpu]); | |
1325 | } | |
1326 | } | |
1327 | ||
1328 | put_online_cpus(); | |
1329 | vfree(all_cpu_data); | |
93f0822d DB |
1330 | return -ENODEV; |
1331 | } | |
1332 | device_initcall(intel_pstate_init); | |
1333 | ||
6be26498 DB |
1334 | static int __init intel_pstate_setup(char *str) |
1335 | { | |
1336 | if (!str) | |
1337 | return -EINVAL; | |
1338 | ||
1339 | if (!strcmp(str, "disable")) | |
1340 | no_load = 1; | |
2f86dc4c DB |
1341 | if (!strcmp(str, "no_hwp")) |
1342 | no_hwp = 1; | |
aa4ea34d EZ |
1343 | if (!strcmp(str, "force")) |
1344 | force_load = 1; | |
d64c3b0b KCA |
1345 | if (!strcmp(str, "hwp_only")) |
1346 | hwp_only = 1; | |
6be26498 DB |
1347 | return 0; |
1348 | } | |
1349 | early_param("intel_pstate", intel_pstate_setup); | |
1350 | ||
93f0822d DB |
1351 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1352 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1353 | MODULE_LICENSE("GPL"); |