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cpufreq: intel_pstate: Correct the busy calculation for KNL
[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
55687da1 22#include <linux/sched/cpufreq.h>
93f0822d
DB		 23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
29#include <linux/debugfs.h>
fbbcdc07 30#include <linux/acpi.h>
d6472302 31#include <linux/vmalloc.h>
93f0822d
DB		 32#include <trace/events/power.h>
33
34#include <asm/div64.h>
35#include <asm/msr.h>
36#include <asm/cpu_device_id.h>
64df1fdf 37#include <asm/cpufeature.h>
5b20c944 38#include <asm/intel-family.h>
93f0822d 39
eabd22c6
RW		 40#define INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41#define INTEL_PSTATE_HWP_SAMPLING_INTERVAL (50 * NSEC_PER_MSEC)
42
001c76f0 43#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
1b72e7fd 44#define INTEL_CPUFREQ_TRANSITION_DELAY 500
001c76f0 45
9522a2ff
SP		 46#ifdef CONFIG_ACPI
47#include <acpi/processor.h>
17669006 48#include <acpi/cppc_acpi.h>
9522a2ff
SP		 49#endif
50
f0fe3cd7 51#define FRAC_BITS 8
93f0822d
DB		 52#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 54
a1c9787d
RW		 55#define EXT_BITS 6
56#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 57#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 59
93f0822d
DB		 60static inline int32_t mul_fp(int32_t x, int32_t y)
61{
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63}
64
7180dddf 65static inline int32_t div_fp(s64 x, s64 y)
93f0822d 66{
7180dddf 67 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 68}
69
d022a65e
DB		 70static inline int ceiling_fp(int32_t x)
71{
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79}
80
ff35f02e
RW		 81static inline int32_t percent_fp(int percent)
82{
83 return div_fp(percent, 100);
84}
85
a1c9787d
RW		 86static inline u64 mul_ext_fp(u64 x, u64 y)
87{
88 return (x * y) >> EXT_FRAC_BITS;
89}
90
91static inline u64 div_ext_fp(u64 x, u64 y)
92{
93 return div64_u64(x << EXT_FRAC_BITS, y);
94}
95
e4c204ce
RW		 96static inline int32_t percent_ext_fp(int percent)
97{
98 return div_ext_fp(percent, 100);
99}
100
13ad7701
SP		 101/**
102 * struct sample - Store performance sample
a1c9787d 103 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 104 * performance during last sample period
105 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 106 * P state. This can be different than core_avg_perf
13ad7701
SP		 107 * to account for cpu idle period
108 * @aperf: Difference of actual performance frequency clock count
109 * read from APERF MSR between last and current sample
110 * @mperf: Difference of maximum performance frequency clock count
111 * read from MPERF MSR between last and current sample
112 * @tsc: Difference of time stamp counter between last and
113 * current sample
13ad7701
SP		 114 * @time: Current time from scheduler
115 *
116 * This structure is used in the cpudata structure to store performance sample
117 * data for choosing next P State.
118 */
93f0822d 119struct sample {
a1c9787d 120 int32_t core_avg_perf;
157386b6 121 int32_t busy_scaled;
93f0822d
DB		 122 u64 aperf;
123 u64 mperf;
4055fad3 124 u64 tsc;
a4675fbc 125 u64 time;
93f0822d
DB		 126};
127
13ad7701
SP		 128/**
129 * struct pstate_data - Store P state data
130 * @current_pstate: Current requested P state
131 * @min_pstate: Min P state possible for this platform
132 * @max_pstate: Max P state possible for this platform
133 * @max_pstate_physical:This is physical Max P state for a processor
134 * This can be higher than the max_pstate which can
135 * be limited by platform thermal design power limits
136 * @scaling: Scaling factor to convert frequency to cpufreq
137 * frequency units
138 * @turbo_pstate: Max Turbo P state possible for this platform
001c76f0
RW		 139 * @max_freq: @max_pstate frequency in cpufreq units
140 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 141 *
142 * Stores the per cpu model P state limits and current P state.
143 */
93f0822d
DB		 144struct pstate_data {
145 int current_pstate;
146 int min_pstate;
147 int max_pstate;
3bcc6fa9 148 int max_pstate_physical;
b27580b0 149 int scaling;
93f0822d 150 int turbo_pstate;
001c76f0
RW		 151 unsigned int max_freq;
152 unsigned int turbo_freq;
93f0822d
DB		 153};
154
13ad7701
SP		 155/**
156 * struct vid_data - Stores voltage information data
157 * @min: VID data for this platform corresponding to
158 * the lowest P state
159 * @max: VID data corresponding to the highest P State.
160 * @turbo: VID data for turbo P state
161 * @ratio: Ratio of (vid max - vid min) /
162 * (max P state - Min P State)
163 *
164 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
165 * This data is used in Atom platforms, where in addition to target P state,
166 * the voltage data needs to be specified to select next P State.
167 */
007bea09 168struct vid_data {
21855ff5
DB		 169 int min;
170 int max;
171 int turbo;
007bea09
DB		 172 int32_t ratio;
173};
174
13ad7701
SP		 175/**
176 * struct _pid - Stores PID data
177 * @setpoint: Target set point for busyness or performance
178 * @integral: Storage for accumulated error values
179 * @p_gain: PID proportional gain
180 * @i_gain: PID integral gain
181 * @d_gain: PID derivative gain
182 * @deadband: PID deadband
183 * @last_err: Last error storage for integral part of PID calculation
184 *
185 * Stores PID coefficients and last error for PID controller.
186 */
93f0822d
DB		 187struct _pid {
188 int setpoint;
189 int32_t integral;
190 int32_t p_gain;
191 int32_t i_gain;
192 int32_t d_gain;
193 int deadband;
d253d2a5 194 int32_t last_err;
93f0822d
DB		 195};
196
c5a2ee7d
RW		 197/**
198 * struct global_params - Global parameters, mostly tunable via sysfs.
199 * @no_turbo: Whether or not to use turbo P-states.
200 * @turbo_disabled: Whethet or not turbo P-states are available at all,
201 * based on the MSR_IA32_MISC_ENABLE value and whether or
202 * not the maximum reported turbo P-state is different from
203 * the maximum reported non-turbo one.
204 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
205 * P-state capacity.
206 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
207 * P-state capacity.
208 */
209struct global_params {
210 bool no_turbo;
211 bool turbo_disabled;
212 int max_perf_pct;
213 int min_perf_pct;
eae48f04
SP		 214};
215
13ad7701
SP		 216/**
217 * struct cpudata - Per CPU instance data storage
218 * @cpu: CPU number for this instance data
2f1d407a 219 * @policy: CPUFreq policy value
13ad7701 220 * @update_util: CPUFreq utility callback information
4578ee7e 221 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 222 * @iowait_boost: iowait-related boost fraction
223 * @last_update: Time of the last update.
13ad7701
SP		 224 * @pstate: Stores P state limits for this CPU
225 * @vid: Stores VID limits for this CPU
226 * @pid: Stores PID parameters for this CPU
227 * @last_sample_time: Last Sample time
6e34e1f2
SP		 228 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
229 * This shift is a multiplier to mperf delta to
230 * calculate CPU busy.
13ad7701
SP		 231 * @prev_aperf: Last APERF value read from APERF MSR
232 * @prev_mperf: Last MPERF value read from MPERF MSR
233 * @prev_tsc: Last timestamp counter (TSC) value
234 * @prev_cummulative_iowait: IO Wait time difference from last and
235 * current sample
236 * @sample: Storage for storing last Sample data
1a4fe38a
SP		 237 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
238 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
9522a2ff
SP		 239 * @acpi_perf_data: Stores ACPI perf information read from _PSS
240 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 241 * @epp_powersave: Last saved HWP energy performance preference
242 * (EPP) or energy performance bias (EPB),
243 * when policy switched to performance
8442885f 244 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 245 * @epp_default: Power on default HWP energy performance
246 * preference/bias
247 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
248 * operation
13ad7701
SP		 249 *
250 * This structure stores per CPU instance data for all CPUs.
251 */
93f0822d
DB		 252struct cpudata {
253 int cpu;
254
2f1d407a 255 unsigned int policy;
a4675fbc 256 struct update_util_data update_util;
4578ee7e 257 bool update_util_set;
93f0822d 258
93f0822d 259 struct pstate_data pstate;
007bea09 260 struct vid_data vid;
93f0822d 261 struct _pid pid;
93f0822d 262
09c448d3 263 u64 last_update;
a4675fbc 264 u64 last_sample_time;
6e34e1f2 265 u64 aperf_mperf_shift;
93f0822d
DB		 266 u64 prev_aperf;
267 u64 prev_mperf;
4055fad3 268 u64 prev_tsc;
63d1d656 269 u64 prev_cummulative_iowait;
d37e2b76 270 struct sample sample;
1a4fe38a
SP		 271 int32_t min_perf_ratio;
272 int32_t max_perf_ratio;
9522a2ff
SP		 273#ifdef CONFIG_ACPI
274 struct acpi_processor_performance acpi_perf_data;
275 bool valid_pss_table;
276#endif
09c448d3 277 unsigned int iowait_boost;
984edbdc 278 s16 epp_powersave;
8442885f 279 s16 epp_policy;
984edbdc
SP		 280 s16 epp_default;
281 s16 epp_saved;
93f0822d
DB		 282};
283
284static struct cpudata **all_cpu_data;
13ad7701
SP		 285
286/**
3954517e 287 * struct pstate_adjust_policy - Stores static PID configuration data
13ad7701
SP		 288 * @sample_rate_ms: PID calculation sample rate in ms
289 * @sample_rate_ns: Sample rate calculation in ns
290 * @deadband: PID deadband
291 * @setpoint: PID Setpoint
292 * @p_gain_pct: PID proportional gain
293 * @i_gain_pct: PID integral gain
294 * @d_gain_pct: PID derivative gain
295 *
296 * Stores per CPU model static PID configuration data.
297 */
93f0822d
DB		 298struct pstate_adjust_policy {
299 int sample_rate_ms;
a4675fbc 300 s64 sample_rate_ns;
93f0822d
DB		 301 int deadband;
302 int setpoint;
303 int p_gain_pct;
304 int d_gain_pct;
305 int i_gain_pct;
306};
307
13ad7701
SP		 308/**
309 * struct pstate_funcs - Per CPU model specific callbacks
310 * @get_max: Callback to get maximum non turbo effective P state
311 * @get_max_physical: Callback to get maximum non turbo physical P state
312 * @get_min: Callback to get minimum P state
313 * @get_turbo: Callback to get turbo P state
314 * @get_scaling: Callback to get frequency scaling factor
315 * @get_val: Callback to convert P state to actual MSR write value
316 * @get_vid: Callback to get VID data for Atom platforms
67dd9bf4 317 * @update_util: Active mode utilization update callback.
13ad7701
SP		 318 *
319 * Core and Atom CPU models have different way to get P State limits. This
320 * structure is used to store those callbacks.
321 */
016c8150
DB		 322struct pstate_funcs {
323 int (*get_max)(void);
3bcc6fa9 324 int (*get_max_physical)(void);
016c8150
DB		 325 int (*get_min)(void);
326 int (*get_turbo)(void);
b27580b0 327 int (*get_scaling)(void);
6e34e1f2 328 int (*get_aperf_mperf_shift)(void);
fdfdb2b1 329 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 330 void (*get_vid)(struct cpudata *);
67dd9bf4
RW		 331 void (*update_util)(struct update_util_data *data, u64 time,
332 unsigned int flags);
93f0822d
DB		 333};
334
4a7cb7a9 335static struct pstate_funcs pstate_funcs __read_mostly;
5c439053
RW		 336static struct pstate_adjust_policy pid_params __read_mostly = {
337 .sample_rate_ms = 10,
338 .sample_rate_ns = 10 * NSEC_PER_MSEC,
339 .deadband = 0,
340 .setpoint = 97,
341 .p_gain_pct = 20,
342 .d_gain_pct = 0,
343 .i_gain_pct = 0,
344};
345
4a7cb7a9 346static int hwp_active __read_mostly;
eae48f04 347static bool per_cpu_limits __read_mostly;
016c8150 348
ee8df89a 349static struct cpufreq_driver *intel_pstate_driver __read_mostly;
0c30b65b 350
9522a2ff
SP		 351#ifdef CONFIG_ACPI
352static bool acpi_ppc;
353#endif
13ad7701 354
c5a2ee7d 355static struct global_params global;
93f0822d 356
0c30b65b 357static DEFINE_MUTEX(intel_pstate_driver_lock);
a410c03d
SP		 358static DEFINE_MUTEX(intel_pstate_limits_lock);
359
9522a2ff 360#ifdef CONFIG_ACPI
2b3ec765
SP		 361
362static bool intel_pstate_get_ppc_enable_status(void)
363{
364 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
365 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
366 return true;
367
368 return acpi_ppc;
369}
370
17669006
RW		 371#ifdef CONFIG_ACPI_CPPC_LIB
372
373/* The work item is needed to avoid CPU hotplug locking issues */
374static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
375{
376 sched_set_itmt_support();
377}
378
379static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
380
381static void intel_pstate_set_itmt_prio(int cpu)
382{
383 struct cppc_perf_caps cppc_perf;
384 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
385 int ret;
386
387 ret = cppc_get_perf_caps(cpu, &cppc_perf);
388 if (ret)
389 return;
390
391 /*
392 * The priorities can be set regardless of whether or not
393 * sched_set_itmt_support(true) has been called and it is valid to
394 * update them at any time after it has been called.
395 */
396 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
397
398 if (max_highest_perf <= min_highest_perf) {
399 if (cppc_perf.highest_perf > max_highest_perf)
400 max_highest_perf = cppc_perf.highest_perf;
401
402 if (cppc_perf.highest_perf < min_highest_perf)
403 min_highest_perf = cppc_perf.highest_perf;
404
405 if (max_highest_perf > min_highest_perf) {
406 /*
407 * This code can be run during CPU online under the
408 * CPU hotplug locks, so sched_set_itmt_support()
409 * cannot be called from here. Queue up a work item
410 * to invoke it.
411 */
412 schedule_work(&sched_itmt_work);
413 }
414 }
415}
416#else
417static void intel_pstate_set_itmt_prio(int cpu)
418{
419}
420#endif
421
9522a2ff
SP		 422static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
423{
424 struct cpudata *cpu;
9522a2ff
SP		 425 int ret;
426 int i;
427
17669006
RW		 428 if (hwp_active) {
429 intel_pstate_set_itmt_prio(policy->cpu);
e59a8f7f 430 return;
17669006 431 }
e59a8f7f 432
2b3ec765 433 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 434 return;
435
436 cpu = all_cpu_data[policy->cpu];
437
438 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
439 policy->cpu);
440 if (ret)
441 return;
442
443 /*
444 * Check if the control value in _PSS is for PERF_CTL MSR, which should
445 * guarantee that the states returned by it map to the states in our
446 * list directly.
447 */
448 if (cpu->acpi_perf_data.control_register.space_id !=
449 ACPI_ADR_SPACE_FIXED_HARDWARE)
450 goto err;
451
452 /*
453 * If there is only one entry _PSS, simply ignore _PSS and continue as
454 * usual without taking _PSS into account
455 */
456 if (cpu->acpi_perf_data.state_count < 2)
457 goto err;
458
459 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
460 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
461 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
462 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
463 (u32) cpu->acpi_perf_data.states[i].core_frequency,
464 (u32) cpu->acpi_perf_data.states[i].power,
465 (u32) cpu->acpi_perf_data.states[i].control);
466 }
467
468 /*
469 * The _PSS table doesn't contain whole turbo frequency range.
470 * This just contains +1 MHZ above the max non turbo frequency,
471 * with control value corresponding to max turbo ratio. But
472 * when cpufreq set policy is called, it will call with this
473 * max frequency, which will cause a reduced performance as
474 * this driver uses real max turbo frequency as the max
475 * frequency. So correct this frequency in _PSS table to
b00345d1 476 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 477 * Also need to convert to MHz as _PSS freq is in MHz.
478 */
7de32556 479 if (!global.turbo_disabled)
9522a2ff
SP		 480 cpu->acpi_perf_data.states[0].core_frequency =
481 policy->cpuinfo.max_freq / 1000;
482 cpu->valid_pss_table = true;
6cacd115 483 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 484
485 return;
486
487 err:
488 cpu->valid_pss_table = false;
489 acpi_processor_unregister_performance(policy->cpu);
490}
491
492static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
493{
494 struct cpudata *cpu;
495
496 cpu = all_cpu_data[policy->cpu];
497 if (!cpu->valid_pss_table)
498 return;
499
500 acpi_processor_unregister_performance(policy->cpu);
501}
9522a2ff 502#else
7a3ba767 503static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 504{
505}
506
7a3ba767 507static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 508{
509}
510#endif
511
d253d2a5 512static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 513{
d253d2a5 514 signed int result;
93f0822d
DB		 515 int32_t pterm, dterm, fp_error;
516 int32_t integral_limit;
517
b54a0dfd 518 fp_error = pid->setpoint - busy;
93f0822d 519
b54a0dfd 520 if (abs(fp_error) <= pid->deadband)
93f0822d
DB		 521 return 0;
522
523 pterm = mul_fp(pid->p_gain, fp_error);
524
525 pid->integral += fp_error;
526
e0d4c8f8
KCA		 527 /*
528 * We limit the integral here so that it will never
529 * get higher than 30. This prevents it from becoming
530 * too large an input over long periods of time and allows
531 * it to get factored out sooner.
532 *
533 * The value of 30 was chosen through experimentation.
534 */
93f0822d
DB		 535 integral_limit = int_tofp(30);
536 if (pid->integral > integral_limit)
537 pid->integral = integral_limit;
538 if (pid->integral < -integral_limit)
539 pid->integral = -integral_limit;
540
d253d2a5
BS		 541 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
542 pid->last_err = fp_error;
93f0822d
DB		 543
544 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
51d211e9 545 result = result + (1 << (FRAC_BITS-1));
93f0822d
DB		 546 return (signed int)fp_toint(result);
547}
548
ff35f02e 549static inline void intel_pstate_pid_reset(struct cpudata *cpu)
93f0822d 550{
ff35f02e 551 struct _pid *pid = &cpu->pid;
93f0822d 552
ff35f02e
RW		 553 pid->p_gain = percent_fp(pid_params.p_gain_pct);
554 pid->d_gain = percent_fp(pid_params.d_gain_pct);
555 pid->i_gain = percent_fp(pid_params.i_gain_pct);
556 pid->setpoint = int_tofp(pid_params.setpoint);
557 pid->last_err = pid->setpoint - int_tofp(100);
558 pid->deadband = int_tofp(pid_params.deadband);
559 pid->integral = 0;
93f0822d
DB		 560}
561
4521e1a0
GM		 562static inline void update_turbo_state(void)
563{
564 u64 misc_en;
565 struct cpudata *cpu;
566
567 cpu = all_cpu_data[0];
568 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
7de32556 569 global.turbo_disabled =
4521e1a0
GM		 570 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
571 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
572}
573
c5a2ee7d
RW		 574static int min_perf_pct_min(void)
575{
576 struct cpudata *cpu = all_cpu_data[0];
57caf4ec 577 int turbo_pstate = cpu->pstate.turbo_pstate;
c5a2ee7d 578
57caf4ec 579 return turbo_pstate ?
d4436c0d 580 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
c5a2ee7d
RW		 581}
582
8442885f
SP		 583static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
584{
585 u64 epb;
586 int ret;
587
588 if (!static_cpu_has(X86_FEATURE_EPB))
589 return -ENXIO;
590
591 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
592 if (ret)
593 return (s16)ret;
594
595 return (s16)(epb & 0x0f);
596}
597
598static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
599{
600 s16 epp;
601
984edbdc
SP		 602 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
603 /*
604 * When hwp_req_data is 0, means that caller didn't read
605 * MSR_HWP_REQUEST, so need to read and get EPP.
606 */
607 if (!hwp_req_data) {
608 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
609 &hwp_req_data);
610 if (epp)
611 return epp;
612 }
8442885f 613 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 614 } else {
8442885f
SP		 615 /* When there is no EPP present, HWP uses EPB settings */
616 epp = intel_pstate_get_epb(cpu_data);
984edbdc 617 }
8442885f
SP		 618
619 return epp;
620}
621
984edbdc 622static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 623{
624 u64 epb;
984edbdc 625 int ret;
8442885f
SP		 626
627 if (!static_cpu_has(X86_FEATURE_EPB))
984edbdc 628 return -ENXIO;
8442885f 629
984edbdc
SP		 630 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
631 if (ret)
632 return ret;
8442885f
SP		 633
634 epb = (epb & ~0x0f) | pref;
635 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 636
637 return 0;
8442885f
SP		 638}
639
984edbdc
SP		 640/*
641 * EPP/EPB display strings corresponding to EPP index in the
642 * energy_perf_strings[]
643 * index String
644 *-------------------------------------
645 * 0 default
646 * 1 performance
647 * 2 balance_performance
648 * 3 balance_power
649 * 4 power
650 */
651static const char * const energy_perf_strings[] = {
652 "default",
653 "performance",
654 "balance_performance",
655 "balance_power",
656 "power",
657 NULL
658};
659
660static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
661{
662 s16 epp;
663 int index = -EINVAL;
664
665 epp = intel_pstate_get_epp(cpu_data, 0);
666 if (epp < 0)
667 return epp;
668
669 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
670 /*
671 * Range:
672 * 0x00-0x3F : Performance
673 * 0x40-0x7F : Balance performance
674 * 0x80-0xBF : Balance power
675 * 0xC0-0xFF : Power
676 * The EPP is a 8 bit value, but our ranges restrict the
677 * value which can be set. Here only using top two bits
678 * effectively.
679 */
680 index = (epp >> 6) + 1;
681 } else if (static_cpu_has(X86_FEATURE_EPB)) {
682 /*
683 * Range:
684 * 0x00-0x03 : Performance
685 * 0x04-0x07 : Balance performance
686 * 0x08-0x0B : Balance power
687 * 0x0C-0x0F : Power
688 * The EPB is a 4 bit value, but our ranges restrict the
689 * value which can be set. Here only using top two bits
690 * effectively.
691 */
692 index = (epp >> 2) + 1;
693 }
694
695 return index;
696}
697
698static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
699 int pref_index)
700{
701 int epp = -EINVAL;
702 int ret;
703
704 if (!pref_index)
705 epp = cpu_data->epp_default;
706
707 mutex_lock(&intel_pstate_limits_lock);
708
709 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
710 u64 value;
711
712 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
713 if (ret)
714 goto return_pref;
715
716 value &= ~GENMASK_ULL(31, 24);
717
718 /*
719 * If epp is not default, convert from index into
720 * energy_perf_strings to epp value, by shifting 6
721 * bits left to use only top two bits in epp.
722 * The resultant epp need to shifted by 24 bits to
723 * epp position in MSR_HWP_REQUEST.
724 */
725 if (epp == -EINVAL)
726 epp = (pref_index - 1) << 6;
727
728 value |= (u64)epp << 24;
729 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
730 } else {
731 if (epp == -EINVAL)
732 epp = (pref_index - 1) << 2;
733 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
734 }
735return_pref:
736 mutex_unlock(&intel_pstate_limits_lock);
737
738 return ret;
739}
740
741static ssize_t show_energy_performance_available_preferences(
742 struct cpufreq_policy *policy, char *buf)
743{
744 int i = 0;
745 int ret = 0;
746
747 while (energy_perf_strings[i] != NULL)
748 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
749
750 ret += sprintf(&buf[ret], "\n");
751
752 return ret;
753}
754
755cpufreq_freq_attr_ro(energy_performance_available_preferences);
756
757static ssize_t store_energy_performance_preference(
758 struct cpufreq_policy *policy, const char *buf, size_t count)
759{
760 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
761 char str_preference[21];
762 int ret, i = 0;
763
764 ret = sscanf(buf, "%20s", str_preference);
765 if (ret != 1)
766 return -EINVAL;
767
768 while (energy_perf_strings[i] != NULL) {
769 if (!strcmp(str_preference, energy_perf_strings[i])) {
770 intel_pstate_set_energy_pref_index(cpu_data, i);
771 return count;
772 }
773 ++i;
774 }
775
776 return -EINVAL;
777}
778
779static ssize_t show_energy_performance_preference(
780 struct cpufreq_policy *policy, char *buf)
781{
782 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
783 int preference;
784
785 preference = intel_pstate_get_energy_pref_index(cpu_data);
786 if (preference < 0)
787 return preference;
788
789 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
790}
791
792cpufreq_freq_attr_rw(energy_performance_preference);
793
794static struct freq_attr *hwp_cpufreq_attrs[] = {
795 &energy_performance_preference,
796 &energy_performance_available_preferences,
797 NULL,
798};
799
1a4fe38a
SP		 800static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
801 int *current_max)
2f86dc4c 802{
1a4fe38a 803 u64 cap;
74da56ce 804
2bfc4cbb 805 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
2bfc4cbb 806 if (global.no_turbo)
1a4fe38a 807 *current_max = HWP_GUARANTEED_PERF(cap);
2bfc4cbb 808 else
1a4fe38a
SP		 809 *current_max = HWP_HIGHEST_PERF(cap);
810
811 *phy_max = HWP_HIGHEST_PERF(cap);
812}
813
814static void intel_pstate_hwp_set(unsigned int cpu)
815{
816 struct cpudata *cpu_data = all_cpu_data[cpu];
817 int max, min;
818 u64 value;
819 s16 epp;
820
821 max = cpu_data->max_perf_ratio;
822 min = cpu_data->min_perf_ratio;
eae48f04 823
2bfc4cbb
RW		 824 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
825 min = max;
3f8ed54a 826
2bfc4cbb 827 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
2f86dc4c 828
2bfc4cbb
RW		 829 value &= ~HWP_MIN_PERF(~0L);
830 value |= HWP_MIN_PERF(min);
8442885f 831
2bfc4cbb
RW		 832 value &= ~HWP_MAX_PERF(~0L);
833 value |= HWP_MAX_PERF(max);
8442885f 834
2bfc4cbb
RW		 835 if (cpu_data->epp_policy == cpu_data->policy)
836 goto skip_epp;
8442885f 837
2bfc4cbb 838 cpu_data->epp_policy = cpu_data->policy;
984edbdc 839
2bfc4cbb
RW		 840 if (cpu_data->epp_saved >= 0) {
841 epp = cpu_data->epp_saved;
842 cpu_data->epp_saved = -EINVAL;
843 goto update_epp;
844 }
8442885f 845
2bfc4cbb
RW		 846 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
847 epp = intel_pstate_get_epp(cpu_data, value);
848 cpu_data->epp_powersave = epp;
849 /* If EPP read was failed, then don't try to write */
850 if (epp < 0)
851 goto skip_epp;
8442885f 852
2bfc4cbb
RW		 853 epp = 0;
854 } else {
855 /* skip setting EPP, when saved value is invalid */
856 if (cpu_data->epp_powersave < 0)
857 goto skip_epp;
8442885f 858
2bfc4cbb
RW		 859 /*
860 * No need to restore EPP when it is not zero. This
861 * means:
862 * - Policy is not changed
863 * - user has manually changed
864 * - Error reading EPB
865 */
866 epp = intel_pstate_get_epp(cpu_data, value);
867 if (epp)
868 goto skip_epp;
8442885f 869
2bfc4cbb
RW		 870 epp = cpu_data->epp_powersave;
871 }
984edbdc 872update_epp:
2bfc4cbb
RW		 873 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
874 value &= ~GENMASK_ULL(31, 24);
875 value |= (u64)epp << 24;
876 } else {
877 intel_pstate_set_epb(cpu, epp);
2f86dc4c 878 }
2bfc4cbb
RW		 879skip_epp:
880 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
41cfd64c 881}
2f86dc4c 882
984edbdc
SP		 883static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
884{
885 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
886
887 if (!hwp_active)
888 return 0;
889
890 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
891
892 return 0;
893}
894
8442885f
SP		 895static int intel_pstate_resume(struct cpufreq_policy *policy)
896{
897 if (!hwp_active)
898 return 0;
899
aa439248
RW		 900 mutex_lock(&intel_pstate_limits_lock);
901
8442885f 902 all_cpu_data[policy->cpu]->epp_policy = 0;
2bfc4cbb 903 intel_pstate_hwp_set(policy->cpu);
aa439248
RW		 904
905 mutex_unlock(&intel_pstate_limits_lock);
906
5f98ced1 907 return 0;
8442885f
SP		 908}
909
111b8b3f 910static void intel_pstate_update_policies(void)
41cfd64c 911{
111b8b3f
RW		 912 int cpu;
913
914 for_each_possible_cpu(cpu)
915 cpufreq_update_policy(cpu);
2f86dc4c
DB		 916}
917
93f0822d
DB		 918/************************** debugfs begin ************************/
919static int pid_param_set(void *data, u64 val)
920{
4ddd0146
RW		 921 unsigned int cpu;
922
93f0822d 923 *(u32 *)data = val;
6e7408ac 924 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
4ddd0146
RW		 925 for_each_possible_cpu(cpu)
926 if (all_cpu_data[cpu])
ff35f02e 927 intel_pstate_pid_reset(all_cpu_data[cpu]);
4ddd0146 928
93f0822d
DB		 929 return 0;
930}
845c1cbe 931
93f0822d
DB		 932static int pid_param_get(void *data, u64 *val)
933{
934 *val = *(u32 *)data;
935 return 0;
936}
2d8d1f18 937DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
93f0822d 938
fb1fe104
RW		 939static struct dentry *debugfs_parent;
940
93f0822d
DB		 941struct pid_param {
942 char *name;
943 void *value;
fb1fe104 944 struct dentry *dentry;
93f0822d
DB		 945};
946
947static struct pid_param pid_files[] = {
fb1fe104
RW		 948 {"sample_rate_ms", &pid_params.sample_rate_ms, },
949 {"d_gain_pct", &pid_params.d_gain_pct, },
950 {"i_gain_pct", &pid_params.i_gain_pct, },
951 {"deadband", &pid_params.deadband, },
952 {"setpoint", &pid_params.setpoint, },
953 {"p_gain_pct", &pid_params.p_gain_pct, },
954 {NULL, NULL, }
93f0822d
DB		 955};
956
fb1fe104 957static void intel_pstate_debug_expose_params(void)
93f0822d 958{
fb1fe104 959 int i;
93f0822d
DB		 960
961 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
962 if (IS_ERR_OR_NULL(debugfs_parent))
963 return;
fb1fe104
RW		 964
965 for (i = 0; pid_files[i].name; i++) {
966 struct dentry *dentry;
967
968 dentry = debugfs_create_file(pid_files[i].name, 0660,
969 debugfs_parent, pid_files[i].value,
970 &fops_pid_param);
971 if (!IS_ERR(dentry))
972 pid_files[i].dentry = dentry;
93f0822d
DB		 973 }
974}
975
fb1fe104
RW		 976static void intel_pstate_debug_hide_params(void)
977{
978 int i;
979
980 if (IS_ERR_OR_NULL(debugfs_parent))
981 return;
982
983 for (i = 0; pid_files[i].name; i++) {
984 debugfs_remove(pid_files[i].dentry);
985 pid_files[i].dentry = NULL;
93f0822d 986 }
fb1fe104
RW		 987
988 debugfs_remove(debugfs_parent);
989 debugfs_parent = NULL;
93f0822d
DB		 990}
991
992/************************** debugfs end ************************/
993
994/************************** sysfs begin ************************/
995#define show_one(file_name, object) \
996 static ssize_t show_##file_name \
997 (struct kobject *kobj, struct attribute *attr, char *buf) \
998 { \
7de32556 999 return sprintf(buf, "%u\n", global.object); \
93f0822d
DB		 1000 }
1001
fb1fe104
RW		 1002static ssize_t intel_pstate_show_status(char *buf);
1003static int intel_pstate_update_status(const char *buf, size_t size);
1004
1005static ssize_t show_status(struct kobject *kobj,
1006 struct attribute *attr, char *buf)
1007{
1008 ssize_t ret;
1009
1010 mutex_lock(&intel_pstate_driver_lock);
1011 ret = intel_pstate_show_status(buf);
1012 mutex_unlock(&intel_pstate_driver_lock);
1013
1014 return ret;
1015}
1016
1017static ssize_t store_status(struct kobject *a, struct attribute *b,
1018 const char *buf, size_t count)
1019{
1020 char *p = memchr(buf, '\n', count);
1021 int ret;
1022
1023 mutex_lock(&intel_pstate_driver_lock);
1024 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1025 mutex_unlock(&intel_pstate_driver_lock);
1026
1027 return ret < 0 ? ret : count;
1028}
1029
d01b1f48
KCA		 1030static ssize_t show_turbo_pct(struct kobject *kobj,
1031 struct attribute *attr, char *buf)
1032{
1033 struct cpudata *cpu;
1034 int total, no_turbo, turbo_pct;
1035 uint32_t turbo_fp;
1036
0c30b65b
RW		 1037 mutex_lock(&intel_pstate_driver_lock);
1038
ee8df89a 1039 if (!intel_pstate_driver) {
0c30b65b
RW		 1040 mutex_unlock(&intel_pstate_driver_lock);
1041 return -EAGAIN;
1042 }
1043
d01b1f48
KCA		 1044 cpu = all_cpu_data[0];
1045
1046 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1047 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 1048 turbo_fp = div_fp(no_turbo, total);
d01b1f48 1049 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
0c30b65b
RW		 1050
1051 mutex_unlock(&intel_pstate_driver_lock);
1052
d01b1f48
KCA		 1053 return sprintf(buf, "%u\n", turbo_pct);
1054}
1055
0522424e
KCA		 1056static ssize_t show_num_pstates(struct kobject *kobj,
1057 struct attribute *attr, char *buf)
1058{
1059 struct cpudata *cpu;
1060 int total;
1061
0c30b65b
RW		 1062 mutex_lock(&intel_pstate_driver_lock);
1063
ee8df89a 1064 if (!intel_pstate_driver) {
0c30b65b
RW		 1065 mutex_unlock(&intel_pstate_driver_lock);
1066 return -EAGAIN;
1067 }
1068
0522424e
KCA		 1069 cpu = all_cpu_data[0];
1070 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
0c30b65b
RW		 1071
1072 mutex_unlock(&intel_pstate_driver_lock);
1073
0522424e
KCA		 1074 return sprintf(buf, "%u\n", total);
1075}
1076
4521e1a0
GM		 1077static ssize_t show_no_turbo(struct kobject *kobj,
1078 struct attribute *attr, char *buf)
1079{
1080 ssize_t ret;
1081
0c30b65b
RW		 1082 mutex_lock(&intel_pstate_driver_lock);
1083
ee8df89a 1084 if (!intel_pstate_driver) {
0c30b65b
RW		 1085 mutex_unlock(&intel_pstate_driver_lock);
1086 return -EAGAIN;
1087 }
1088
4521e1a0 1089 update_turbo_state();
7de32556
RW		 1090 if (global.turbo_disabled)
1091 ret = sprintf(buf, "%u\n", global.turbo_disabled);
4521e1a0 1092 else
7de32556 1093 ret = sprintf(buf, "%u\n", global.no_turbo);
4521e1a0 1094
0c30b65b
RW		 1095 mutex_unlock(&intel_pstate_driver_lock);
1096
4521e1a0
GM		 1097 return ret;
1098}
1099
93f0822d 1100static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 1101 const char *buf, size_t count)
93f0822d
DB		 1102{
1103 unsigned int input;
1104 int ret;
845c1cbe 1105
93f0822d
DB		 1106 ret = sscanf(buf, "%u", &input);
1107 if (ret != 1)
1108 return -EINVAL;
4521e1a0 1109
0c30b65b
RW		 1110 mutex_lock(&intel_pstate_driver_lock);
1111
ee8df89a 1112 if (!intel_pstate_driver) {
0c30b65b
RW		 1113 mutex_unlock(&intel_pstate_driver_lock);
1114 return -EAGAIN;
1115 }
1116
a410c03d
SP		 1117 mutex_lock(&intel_pstate_limits_lock);
1118
4521e1a0 1119 update_turbo_state();
7de32556 1120 if (global.turbo_disabled) {
4836df17 1121 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 1122 mutex_unlock(&intel_pstate_limits_lock);
0c30b65b 1123 mutex_unlock(&intel_pstate_driver_lock);
4521e1a0 1124 return -EPERM;
dd5fbf70 1125 }
2f86dc4c 1126
7de32556 1127 global.no_turbo = clamp_t(int, input, 0, 1);
111b8b3f 1128
c5a2ee7d
RW		 1129 if (global.no_turbo) {
1130 struct cpudata *cpu = all_cpu_data[0];
1131 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1132
1133 /* Squash the global minimum into the permitted range. */
1134 if (global.min_perf_pct > pct)
1135 global.min_perf_pct = pct;
1136 }
1137
cd59b4be
RW		 1138 mutex_unlock(&intel_pstate_limits_lock);
1139
7de32556
RW		 1140 intel_pstate_update_policies();
1141
0c30b65b
RW		 1142 mutex_unlock(&intel_pstate_driver_lock);
1143
93f0822d
DB		 1144 return count;
1145}
1146
1147static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1148 const char *buf, size_t count)
93f0822d
DB		 1149{
1150 unsigned int input;
1151 int ret;
845c1cbe 1152
93f0822d
DB		 1153 ret = sscanf(buf, "%u", &input);
1154 if (ret != 1)
1155 return -EINVAL;
1156
0c30b65b
RW		 1157 mutex_lock(&intel_pstate_driver_lock);
1158
ee8df89a 1159 if (!intel_pstate_driver) {
0c30b65b
RW		 1160 mutex_unlock(&intel_pstate_driver_lock);
1161 return -EAGAIN;
1162 }
1163
a410c03d
SP		 1164 mutex_lock(&intel_pstate_limits_lock);
1165
c5a2ee7d 1166 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
111b8b3f 1167
cd59b4be
RW		 1168 mutex_unlock(&intel_pstate_limits_lock);
1169
7de32556
RW		 1170 intel_pstate_update_policies();
1171
0c30b65b
RW		 1172 mutex_unlock(&intel_pstate_driver_lock);
1173
93f0822d
DB		 1174 return count;
1175}
1176
1177static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1178 const char *buf, size_t count)
93f0822d
DB		 1179{
1180 unsigned int input;
1181 int ret;
845c1cbe 1182
93f0822d
DB		 1183 ret = sscanf(buf, "%u", &input);
1184 if (ret != 1)
1185 return -EINVAL;
a0475992 1186
0c30b65b
RW		 1187 mutex_lock(&intel_pstate_driver_lock);
1188
ee8df89a 1189 if (!intel_pstate_driver) {
0c30b65b
RW		 1190 mutex_unlock(&intel_pstate_driver_lock);
1191 return -EAGAIN;
1192 }
1193
a410c03d
SP		 1194 mutex_lock(&intel_pstate_limits_lock);
1195
c5a2ee7d
RW		 1196 global.min_perf_pct = clamp_t(int, input,
1197 min_perf_pct_min(), global.max_perf_pct);
111b8b3f 1198
cd59b4be
RW		 1199 mutex_unlock(&intel_pstate_limits_lock);
1200
7de32556
RW		 1201 intel_pstate_update_policies();
1202
0c30b65b
RW		 1203 mutex_unlock(&intel_pstate_driver_lock);
1204
93f0822d
DB		 1205 return count;
1206}
1207
93f0822d
DB		 1208show_one(max_perf_pct, max_perf_pct);
1209show_one(min_perf_pct, min_perf_pct);
1210
fb1fe104 1211define_one_global_rw(status);
93f0822d
DB		 1212define_one_global_rw(no_turbo);
1213define_one_global_rw(max_perf_pct);
1214define_one_global_rw(min_perf_pct);
d01b1f48 1215define_one_global_ro(turbo_pct);
0522424e 1216define_one_global_ro(num_pstates);
93f0822d
DB		 1217
1218static struct attribute *intel_pstate_attributes[] = {
fb1fe104 1219 &status.attr,
93f0822d 1220 &no_turbo.attr,
d01b1f48 1221 &turbo_pct.attr,
0522424e 1222 &num_pstates.attr,
93f0822d
DB		 1223 NULL
1224};
1225
1226static struct attribute_group intel_pstate_attr_group = {
1227 .attrs = intel_pstate_attributes,
1228};
93f0822d 1229
317dd50e 1230static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1231{
317dd50e 1232 struct kobject *intel_pstate_kobject;
93f0822d
DB		 1233 int rc;
1234
1235 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1236 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 1237 if (WARN_ON(!intel_pstate_kobject))
1238 return;
1239
2d8d1f18 1240 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1241 if (WARN_ON(rc))
1242 return;
1243
1244 /*
1245 * If per cpu limits are enforced there are no global limits, so
1246 * return without creating max/min_perf_pct attributes
1247 */
1248 if (per_cpu_limits)
1249 return;
1250
1251 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1252 WARN_ON(rc);
1253
1254 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1255 WARN_ON(rc);
1256
93f0822d 1257}
93f0822d 1258/************************** sysfs end ************************/
2f86dc4c 1259
ba88d433 1260static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1261{
f05c9665 1262 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 1263 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1264 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1265
ba88d433 1266 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
8442885f 1267 cpudata->epp_policy = 0;
984edbdc
SP		 1268 if (cpudata->epp_default == -EINVAL)
1269 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2f86dc4c
DB		 1270}
1271
6e978b22
SP		 1272#define MSR_IA32_POWER_CTL_BIT_EE 19
1273
1274/* Disable energy efficiency optimization */
1275static void intel_pstate_disable_ee(int cpu)
1276{
1277 u64 power_ctl;
1278 int ret;
1279
1280 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1281 if (ret)
1282 return;
1283
1284 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1285 pr_info("Disabling energy efficiency optimization\n");
1286 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1287 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1288 }
1289}
1290
938d21a2 1291static int atom_get_min_pstate(void)
19e77c28
DB		 1292{
1293 u64 value;
845c1cbe 1294
92134bdb 1295 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1296 return (value >> 8) & 0x7F;
19e77c28
DB		 1297}
1298
938d21a2 1299static int atom_get_max_pstate(void)
19e77c28
DB		 1300{
1301 u64 value;
845c1cbe 1302
92134bdb 1303 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
c16ed060 1304 return (value >> 16) & 0x7F;
19e77c28 1305}
93f0822d 1306
938d21a2 1307static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 1308{
1309 u64 value;
845c1cbe 1310
92134bdb 1311 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
c16ed060 1312 return value & 0x7F;
61d8d2ab
DB		 1313}
1314
fdfdb2b1 1315static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1316{
1317 u64 val;
1318 int32_t vid_fp;
1319 u32 vid;
1320
144c8e17 1321 val = (u64)pstate << 8;
7de32556 1322 if (global.no_turbo && !global.turbo_disabled)
007bea09
DB		 1323 val |= (u64)1 << 32;
1324
1325 vid_fp = cpudata->vid.min + mul_fp(
1326 int_tofp(pstate - cpudata->pstate.min_pstate),
1327 cpudata->vid.ratio);
1328
1329 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1330 vid = ceiling_fp(vid_fp);
007bea09 1331
21855ff5
DB		 1332 if (pstate > cpudata->pstate.max_pstate)
1333 vid = cpudata->vid.turbo;
1334
fdfdb2b1 1335 return val | vid;
007bea09
DB		 1336}
1337
1421df63 1338static int silvermont_get_scaling(void)
b27580b0
DB		 1339{
1340 u64 value;
1341 int i;
1421df63
PL		 1342 /* Defined in Table 35-6 from SDM (Sept 2015) */
1343 static int silvermont_freq_table[] = {
1344 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1345
1346 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1347 i = value & 0x7;
1348 WARN_ON(i > 4);
b27580b0 1349
1421df63
PL		 1350 return silvermont_freq_table[i];
1351}
b27580b0 1352
1421df63
PL		 1353static int airmont_get_scaling(void)
1354{
1355 u64 value;
1356 int i;
1357 /* Defined in Table 35-10 from SDM (Sept 2015) */
1358 static int airmont_freq_table[] = {
1359 83300, 100000, 133300, 116700, 80000,
1360 93300, 90000, 88900, 87500};
1361
1362 rdmsrl(MSR_FSB_FREQ, value);
1363 i = value & 0xF;
1364 WARN_ON(i > 8);
1365
1366 return airmont_freq_table[i];
b27580b0
DB		 1367}
1368
938d21a2 1369static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1370{
1371 u64 value;
1372
92134bdb 1373 rdmsrl(MSR_ATOM_CORE_VIDS, value);
c16ed060
DB		 1374 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1375 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1376 cpudata->vid.ratio = div_fp(
1377 cpudata->vid.max - cpudata->vid.min,
1378 int_tofp(cpudata->pstate.max_pstate -
1379 cpudata->pstate.min_pstate));
21855ff5 1380
92134bdb 1381 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
21855ff5 1382 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1383}
1384
016c8150 1385static int core_get_min_pstate(void)
93f0822d
DB		 1386{
1387 u64 value;
845c1cbe 1388
05e99c8c 1389 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1390 return (value >> 40) & 0xFF;
1391}
1392
3bcc6fa9 1393static int core_get_max_pstate_physical(void)
93f0822d
DB		 1394{
1395 u64 value;
845c1cbe 1396
05e99c8c 1397 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1398 return (value >> 8) & 0xFF;
1399}
1400
8fc7554a
SP		 1401static int core_get_tdp_ratio(u64 plat_info)
1402{
1403 /* Check how many TDP levels present */
1404 if (plat_info & 0x600000000) {
1405 u64 tdp_ctrl;
1406 u64 tdp_ratio;
1407 int tdp_msr;
1408 int err;
1409
1410 /* Get the TDP level (0, 1, 2) to get ratios */
1411 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1412 if (err)
1413 return err;
1414
1415 /* TDP MSR are continuous starting at 0x648 */
1416 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1417 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1418 if (err)
1419 return err;
1420
1421 /* For level 1 and 2, bits[23:16] contain the ratio */
1422 if (tdp_ctrl & 0x03)
1423 tdp_ratio >>= 16;
1424
1425 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1426 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1427
1428 return (int)tdp_ratio;
1429 }
1430
1431 return -ENXIO;
1432}
1433
016c8150 1434static int core_get_max_pstate(void)
93f0822d 1435{
6a35fc2d
SP		 1436 u64 tar;
1437 u64 plat_info;
1438 int max_pstate;
8fc7554a 1439 int tdp_ratio;
6a35fc2d
SP		 1440 int err;
1441
1442 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1443 max_pstate = (plat_info >> 8) & 0xFF;
1444
8fc7554a
SP		 1445 tdp_ratio = core_get_tdp_ratio(plat_info);
1446 if (tdp_ratio <= 0)
1447 return max_pstate;
1448
1449 if (hwp_active) {
1450 /* Turbo activation ratio is not used on HWP platforms */
1451 return tdp_ratio;
1452 }
1453
6a35fc2d
SP		 1454 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1455 if (!err) {
8fc7554a
SP		 1456 int tar_levels;
1457
6a35fc2d 1458 /* Do some sanity checking for safety */
8fc7554a
SP		 1459 tar_levels = tar & 0xff;
1460 if (tdp_ratio - 1 == tar_levels) {
1461 max_pstate = tar_levels;
1462 pr_debug("max_pstate=TAC %x\n", max_pstate);
6a35fc2d
SP		 1463 }
1464 }
845c1cbe 1465
6a35fc2d 1466 return max_pstate;
93f0822d
DB		 1467}
1468
016c8150 1469static int core_get_turbo_pstate(void)
93f0822d
DB		 1470{
1471 u64 value;
1472 int nont, ret;
845c1cbe 1473
100cf6f2 1474 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1475 nont = core_get_max_pstate();
285cb990 1476 ret = (value) & 255;
93f0822d
DB		 1477 if (ret <= nont)
1478 ret = nont;
1479 return ret;
1480}
1481
b27580b0
DB		 1482static inline int core_get_scaling(void)
1483{
1484 return 100000;
1485}
1486
fdfdb2b1 1487static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1488{
1489 u64 val;
1490
144c8e17 1491 val = (u64)pstate << 8;
7de32556 1492 if (global.no_turbo && !global.turbo_disabled)
016c8150
DB		 1493 val |= (u64)1 << 32;
1494
fdfdb2b1 1495 return val;
016c8150
DB		 1496}
1497
6e34e1f2
SP		 1498static int knl_get_aperf_mperf_shift(void)
1499{
1500 return 10;
1501}
1502
b34ef932
DC		 1503static int knl_get_turbo_pstate(void)
1504{
1505 u64 value;
1506 int nont, ret;
1507
100cf6f2 1508 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1509 nont = core_get_max_pstate();
1510 ret = (((value) >> 8) & 0xFF);
1511 if (ret <= nont)
1512 ret = nont;
1513 return ret;
1514}
1515
b02aabe8 1516static int intel_pstate_get_base_pstate(struct cpudata *cpu)
93f0822d 1517{
b02aabe8
RW		 1518 return global.no_turbo || global.turbo_disabled ?
1519 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
93f0822d
DB		 1520}
1521
a6c6ead1 1522static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1523{
bc95a454
RW		 1524 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1525 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1526 /*
1527 * Generally, there is no guarantee that this code will always run on
1528 * the CPU being updated, so force the register update to run on the
1529 * right CPU.
1530 */
1531 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1532 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1533}
1534
a6c6ead1
RW		 1535static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1536{
1537 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1538}
1539
1540static void intel_pstate_max_within_limits(struct cpudata *cpu)
1541{
b02aabe8 1542 int pstate;
a6c6ead1
RW		 1543
1544 update_turbo_state();
b02aabe8 1545 pstate = intel_pstate_get_base_pstate(cpu);
1a4fe38a 1546 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
b02aabe8 1547 intel_pstate_set_pstate(cpu, pstate);
a6c6ead1
RW		 1548}
1549
93f0822d
DB		 1550static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1551{
016c8150
DB		 1552 cpu->pstate.min_pstate = pstate_funcs.get_min();
1553 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1554 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1555 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1556 cpu->pstate.scaling = pstate_funcs.get_scaling();
001c76f0
RW		 1557 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1558 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d 1559
6e34e1f2
SP		 1560 if (pstate_funcs.get_aperf_mperf_shift)
1561 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1562
007bea09
DB		 1563 if (pstate_funcs.get_vid)
1564 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1565
1566 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1567}
1568
a1c9787d 1569static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1570{
6b17ddb2 1571 struct sample *sample = &cpu->sample;
e66c1768 1572
a1c9787d 1573 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1574}
1575
4fec7ad5 1576static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1577{
93f0822d 1578 u64 aperf, mperf;
4ab60c3f 1579 unsigned long flags;
4055fad3 1580 u64 tsc;
93f0822d 1581
4ab60c3f 1582 local_irq_save(flags);
93f0822d
DB		 1583 rdmsrl(MSR_IA32_APERF, aperf);
1584 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1585 tsc = rdtsc();
4fec7ad5 1586 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1587 local_irq_restore(flags);
4fec7ad5 1588 return false;
8e601a9f 1589 }
4ab60c3f 1590 local_irq_restore(flags);
b69880f9 1591
c4ee841f 1592 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1593 cpu->sample.time = time;
d37e2b76
DB		 1594 cpu->sample.aperf = aperf;
1595 cpu->sample.mperf = mperf;
4055fad3 1596 cpu->sample.tsc = tsc;
d37e2b76
DB		 1597 cpu->sample.aperf -= cpu->prev_aperf;
1598 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1599 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1600
93f0822d
DB		 1601 cpu->prev_aperf = aperf;
1602 cpu->prev_mperf = mperf;
4055fad3 1603 cpu->prev_tsc = tsc;
febce40f
RW		 1604 /*
1605 * First time this function is invoked in a given cycle, all of the
1606 * previous sample data fields are equal to zero or stale and they must
1607 * be populated with meaningful numbers for things to work, so assume
1608 * that sample.time will always be reset before setting the utilization
1609 * update hook and make the caller skip the sample then.
1610 */
eabd22c6
RW		 1611 if (cpu->last_sample_time) {
1612 intel_pstate_calc_avg_perf(cpu);
1613 return true;
1614 }
1615 return false;
93f0822d
DB		 1616}
1617
8fa520af
PL		 1618static inline int32_t get_avg_frequency(struct cpudata *cpu)
1619{
a1c9787d
RW		 1620 return mul_ext_fp(cpu->sample.core_avg_perf,
1621 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
8fa520af
PL		 1622}
1623
bdcaa23f
PL		 1624static inline int32_t get_avg_pstate(struct cpudata *cpu)
1625{
8edb0a6e
RW		 1626 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1627 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1628}
1629
e70eed2b
PL		 1630static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1631{
1632 struct sample *sample = &cpu->sample;
09c448d3 1633 int32_t busy_frac, boost;
0843e83c 1634 int target, avg_pstate;
e70eed2b 1635
6e34e1f2
SP		 1636 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1637 sample->tsc);
63d1d656 1638
09c448d3
RW		 1639 boost = cpu->iowait_boost;
1640 cpu->iowait_boost >>= 1;
63d1d656 1641
09c448d3
RW		 1642 if (busy_frac < boost)
1643 busy_frac = boost;
63d1d656 1644
09c448d3 1645 sample->busy_scaled = busy_frac * 100;
0843e83c 1646
7de32556 1647 target = global.no_turbo || global.turbo_disabled ?
0843e83c
RW		 1648 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1649 target += target >> 2;
1650 target = mul_fp(target, busy_frac);
1651 if (target < cpu->pstate.min_pstate)
1652 target = cpu->pstate.min_pstate;
1653
1654 /*
1655 * If the average P-state during the previous cycle was higher than the
1656 * current target, add 50% of the difference to the target to reduce
1657 * possible performance oscillations and offset possible performance
1658 * loss related to moving the workload from one CPU to another within
1659 * a package/module.
1660 */
1661 avg_pstate = get_avg_pstate(cpu);
1662 if (avg_pstate > target)
1663 target += (avg_pstate - target) >> 1;
1664
1665 return target;
e70eed2b
PL		 1666}
1667
157386b6 1668static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
93f0822d 1669{
1aa7a6e2 1670 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
a4675fbc 1671 u64 duration_ns;
93f0822d 1672
e0d4c8f8 1673 /*
f00593a4
RW		 1674 * perf_scaled is the ratio of the average P-state during the last
1675 * sampling period to the P-state requested last time (in percent).
1676 *
1677 * That measures the system's response to the previous P-state
1678 * selection.
e0d4c8f8 1679 */
22590efb
RW		 1680 max_pstate = cpu->pstate.max_pstate_physical;
1681 current_pstate = cpu->pstate.current_pstate;
1aa7a6e2 1682 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
a1c9787d 1683 div_fp(100 * max_pstate, current_pstate));
c4ee841f 1684
e0d4c8f8 1685 /*
a4675fbc
RW		 1686 * Since our utilization update callback will not run unless we are
1687 * in C0, check if the actual elapsed time is significantly greater (3x)
1688 * than our sample interval. If it is, then we were idle for a long
1aa7a6e2 1689 * enough period of time to adjust our performance metric.
e0d4c8f8 1690 */
a4675fbc 1691 duration_ns = cpu->sample.time - cpu->last_sample_time;
febce40f 1692 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
22590efb 1693 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1aa7a6e2 1694 perf_scaled = mul_fp(perf_scaled, sample_ratio);
ffb81056 1695 } else {
6e34e1f2
SP		 1696 sample_ratio = div_fp(100 * (cpu->sample.mperf << cpu->aperf_mperf_shift),
1697 cpu->sample.tsc);
ffb81056 1698 if (sample_ratio < int_tofp(1))
1aa7a6e2 1699 perf_scaled = 0;
c4ee841f
DB		 1700 }
1701
1aa7a6e2
RW		 1702 cpu->sample.busy_scaled = perf_scaled;
1703 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
93f0822d
DB		 1704}
1705
001c76f0 1706static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1 1707{
b02aabe8
RW		 1708 int max_pstate = intel_pstate_get_base_pstate(cpu);
1709 int min_pstate;
fdfdb2b1 1710
1a4fe38a
SP		 1711 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1712 max_pstate = max(min_pstate, cpu->max_perf_ratio);
b02aabe8 1713 return clamp_t(int, pstate, min_pstate, max_pstate);
001c76f0
RW		 1714}
1715
1716static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1717{
fdfdb2b1
RW		 1718 if (pstate == cpu->pstate.current_pstate)
1719 return;
1720
bc95a454 1721 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1722 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1723}
1724
67dd9bf4 1725static void intel_pstate_adjust_pstate(struct cpudata *cpu, int target_pstate)
93f0822d 1726{
67dd9bf4 1727 int from = cpu->pstate.current_pstate;
4055fad3
DS		 1728 struct sample *sample;
1729
001c76f0
RW		 1730 update_turbo_state();
1731
64078299
RW		 1732 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1733 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
fdfdb2b1 1734 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1735
1736 sample = &cpu->sample;
a1c9787d 1737 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1738 fp_toint(sample->busy_scaled),
4055fad3
DS		 1739 from,
1740 cpu->pstate.current_pstate,
1741 sample->mperf,
1742 sample->aperf,
1743 sample->tsc,
3ba7bcaa
SP		 1744 get_avg_frequency(cpu),
1745 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1746}
1747
eabd22c6
RW		 1748static void intel_pstate_update_util_pid(struct update_util_data *data,
1749 u64 time, unsigned int flags)
1750{
1751 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1752 u64 delta_ns = time - cpu->sample.time;
1753
1754 if ((s64)delta_ns < pid_params.sample_rate_ns)
1755 return;
1756
67dd9bf4
RW		 1757 if (intel_pstate_sample(cpu, time)) {
1758 int target_pstate;
1759
1760 target_pstate = get_target_pstate_use_performance(cpu);
1761 intel_pstate_adjust_pstate(cpu, target_pstate);
1762 }
eabd22c6
RW		 1763}
1764
a4675fbc 1765static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1766 unsigned int flags)
93f0822d 1767{
a4675fbc 1768 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1769 u64 delta_ns;
1770
eabd22c6
RW		 1771 if (flags & SCHED_CPUFREQ_IOWAIT) {
1772 cpu->iowait_boost = int_tofp(1);
1773 } else if (cpu->iowait_boost) {
1774 /* Clear iowait_boost if the CPU may have been idle. */
1775 delta_ns = time - cpu->last_update;
1776 if (delta_ns > TICK_NSEC)
1777 cpu->iowait_boost = 0;
09c448d3 1778 }
eabd22c6 1779 cpu->last_update = time;
09c448d3 1780 delta_ns = time - cpu->sample.time;
eabd22c6
RW		 1781 if ((s64)delta_ns < INTEL_PSTATE_DEFAULT_SAMPLING_INTERVAL)
1782 return;
4fec7ad5 1783
67dd9bf4
RW		 1784 if (intel_pstate_sample(cpu, time)) {
1785 int target_pstate;
93f0822d 1786
67dd9bf4
RW		 1787 target_pstate = get_target_pstate_use_cpu_load(cpu);
1788 intel_pstate_adjust_pstate(cpu, target_pstate);
1789 }
1790}
eabd22c6 1791
2f49afc2
RW		 1792static struct pstate_funcs core_funcs = {
1793 .get_max = core_get_max_pstate,
1794 .get_max_physical = core_get_max_pstate_physical,
1795 .get_min = core_get_min_pstate,
1796 .get_turbo = core_get_turbo_pstate,
1797 .get_scaling = core_get_scaling,
1798 .get_val = core_get_val,
1799 .update_util = intel_pstate_update_util_pid,
de4a76cb
RW		 1800};
1801
2f49afc2
RW		 1802static const struct pstate_funcs silvermont_funcs = {
1803 .get_max = atom_get_max_pstate,
1804 .get_max_physical = atom_get_max_pstate,
1805 .get_min = atom_get_min_pstate,
1806 .get_turbo = atom_get_turbo_pstate,
1807 .get_val = atom_get_val,
1808 .get_scaling = silvermont_get_scaling,
1809 .get_vid = atom_get_vid,
1810 .update_util = intel_pstate_update_util,
de4a76cb
RW		 1811};
1812
2f49afc2
RW		 1813static const struct pstate_funcs airmont_funcs = {
1814 .get_max = atom_get_max_pstate,
1815 .get_max_physical = atom_get_max_pstate,
1816 .get_min = atom_get_min_pstate,
1817 .get_turbo = atom_get_turbo_pstate,
1818 .get_val = atom_get_val,
1819 .get_scaling = airmont_get_scaling,
1820 .get_vid = atom_get_vid,
1821 .update_util = intel_pstate_update_util,
de4a76cb
RW		 1822};
1823
2f49afc2
RW		 1824static const struct pstate_funcs knl_funcs = {
1825 .get_max = core_get_max_pstate,
1826 .get_max_physical = core_get_max_pstate_physical,
1827 .get_min = core_get_min_pstate,
1828 .get_turbo = knl_get_turbo_pstate,
6e34e1f2 1829 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2f49afc2
RW		 1830 .get_scaling = core_get_scaling,
1831 .get_val = core_get_val,
1832 .update_util = intel_pstate_update_util_pid,
de4a76cb
RW		 1833};
1834
2f49afc2
RW		 1835static const struct pstate_funcs bxt_funcs = {
1836 .get_max = core_get_max_pstate,
1837 .get_max_physical = core_get_max_pstate_physical,
1838 .get_min = core_get_min_pstate,
1839 .get_turbo = core_get_turbo_pstate,
1840 .get_scaling = core_get_scaling,
1841 .get_val = core_get_val,
1842 .update_util = intel_pstate_update_util,
de4a76cb
RW		 1843};
1844
93f0822d 1845#define ICPU(model, policy) \
6cbd7ee1
DB		 1846 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1847 (unsigned long)&policy }
93f0822d
DB		 1848
1849static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2f49afc2
RW		 1850 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1851 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1852 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1853 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1854 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1855 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1856 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1857 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1858 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1859 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1860 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1861 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1862 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1863 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1864 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1865 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1866 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1867 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1868 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_funcs),
630e5757 1869 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, bxt_funcs),
93f0822d
DB		 1870 {}
1871};
1872MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1873
29327c84 1874static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2f49afc2
RW		 1875 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1876 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1877 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
2f86dc4c
DB		 1878 {}
1879};
1880
6e978b22 1881static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2f49afc2 1882 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
6e978b22
SP		 1883 {}
1884};
1885
8ca6ce37
RW		 1886static bool pid_in_use(void);
1887
93f0822d
DB		 1888static int intel_pstate_init_cpu(unsigned int cpunum)
1889{
93f0822d
DB		 1890 struct cpudata *cpu;
1891
eae48f04
SP		 1892 cpu = all_cpu_data[cpunum];
1893
1894 if (!cpu) {
c5a2ee7d 1895 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
eae48f04
SP		 1896 if (!cpu)
1897 return -ENOMEM;
1898
1899 all_cpu_data[cpunum] = cpu;
eae48f04 1900
984edbdc
SP		 1901 cpu->epp_default = -EINVAL;
1902 cpu->epp_powersave = -EINVAL;
1903 cpu->epp_saved = -EINVAL;
eae48f04 1904 }
93f0822d
DB		 1905
1906 cpu = all_cpu_data[cpunum];
1907
93f0822d 1908 cpu->cpu = cpunum;
ba88d433 1909
a4675fbc 1910 if (hwp_active) {
6e978b22
SP		 1911 const struct x86_cpu_id *id;
1912
1913 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1914 if (id)
1915 intel_pstate_disable_ee(cpunum);
1916
ba88d433 1917 intel_pstate_hwp_enable(cpu);
8ca6ce37 1918 } else if (pid_in_use()) {
694cb173 1919 intel_pstate_pid_reset(cpu);
a4675fbc 1920 }
ba88d433 1921
179e8471 1922 intel_pstate_get_cpu_pstates(cpu);
016c8150 1923
4836df17 1924 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 1925
1926 return 0;
1927}
1928
1929static unsigned int intel_pstate_get(unsigned int cpu_num)
1930{
f96fd0c8 1931 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 1932
f96fd0c8 1933 return cpu ? get_avg_frequency(cpu) : 0;
93f0822d
DB		 1934}
1935
febce40f 1936static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 1937{
febce40f
RW		 1938 struct cpudata *cpu = all_cpu_data[cpu_num];
1939
62611cb9
LB		 1940 if (hwp_active)
1941 return;
1942
5ab666e0
RW		 1943 if (cpu->update_util_set)
1944 return;
1945
febce40f
RW		 1946 /* Prevent intel_pstate_update_util() from using stale data. */
1947 cpu->sample.time = 0;
67dd9bf4
RW		 1948 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1949 pstate_funcs.update_util);
4578ee7e 1950 cpu->update_util_set = true;
bb6ab52f
RW		 1951}
1952
1953static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1954{
4578ee7e
CY		 1955 struct cpudata *cpu_data = all_cpu_data[cpu];
1956
1957 if (!cpu_data->update_util_set)
1958 return;
1959
0bed612b 1960 cpufreq_remove_update_util_hook(cpu);
4578ee7e 1961 cpu_data->update_util_set = false;
bb6ab52f
RW		 1962 synchronize_sched();
1963}
1964
80b120ca
RW		 1965static int intel_pstate_get_max_freq(struct cpudata *cpu)
1966{
1967 return global.turbo_disabled || global.no_turbo ?
1968 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1969}
1970
eae48f04 1971static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
c5a2ee7d 1972 struct cpudata *cpu)
eae48f04 1973{
80b120ca 1974 int max_freq = intel_pstate_get_max_freq(cpu);
e4c204ce 1975 int32_t max_policy_perf, min_policy_perf;
1a4fe38a 1976 int max_state, turbo_max;
a410c03d 1977
1a4fe38a
SP		 1978 /*
1979 * HWP needs some special consideration, because on BDX the
1980 * HWP_REQUEST uses abstract value to represent performance
1981 * rather than pure ratios.
1982 */
1983 if (hwp_active) {
1984 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1985 } else {
1986 max_state = intel_pstate_get_base_pstate(cpu);
1987 turbo_max = cpu->pstate.turbo_pstate;
1988 }
1989
1990 max_policy_perf = max_state * policy->max / max_freq;
5879f877 1991 if (policy->max == policy->min) {
e4c204ce 1992 min_policy_perf = max_policy_perf;
5879f877 1993 } else {
1a4fe38a 1994 min_policy_perf = max_state * policy->min / max_freq;
e4c204ce
RW		 1995 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1996 0, max_policy_perf);
5879f877 1997 }
eae48f04 1998
1a4fe38a
SP		 1999 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2000 policy->cpu, max_state,
2001 min_policy_perf, max_policy_perf);
2002
e4c204ce 2003 /* Normalize user input to [min_perf, max_perf] */
c5a2ee7d 2004 if (per_cpu_limits) {
1a4fe38a
SP		 2005 cpu->min_perf_ratio = min_policy_perf;
2006 cpu->max_perf_ratio = max_policy_perf;
c5a2ee7d
RW		 2007 } else {
2008 int32_t global_min, global_max;
2009
2010 /* Global limits are in percent of the maximum turbo P-state. */
1a4fe38a
SP		 2011 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2012 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
c5a2ee7d 2013 global_min = clamp_t(int32_t, global_min, 0, global_max);
eae48f04 2014
1a4fe38a
SP		 2015 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2016 global_min, global_max);
c5a2ee7d 2017
1a4fe38a
SP		 2018 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2019 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2020 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2021 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
eae48f04 2022
1a4fe38a
SP		 2023 /* Make sure min_perf <= max_perf */
2024 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2025 cpu->max_perf_ratio);
eae48f04 2026
1a4fe38a
SP		 2027 }
2028 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2029 cpu->max_perf_ratio,
2030 cpu->min_perf_ratio);
eae48f04
SP		 2031}
2032
93f0822d
DB		 2033static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2034{
3be9200d
SP		 2035 struct cpudata *cpu;
2036
d3929b83
DB		 2037 if (!policy->cpuinfo.max_freq)
2038 return -ENODEV;
2039
2c2c1af4
SP		 2040 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2041 policy->cpuinfo.max_freq, policy->max);
2042
a6c6ead1 2043 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 2044 cpu->policy = policy->policy;
2045
b59fe540
SP		 2046 mutex_lock(&intel_pstate_limits_lock);
2047
c5a2ee7d 2048 intel_pstate_update_perf_limits(policy, cpu);
a240c4aa 2049
2f1d407a 2050 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 2051 /*
2052 * NOHZ_FULL CPUs need this as the governor callback may not
2053 * be invoked on them.
2054 */
2055 intel_pstate_clear_update_util_hook(policy->cpu);
2056 intel_pstate_max_within_limits(cpu);
82b4e03e
LB		 2057 } else {
2058 intel_pstate_set_update_util_hook(policy->cpu);
a6c6ead1
RW		 2059 }
2060
5f98ced1 2061 if (hwp_active)
2bfc4cbb 2062 intel_pstate_hwp_set(policy->cpu);
2f86dc4c 2063
b59fe540
SP		 2064 mutex_unlock(&intel_pstate_limits_lock);
2065
93f0822d
DB		 2066 return 0;
2067}
2068
80b120ca
RW		 2069static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2070 struct cpudata *cpu)
2071{
2072 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2073 policy->max < policy->cpuinfo.max_freq &&
2074 policy->max > cpu->pstate.max_freq) {
2075 pr_debug("policy->max > max non turbo frequency\n");
2076 policy->max = policy->cpuinfo.max_freq;
2077 }
2078}
2079
93f0822d
DB		 2080static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2081{
7d9a8a9f 2082 struct cpudata *cpu = all_cpu_data[policy->cpu];
7d9a8a9f
SP		 2083
2084 update_turbo_state();
80b120ca
RW		 2085 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2086 intel_pstate_get_max_freq(cpu));
93f0822d 2087
285cb990 2088 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 2089 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 2090 return -EINVAL;
2091
80b120ca
RW		 2092 intel_pstate_adjust_policy_max(policy, cpu);
2093
93f0822d
DB		 2094 return 0;
2095}
2096
001c76f0
RW		 2097static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2098{
2099 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2100}
2101
bb18008f 2102static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 2103{
001c76f0 2104 pr_debug("CPU %d exiting\n", policy->cpu);
93f0822d 2105
001c76f0 2106 intel_pstate_clear_update_util_hook(policy->cpu);
984edbdc
SP		 2107 if (hwp_active)
2108 intel_pstate_hwp_save_state(policy);
2109 else
001c76f0
RW		 2110 intel_cpufreq_stop_cpu(policy);
2111}
bb18008f 2112
001c76f0
RW		 2113static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2114{
2115 intel_pstate_exit_perf_limits(policy);
a4675fbc 2116
001c76f0 2117 policy->fast_switch_possible = false;
2f86dc4c 2118
001c76f0 2119 return 0;
93f0822d
DB		 2120}
2121
001c76f0 2122static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 2123{
93f0822d 2124 struct cpudata *cpu;
52e0a509 2125 int rc;
93f0822d
DB		 2126
2127 rc = intel_pstate_init_cpu(policy->cpu);
2128 if (rc)
2129 return rc;
2130
2131 cpu = all_cpu_data[policy->cpu];
2132
1a4fe38a
SP		 2133 cpu->max_perf_ratio = 0xFF;
2134 cpu->min_perf_ratio = 0;
93f0822d 2135
b27580b0
DB		 2136 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2137 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 2138
2139 /* cpuinfo and default policy values */
b27580b0 2140 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e 2141 update_turbo_state();
7de32556 2142 policy->cpuinfo.max_freq = global.turbo_disabled ?
983e600e
SP		 2143 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2144 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2145
9522a2ff 2146 intel_pstate_init_acpi_perf_limits(policy);
93f0822d
DB		 2147 cpumask_set_cpu(policy->cpu, policy->cpus);
2148
001c76f0
RW		 2149 policy->fast_switch_possible = true;
2150
93f0822d
DB		 2151 return 0;
2152}
2153
001c76f0 2154static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 2155{
001c76f0
RW		 2156 int ret = __intel_pstate_cpu_init(policy);
2157
2158 if (ret)
2159 return ret;
2160
2161 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
7de32556 2162 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
001c76f0
RW		 2163 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2164 else
2165 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff
SP		 2166
2167 return 0;
2168}
2169
001c76f0 2170static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 2171 .flags = CPUFREQ_CONST_LOOPS,
2172 .verify = intel_pstate_verify_policy,
2173 .setpolicy = intel_pstate_set_policy,
984edbdc 2174 .suspend = intel_pstate_hwp_save_state,
8442885f 2175 .resume = intel_pstate_resume,
93f0822d
DB		 2176 .get = intel_pstate_get,
2177 .init = intel_pstate_cpu_init,
9522a2ff 2178 .exit = intel_pstate_cpu_exit,
bb18008f 2179 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 2180 .name = "intel_pstate",
93f0822d
DB		 2181};
2182
001c76f0
RW		 2183static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2184{
2185 struct cpudata *cpu = all_cpu_data[policy->cpu];
001c76f0
RW		 2186
2187 update_turbo_state();
80b120ca
RW		 2188 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2189 intel_pstate_get_max_freq(cpu));
001c76f0 2190
80b120ca 2191 intel_pstate_adjust_policy_max(policy, cpu);
001c76f0 2192
c5a2ee7d
RW		 2193 intel_pstate_update_perf_limits(policy, cpu);
2194
001c76f0
RW		 2195 return 0;
2196}
2197
001c76f0
RW		 2198static int intel_cpufreq_target(struct cpufreq_policy *policy,
2199 unsigned int target_freq,
2200 unsigned int relation)
2201{
2202 struct cpudata *cpu = all_cpu_data[policy->cpu];
2203 struct cpufreq_freqs freqs;
2204 int target_pstate;
2205
64897b20
RW		 2206 update_turbo_state();
2207
001c76f0 2208 freqs.old = policy->cur;
64897b20 2209 freqs.new = target_freq;
001c76f0
RW		 2210
2211 cpufreq_freq_transition_begin(policy, &freqs);
2212 switch (relation) {
2213 case CPUFREQ_RELATION_L:
2214 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2215 break;
2216 case CPUFREQ_RELATION_H:
2217 target_pstate = freqs.new / cpu->pstate.scaling;
2218 break;
2219 default:
2220 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2221 break;
2222 }
2223 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2224 if (target_pstate != cpu->pstate.current_pstate) {
2225 cpu->pstate.current_pstate = target_pstate;
2226 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2227 pstate_funcs.get_val(cpu, target_pstate));
2228 }
64078299 2229 freqs.new = target_pstate * cpu->pstate.scaling;
001c76f0
RW		 2230 cpufreq_freq_transition_end(policy, &freqs, false);
2231
2232 return 0;
2233}
2234
2235static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2236 unsigned int target_freq)
2237{
2238 struct cpudata *cpu = all_cpu_data[policy->cpu];
2239 int target_pstate;
2240
64897b20
RW		 2241 update_turbo_state();
2242
001c76f0 2243 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
64078299 2244 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
001c76f0 2245 intel_pstate_update_pstate(cpu, target_pstate);
64078299 2246 return target_pstate * cpu->pstate.scaling;
001c76f0
RW		 2247}
2248
2249static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2250{
2251 int ret = __intel_pstate_cpu_init(policy);
2252
2253 if (ret)
2254 return ret;
2255
2256 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
1b72e7fd 2257 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
001c76f0
RW		 2258 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2259 policy->cur = policy->cpuinfo.min_freq;
2260
2261 return 0;
2262}
2263
2264static struct cpufreq_driver intel_cpufreq = {
2265 .flags = CPUFREQ_CONST_LOOPS,
2266 .verify = intel_cpufreq_verify_policy,
2267 .target = intel_cpufreq_target,
2268 .fast_switch = intel_cpufreq_fast_switch,
2269 .init = intel_cpufreq_cpu_init,
2270 .exit = intel_pstate_cpu_exit,
2271 .stop_cpu = intel_cpufreq_stop_cpu,
2272 .name = "intel_cpufreq",
2273};
2274
ee8df89a 2275static struct cpufreq_driver *default_driver = &intel_pstate;
001c76f0 2276
8ca6ce37
RW		 2277static bool pid_in_use(void)
2278{
2279 return intel_pstate_driver == &intel_pstate &&
2280 pstate_funcs.update_util == intel_pstate_update_util_pid;
2281}
2282
fb1fe104
RW		 2283static void intel_pstate_driver_cleanup(void)
2284{
2285 unsigned int cpu;
2286
2287 get_online_cpus();
2288 for_each_online_cpu(cpu) {
2289 if (all_cpu_data[cpu]) {
2290 if (intel_pstate_driver == &intel_pstate)
2291 intel_pstate_clear_update_util_hook(cpu);
2292
2293 kfree(all_cpu_data[cpu]);
2294 all_cpu_data[cpu] = NULL;
2295 }
2296 }
2297 put_online_cpus();
ee8df89a 2298 intel_pstate_driver = NULL;
fb1fe104
RW		 2299}
2300
ee8df89a 2301static int intel_pstate_register_driver(struct cpufreq_driver *driver)
fb1fe104
RW		 2302{
2303 int ret;
2304
c5a2ee7d
RW		 2305 memset(&global, 0, sizeof(global));
2306 global.max_perf_pct = 100;
c3a49c89 2307
ee8df89a 2308 intel_pstate_driver = driver;
fb1fe104
RW		 2309 ret = cpufreq_register_driver(intel_pstate_driver);
2310 if (ret) {
2311 intel_pstate_driver_cleanup();
2312 return ret;
2313 }
2314
c5a2ee7d
RW		 2315 global.min_perf_pct = min_perf_pct_min();
2316
8ca6ce37 2317 if (pid_in_use())
fb1fe104
RW		 2318 intel_pstate_debug_expose_params();
2319
2320 return 0;
2321}
2322
2323static int intel_pstate_unregister_driver(void)
2324{
2325 if (hwp_active)
2326 return -EBUSY;
2327
8ca6ce37 2328 if (pid_in_use())
fb1fe104
RW		 2329 intel_pstate_debug_hide_params();
2330
fb1fe104
RW		 2331 cpufreq_unregister_driver(intel_pstate_driver);
2332 intel_pstate_driver_cleanup();
2333
2334 return 0;
2335}
2336
2337static ssize_t intel_pstate_show_status(char *buf)
2338{
ee8df89a 2339 if (!intel_pstate_driver)
fb1fe104
RW		 2340 return sprintf(buf, "off\n");
2341
2342 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2343 "active" : "passive");
2344}
2345
2346static int intel_pstate_update_status(const char *buf, size_t size)
2347{
2348 int ret;
2349
2350 if (size == 3 && !strncmp(buf, "off", size))
ee8df89a 2351 return intel_pstate_driver ?
fb1fe104
RW		 2352 intel_pstate_unregister_driver() : -EINVAL;
2353
2354 if (size == 6 && !strncmp(buf, "active", size)) {
ee8df89a 2355 if (intel_pstate_driver) {
fb1fe104
RW		 2356 if (intel_pstate_driver == &intel_pstate)
2357 return 0;
2358
2359 ret = intel_pstate_unregister_driver();
2360 if (ret)
2361 return ret;
2362 }
2363
ee8df89a 2364 return intel_pstate_register_driver(&intel_pstate);
fb1fe104
RW		 2365 }
2366
2367 if (size == 7 && !strncmp(buf, "passive", size)) {
ee8df89a 2368 if (intel_pstate_driver) {
0042b2c0 2369 if (intel_pstate_driver == &intel_cpufreq)
fb1fe104
RW		 2370 return 0;
2371
2372 ret = intel_pstate_unregister_driver();
2373 if (ret)
2374 return ret;
2375 }
2376
ee8df89a 2377 return intel_pstate_register_driver(&intel_cpufreq);
fb1fe104
RW		 2378 }
2379
2380 return -EINVAL;
2381}
2382
eed43609
JZ		 2383static int no_load __initdata;
2384static int no_hwp __initdata;
2385static int hwp_only __initdata;
29327c84 2386static unsigned int force_load __initdata;
6be26498 2387
29327c84 2388static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 2389{
016c8150 2390 if (!pstate_funcs.get_max() ||
c410833a
SK		 2391 !pstate_funcs.get_min() ||
2392 !pstate_funcs.get_turbo())
b563b4e3
DB		 2393 return -ENODEV;
2394
b563b4e3
DB		 2395 return 0;
2396}
016c8150 2397
7f7a516e
SP		 2398#ifdef CONFIG_ACPI
2399static void intel_pstate_use_acpi_profile(void)
2400{
55395345
RW		 2401 switch (acpi_gbl_FADT.preferred_profile) {
2402 case PM_MOBILE:
2403 case PM_TABLET:
2404 case PM_APPLIANCE_PC:
2405 case PM_DESKTOP:
2406 case PM_WORKSTATION:
67dd9bf4 2407 pstate_funcs.update_util = intel_pstate_update_util;
55395345 2408 }
7f7a516e
SP		 2409}
2410#else
2411static void intel_pstate_use_acpi_profile(void)
2412{
2413}
2414#endif
2415
29327c84 2416static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 2417{
2418 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 2419 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 2420 pstate_funcs.get_min = funcs->get_min;
2421 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 2422 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 2423 pstate_funcs.get_val = funcs->get_val;
007bea09 2424 pstate_funcs.get_vid = funcs->get_vid;
67dd9bf4 2425 pstate_funcs.update_util = funcs->update_util;
6e34e1f2 2426 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
157386b6 2427
7f7a516e 2428 intel_pstate_use_acpi_profile();
016c8150
DB		 2429}
2430
9522a2ff 2431#ifdef CONFIG_ACPI
fbbcdc07 2432
29327c84 2433static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 2434{
2435 int i;
2436
2437 for_each_possible_cpu(i) {
2438 acpi_status status;
2439 union acpi_object *pss;
2440 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2441 struct acpi_processor *pr = per_cpu(processors, i);
2442
2443 if (!pr)
2444 continue;
2445
2446 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2447 if (ACPI_FAILURE(status))
2448 continue;
2449
2450 pss = buffer.pointer;
2451 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2452 kfree(pss);
2453 return false;
2454 }
2455
2456 kfree(pss);
2457 }
2458
2459 return true;
2460}
2461
29327c84 2462static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 2463{
2464 int i;
2465
2466 for_each_possible_cpu(i) {
2467 struct acpi_processor *pr = per_cpu(processors, i);
2468
2469 if (!pr)
2470 continue;
2471 if (acpi_has_method(pr->handle, "_PPC"))
2472 return true;
2473 }
2474 return false;
2475}
2476
2477enum {
2478 PSS,
2479 PPC,
2480};
2481
fbbcdc07
AH		 2482struct hw_vendor_info {
2483 u16 valid;
2484 char oem_id[ACPI_OEM_ID_SIZE];
2485 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
966916ea 2486 int oem_pwr_table;
fbbcdc07
AH		 2487};
2488
2489/* Hardware vendor-specific info that has its own power management modes */
29327c84 2490static struct hw_vendor_info vendor_info[] __initdata = {
966916ea 2491 {1, "HP ", "ProLiant", PSS},
2492 {1, "ORACLE", "X4-2 ", PPC},
2493 {1, "ORACLE", "X4-2L ", PPC},
2494 {1, "ORACLE", "X4-2B ", PPC},
2495 {1, "ORACLE", "X3-2 ", PPC},
2496 {1, "ORACLE", "X3-2L ", PPC},
2497 {1, "ORACLE", "X3-2B ", PPC},
2498 {1, "ORACLE", "X4470M2 ", PPC},
2499 {1, "ORACLE", "X4270M3 ", PPC},
2500 {1, "ORACLE", "X4270M2 ", PPC},
2501 {1, "ORACLE", "X4170M2 ", PPC},
5aecc3c8
EZ		 2502 {1, "ORACLE", "X4170 M3", PPC},
2503 {1, "ORACLE", "X4275 M3", PPC},
2504 {1, "ORACLE", "X6-2 ", PPC},
2505 {1, "ORACLE", "Sudbury ", PPC},
fbbcdc07
AH		 2506 {0, "", ""},
2507};
2508
29327c84 2509static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07
AH		 2510{
2511 struct acpi_table_header hdr;
2512 struct hw_vendor_info *v_info;
2f86dc4c
DB		 2513 const struct x86_cpu_id *id;
2514 u64 misc_pwr;
2515
2516 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2517 if (id) {
2518 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2519 if ( misc_pwr & (1 << 8))
2520 return true;
2521 }
fbbcdc07 2522
c410833a
SK		 2523 if (acpi_disabled ||
2524 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
fbbcdc07
AH		 2525 return false;
2526
2527 for (v_info = vendor_info; v_info->valid; v_info++) {
c410833a 2528 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
966916ea 2529 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2530 ACPI_OEM_TABLE_ID_SIZE))
2531 switch (v_info->oem_pwr_table) {
2532 case PSS:
2533 return intel_pstate_no_acpi_pss();
2534 case PPC:
aa4ea34d
EZ		 2535 return intel_pstate_has_acpi_ppc() &&
2536 (!force_load);
966916ea 2537 }
fbbcdc07
AH		 2538 }
2539
2540 return false;
2541}
d0ea59e1
RW		 2542
2543static void intel_pstate_request_control_from_smm(void)
2544{
2545 /*
2546 * It may be unsafe to request P-states control from SMM if _PPC support
2547 * has not been enabled.
2548 */
2549 if (acpi_ppc)
2550 acpi_processor_pstate_control();
2551}
fbbcdc07
AH		 2552#else /* CONFIG_ACPI not enabled */
2553static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 2554static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 2555static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 2556#endif /* CONFIG_ACPI */
2557
7791e4aa
SP		 2558static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2559 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2560 {}
2561};
2562
93f0822d
DB		 2563static int __init intel_pstate_init(void)
2564{
eb5139d1 2565 int rc;
93f0822d 2566
6be26498
DB		 2567 if (no_load)
2568 return -ENODEV;
2569
eb5139d1 2570 if (x86_match_cpu(hwp_support_ids)) {
2f49afc2 2571 copy_cpu_funcs(&core_funcs);
eb5139d1 2572 if (no_hwp) {
67dd9bf4 2573 pstate_funcs.update_util = intel_pstate_update_util;
eb5139d1
RW		 2574 } else {
2575 hwp_active++;
2576 intel_pstate.attr = hwp_cpufreq_attrs;
2577 goto hwp_cpu_matched;
2578 }
2579 } else {
2580 const struct x86_cpu_id *id;
7791e4aa 2581
eb5139d1
RW		 2582 id = x86_match_cpu(intel_pstate_cpu_ids);
2583 if (!id)
2584 return -ENODEV;
93f0822d 2585
2f49afc2 2586 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
eb5139d1 2587 }
016c8150 2588
b563b4e3
DB		 2589 if (intel_pstate_msrs_not_valid())
2590 return -ENODEV;
2591
7791e4aa
SP		 2592hwp_cpu_matched:
2593 /*
2594 * The Intel pstate driver will be ignored if the platform
2595 * firmware has its own power management modes.
2596 */
2597 if (intel_pstate_platform_pwr_mgmt_exists())
2598 return -ENODEV;
2599
fb1fe104
RW		 2600 if (!hwp_active && hwp_only)
2601 return -ENOTSUPP;
2602
4836df17 2603 pr_info("Intel P-state driver initializing\n");
93f0822d 2604
b57ffac5 2605 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB		 2606 if (!all_cpu_data)
2607 return -ENOMEM;
93f0822d 2608
d0ea59e1
RW		 2609 intel_pstate_request_control_from_smm();
2610
93f0822d 2611 intel_pstate_sysfs_expose_params();
b69880f9 2612
0c30b65b 2613 mutex_lock(&intel_pstate_driver_lock);
ee8df89a 2614 rc = intel_pstate_register_driver(default_driver);
0c30b65b 2615 mutex_unlock(&intel_pstate_driver_lock);
fb1fe104
RW		 2616 if (rc)
2617 return rc;
366430b5 2618
7791e4aa 2619 if (hwp_active)
4836df17 2620 pr_info("HWP enabled\n");
7791e4aa 2621
fb1fe104 2622 return 0;
93f0822d
DB		 2623}
2624device_initcall(intel_pstate_init);
2625
6be26498
DB		 2626static int __init intel_pstate_setup(char *str)
2627{
2628 if (!str)
2629 return -EINVAL;
2630
001c76f0 2631 if (!strcmp(str, "disable")) {
6be26498 2632 no_load = 1;
001c76f0
RW		 2633 } else if (!strcmp(str, "passive")) {
2634 pr_info("Passive mode enabled\n");
ee8df89a 2635 default_driver = &intel_cpufreq;
001c76f0
RW		 2636 no_hwp = 1;
2637 }
539342f6 2638 if (!strcmp(str, "no_hwp")) {
4836df17 2639 pr_info("HWP disabled\n");
2f86dc4c 2640 no_hwp = 1;
539342f6 2641 }
aa4ea34d
EZ		 2642 if (!strcmp(str, "force"))
2643 force_load = 1;
d64c3b0b
KCA		 2644 if (!strcmp(str, "hwp_only"))
2645 hwp_only = 1;
eae48f04
SP		 2646 if (!strcmp(str, "per_cpu_perf_limits"))
2647 per_cpu_limits = true;
9522a2ff
SP		 2648
2649#ifdef CONFIG_ACPI
2650 if (!strcmp(str, "support_acpi_ppc"))
2651 acpi_ppc = true;
2652#endif
2653
6be26498
DB		 2654 return 0;
2655}
2656early_param("intel_pstate", intel_pstate_setup);
2657
93f0822d
DB		 2658MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2659MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2660MODULE_LICENSE("GPL");
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