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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
93f0822d DB |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include <asm/div64.h> | |
32 | #include <asm/msr.h> | |
33 | #include <asm/cpu_device_id.h> | |
34 | ||
61d8d2ab DB |
35 | #define BYT_RATIOS 0x66a |
36 | #define BYT_VIDS 0x66b | |
37 | #define BYT_TURBO_RATIOS 0x66c | |
21855ff5 | 38 | #define BYT_TURBO_VIDS 0x66d |
61d8d2ab | 39 | |
f0fe3cd7 | 40 | #define FRAC_BITS 8 |
93f0822d DB |
41 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
42 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 43 | |
93f0822d DB |
44 | |
45 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
46 | { | |
47 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
48 | } | |
49 | ||
50 | static inline int32_t div_fp(int32_t x, int32_t y) | |
51 | { | |
fa30dff9 | 52 | return div_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
53 | } |
54 | ||
d022a65e DB |
55 | static inline int ceiling_fp(int32_t x) |
56 | { | |
57 | int mask, ret; | |
58 | ||
59 | ret = fp_toint(x); | |
60 | mask = (1 << FRAC_BITS) - 1; | |
61 | if (x & mask) | |
62 | ret += 1; | |
63 | return ret; | |
64 | } | |
65 | ||
93f0822d | 66 | struct sample { |
d253d2a5 | 67 | int32_t core_pct_busy; |
93f0822d DB |
68 | u64 aperf; |
69 | u64 mperf; | |
70 | int freq; | |
c4ee841f | 71 | ktime_t time; |
93f0822d DB |
72 | }; |
73 | ||
74 | struct pstate_data { | |
75 | int current_pstate; | |
76 | int min_pstate; | |
77 | int max_pstate; | |
b27580b0 | 78 | int scaling; |
93f0822d DB |
79 | int turbo_pstate; |
80 | }; | |
81 | ||
007bea09 | 82 | struct vid_data { |
21855ff5 DB |
83 | int min; |
84 | int max; | |
85 | int turbo; | |
007bea09 DB |
86 | int32_t ratio; |
87 | }; | |
88 | ||
93f0822d DB |
89 | struct _pid { |
90 | int setpoint; | |
91 | int32_t integral; | |
92 | int32_t p_gain; | |
93 | int32_t i_gain; | |
94 | int32_t d_gain; | |
95 | int deadband; | |
d253d2a5 | 96 | int32_t last_err; |
93f0822d DB |
97 | }; |
98 | ||
99 | struct cpudata { | |
100 | int cpu; | |
101 | ||
93f0822d DB |
102 | struct timer_list timer; |
103 | ||
93f0822d | 104 | struct pstate_data pstate; |
007bea09 | 105 | struct vid_data vid; |
93f0822d | 106 | struct _pid pid; |
93f0822d | 107 | |
c4ee841f | 108 | ktime_t last_sample_time; |
93f0822d DB |
109 | u64 prev_aperf; |
110 | u64 prev_mperf; | |
d37e2b76 | 111 | struct sample sample; |
93f0822d DB |
112 | }; |
113 | ||
114 | static struct cpudata **all_cpu_data; | |
115 | struct pstate_adjust_policy { | |
116 | int sample_rate_ms; | |
117 | int deadband; | |
118 | int setpoint; | |
119 | int p_gain_pct; | |
120 | int d_gain_pct; | |
121 | int i_gain_pct; | |
122 | }; | |
123 | ||
016c8150 DB |
124 | struct pstate_funcs { |
125 | int (*get_max)(void); | |
126 | int (*get_min)(void); | |
127 | int (*get_turbo)(void); | |
b27580b0 | 128 | int (*get_scaling)(void); |
007bea09 DB |
129 | void (*set)(struct cpudata*, int pstate); |
130 | void (*get_vid)(struct cpudata *); | |
93f0822d DB |
131 | }; |
132 | ||
016c8150 DB |
133 | struct cpu_defaults { |
134 | struct pstate_adjust_policy pid_policy; | |
135 | struct pstate_funcs funcs; | |
93f0822d DB |
136 | }; |
137 | ||
016c8150 DB |
138 | static struct pstate_adjust_policy pid_params; |
139 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 140 | static int hwp_active; |
016c8150 | 141 | |
93f0822d DB |
142 | struct perf_limits { |
143 | int no_turbo; | |
dd5fbf70 | 144 | int turbo_disabled; |
93f0822d DB |
145 | int max_perf_pct; |
146 | int min_perf_pct; | |
147 | int32_t max_perf; | |
148 | int32_t min_perf; | |
d8f469e9 DB |
149 | int max_policy_pct; |
150 | int max_sysfs_pct; | |
93f0822d DB |
151 | }; |
152 | ||
153 | static struct perf_limits limits = { | |
154 | .no_turbo = 0, | |
4521e1a0 | 155 | .turbo_disabled = 0, |
93f0822d DB |
156 | .max_perf_pct = 100, |
157 | .max_perf = int_tofp(1), | |
158 | .min_perf_pct = 0, | |
159 | .min_perf = 0, | |
d8f469e9 DB |
160 | .max_policy_pct = 100, |
161 | .max_sysfs_pct = 100, | |
93f0822d DB |
162 | }; |
163 | ||
164 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
c410833a | 165 | int deadband, int integral) { |
93f0822d DB |
166 | pid->setpoint = setpoint; |
167 | pid->deadband = deadband; | |
168 | pid->integral = int_tofp(integral); | |
d98d099b | 169 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
170 | } |
171 | ||
172 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
173 | { | |
174 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
175 | } | |
176 | ||
177 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
178 | { | |
179 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
180 | } | |
181 | ||
182 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
183 | { | |
93f0822d DB |
184 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
185 | } | |
186 | ||
d253d2a5 | 187 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 188 | { |
d253d2a5 | 189 | signed int result; |
93f0822d DB |
190 | int32_t pterm, dterm, fp_error; |
191 | int32_t integral_limit; | |
192 | ||
d253d2a5 | 193 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 194 | |
d253d2a5 | 195 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
196 | return 0; |
197 | ||
198 | pterm = mul_fp(pid->p_gain, fp_error); | |
199 | ||
200 | pid->integral += fp_error; | |
201 | ||
e0d4c8f8 KCA |
202 | /* |
203 | * We limit the integral here so that it will never | |
204 | * get higher than 30. This prevents it from becoming | |
205 | * too large an input over long periods of time and allows | |
206 | * it to get factored out sooner. | |
207 | * | |
208 | * The value of 30 was chosen through experimentation. | |
209 | */ | |
93f0822d DB |
210 | integral_limit = int_tofp(30); |
211 | if (pid->integral > integral_limit) | |
212 | pid->integral = integral_limit; | |
213 | if (pid->integral < -integral_limit) | |
214 | pid->integral = -integral_limit; | |
215 | ||
d253d2a5 BS |
216 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
217 | pid->last_err = fp_error; | |
93f0822d DB |
218 | |
219 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 220 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
221 | return (signed int)fp_toint(result); |
222 | } | |
223 | ||
224 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
225 | { | |
016c8150 DB |
226 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
227 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
228 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 229 | |
2d8d1f18 | 230 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
231 | } |
232 | ||
93f0822d DB |
233 | static inline void intel_pstate_reset_all_pid(void) |
234 | { | |
235 | unsigned int cpu; | |
845c1cbe | 236 | |
93f0822d DB |
237 | for_each_online_cpu(cpu) { |
238 | if (all_cpu_data[cpu]) | |
239 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
240 | } | |
241 | } | |
242 | ||
4521e1a0 GM |
243 | static inline void update_turbo_state(void) |
244 | { | |
245 | u64 misc_en; | |
246 | struct cpudata *cpu; | |
247 | ||
248 | cpu = all_cpu_data[0]; | |
249 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
250 | limits.turbo_disabled = | |
251 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || | |
252 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
253 | } | |
254 | ||
2f86dc4c DB |
255 | #define PCT_TO_HWP(x) (x * 255 / 100) |
256 | static void intel_pstate_hwp_set(void) | |
257 | { | |
258 | int min, max, cpu; | |
259 | u64 value, freq; | |
260 | ||
261 | get_online_cpus(); | |
262 | ||
263 | for_each_online_cpu(cpu) { | |
264 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
265 | min = PCT_TO_HWP(limits.min_perf_pct); | |
266 | value &= ~HWP_MIN_PERF(~0L); | |
267 | value |= HWP_MIN_PERF(min); | |
268 | ||
269 | max = PCT_TO_HWP(limits.max_perf_pct); | |
270 | if (limits.no_turbo) { | |
271 | rdmsrl( MSR_HWP_CAPABILITIES, freq); | |
272 | max = HWP_GUARANTEED_PERF(freq); | |
273 | } | |
274 | ||
275 | value &= ~HWP_MAX_PERF(~0L); | |
276 | value |= HWP_MAX_PERF(max); | |
277 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
278 | } | |
279 | ||
280 | put_online_cpus(); | |
281 | } | |
282 | ||
93f0822d DB |
283 | /************************** debugfs begin ************************/ |
284 | static int pid_param_set(void *data, u64 val) | |
285 | { | |
286 | *(u32 *)data = val; | |
287 | intel_pstate_reset_all_pid(); | |
288 | return 0; | |
289 | } | |
845c1cbe | 290 | |
93f0822d DB |
291 | static int pid_param_get(void *data, u64 *val) |
292 | { | |
293 | *val = *(u32 *)data; | |
294 | return 0; | |
295 | } | |
2d8d1f18 | 296 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
297 | |
298 | struct pid_param { | |
299 | char *name; | |
300 | void *value; | |
301 | }; | |
302 | ||
303 | static struct pid_param pid_files[] = { | |
016c8150 DB |
304 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
305 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
306 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
307 | {"deadband", &pid_params.deadband}, | |
308 | {"setpoint", &pid_params.setpoint}, | |
309 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
310 | {NULL, NULL} |
311 | }; | |
312 | ||
317dd50e | 313 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 314 | { |
317dd50e | 315 | struct dentry *debugfs_parent; |
93f0822d DB |
316 | int i = 0; |
317 | ||
2f86dc4c DB |
318 | if (hwp_active) |
319 | return; | |
93f0822d DB |
320 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
321 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
322 | return; | |
323 | while (pid_files[i].name) { | |
324 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
325 | debugfs_parent, pid_files[i].value, |
326 | &fops_pid_param); | |
93f0822d DB |
327 | i++; |
328 | } | |
329 | } | |
330 | ||
331 | /************************** debugfs end ************************/ | |
332 | ||
333 | /************************** sysfs begin ************************/ | |
334 | #define show_one(file_name, object) \ | |
335 | static ssize_t show_##file_name \ | |
336 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
337 | { \ | |
338 | return sprintf(buf, "%u\n", limits.object); \ | |
339 | } | |
340 | ||
4521e1a0 GM |
341 | static ssize_t show_no_turbo(struct kobject *kobj, |
342 | struct attribute *attr, char *buf) | |
343 | { | |
344 | ssize_t ret; | |
345 | ||
346 | update_turbo_state(); | |
347 | if (limits.turbo_disabled) | |
348 | ret = sprintf(buf, "%u\n", limits.turbo_disabled); | |
349 | else | |
350 | ret = sprintf(buf, "%u\n", limits.no_turbo); | |
351 | ||
352 | return ret; | |
353 | } | |
354 | ||
93f0822d | 355 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 356 | const char *buf, size_t count) |
93f0822d DB |
357 | { |
358 | unsigned int input; | |
359 | int ret; | |
845c1cbe | 360 | |
93f0822d DB |
361 | ret = sscanf(buf, "%u", &input); |
362 | if (ret != 1) | |
363 | return -EINVAL; | |
4521e1a0 GM |
364 | |
365 | update_turbo_state(); | |
dd5fbf70 DB |
366 | if (limits.turbo_disabled) { |
367 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); | |
4521e1a0 | 368 | return -EPERM; |
dd5fbf70 | 369 | } |
2f86dc4c | 370 | |
4521e1a0 GM |
371 | limits.no_turbo = clamp_t(int, input, 0, 1); |
372 | ||
2f86dc4c DB |
373 | if (hwp_active) |
374 | intel_pstate_hwp_set(); | |
375 | ||
93f0822d DB |
376 | return count; |
377 | } | |
378 | ||
379 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 380 | const char *buf, size_t count) |
93f0822d DB |
381 | { |
382 | unsigned int input; | |
383 | int ret; | |
845c1cbe | 384 | |
93f0822d DB |
385 | ret = sscanf(buf, "%u", &input); |
386 | if (ret != 1) | |
387 | return -EINVAL; | |
388 | ||
d8f469e9 DB |
389 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
390 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d | 391 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
845c1cbe | 392 | |
2f86dc4c DB |
393 | if (hwp_active) |
394 | intel_pstate_hwp_set(); | |
93f0822d DB |
395 | return count; |
396 | } | |
397 | ||
398 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 399 | const char *buf, size_t count) |
93f0822d DB |
400 | { |
401 | unsigned int input; | |
402 | int ret; | |
845c1cbe | 403 | |
93f0822d DB |
404 | ret = sscanf(buf, "%u", &input); |
405 | if (ret != 1) | |
406 | return -EINVAL; | |
407 | limits.min_perf_pct = clamp_t(int, input, 0 , 100); | |
408 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
409 | ||
2f86dc4c DB |
410 | if (hwp_active) |
411 | intel_pstate_hwp_set(); | |
93f0822d DB |
412 | return count; |
413 | } | |
414 | ||
93f0822d DB |
415 | show_one(max_perf_pct, max_perf_pct); |
416 | show_one(min_perf_pct, min_perf_pct); | |
417 | ||
418 | define_one_global_rw(no_turbo); | |
419 | define_one_global_rw(max_perf_pct); | |
420 | define_one_global_rw(min_perf_pct); | |
421 | ||
422 | static struct attribute *intel_pstate_attributes[] = { | |
423 | &no_turbo.attr, | |
424 | &max_perf_pct.attr, | |
425 | &min_perf_pct.attr, | |
426 | NULL | |
427 | }; | |
428 | ||
429 | static struct attribute_group intel_pstate_attr_group = { | |
430 | .attrs = intel_pstate_attributes, | |
431 | }; | |
93f0822d | 432 | |
317dd50e | 433 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 434 | { |
317dd50e | 435 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
436 | int rc; |
437 | ||
438 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
439 | &cpu_subsys.dev_root->kobj); | |
440 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 441 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
442 | BUG_ON(rc); |
443 | } | |
93f0822d | 444 | /************************** sysfs end ************************/ |
2f86dc4c DB |
445 | |
446 | static void intel_pstate_hwp_enable(void) | |
447 | { | |
448 | hwp_active++; | |
449 | pr_info("intel_pstate HWP enabled\n"); | |
450 | ||
451 | wrmsrl( MSR_PM_ENABLE, 0x1); | |
452 | } | |
453 | ||
19e77c28 DB |
454 | static int byt_get_min_pstate(void) |
455 | { | |
456 | u64 value; | |
845c1cbe | 457 | |
19e77c28 | 458 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 459 | return (value >> 8) & 0x7F; |
19e77c28 DB |
460 | } |
461 | ||
462 | static int byt_get_max_pstate(void) | |
463 | { | |
464 | u64 value; | |
845c1cbe | 465 | |
19e77c28 | 466 | rdmsrl(BYT_RATIOS, value); |
c16ed060 | 467 | return (value >> 16) & 0x7F; |
19e77c28 | 468 | } |
93f0822d | 469 | |
61d8d2ab DB |
470 | static int byt_get_turbo_pstate(void) |
471 | { | |
472 | u64 value; | |
845c1cbe | 473 | |
61d8d2ab | 474 | rdmsrl(BYT_TURBO_RATIOS, value); |
c16ed060 | 475 | return value & 0x7F; |
61d8d2ab DB |
476 | } |
477 | ||
007bea09 DB |
478 | static void byt_set_pstate(struct cpudata *cpudata, int pstate) |
479 | { | |
480 | u64 val; | |
481 | int32_t vid_fp; | |
482 | u32 vid; | |
483 | ||
484 | val = pstate << 8; | |
dd5fbf70 | 485 | if (limits.no_turbo && !limits.turbo_disabled) |
007bea09 DB |
486 | val |= (u64)1 << 32; |
487 | ||
488 | vid_fp = cpudata->vid.min + mul_fp( | |
489 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
490 | cpudata->vid.ratio); | |
491 | ||
492 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 493 | vid = ceiling_fp(vid_fp); |
007bea09 | 494 | |
21855ff5 DB |
495 | if (pstate > cpudata->pstate.max_pstate) |
496 | vid = cpudata->vid.turbo; | |
497 | ||
007bea09 DB |
498 | val |= vid; |
499 | ||
500 | wrmsrl(MSR_IA32_PERF_CTL, val); | |
501 | } | |
502 | ||
b27580b0 DB |
503 | #define BYT_BCLK_FREQS 5 |
504 | static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800}; | |
505 | ||
506 | static int byt_get_scaling(void) | |
507 | { | |
508 | u64 value; | |
509 | int i; | |
510 | ||
511 | rdmsrl(MSR_FSB_FREQ, value); | |
512 | i = value & 0x3; | |
513 | ||
514 | BUG_ON(i > BYT_BCLK_FREQS); | |
515 | ||
516 | return byt_freq_table[i] * 100; | |
517 | } | |
518 | ||
007bea09 DB |
519 | static void byt_get_vid(struct cpudata *cpudata) |
520 | { | |
521 | u64 value; | |
522 | ||
523 | rdmsrl(BYT_VIDS, value); | |
c16ed060 DB |
524 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
525 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
526 | cpudata->vid.ratio = div_fp( |
527 | cpudata->vid.max - cpudata->vid.min, | |
528 | int_tofp(cpudata->pstate.max_pstate - | |
529 | cpudata->pstate.min_pstate)); | |
21855ff5 DB |
530 | |
531 | rdmsrl(BYT_TURBO_VIDS, value); | |
532 | cpudata->vid.turbo = value & 0x7f; | |
007bea09 DB |
533 | } |
534 | ||
016c8150 | 535 | static int core_get_min_pstate(void) |
93f0822d DB |
536 | { |
537 | u64 value; | |
845c1cbe | 538 | |
05e99c8c | 539 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
540 | return (value >> 40) & 0xFF; |
541 | } | |
542 | ||
016c8150 | 543 | static int core_get_max_pstate(void) |
93f0822d DB |
544 | { |
545 | u64 value; | |
845c1cbe | 546 | |
05e99c8c | 547 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
548 | return (value >> 8) & 0xFF; |
549 | } | |
550 | ||
016c8150 | 551 | static int core_get_turbo_pstate(void) |
93f0822d DB |
552 | { |
553 | u64 value; | |
554 | int nont, ret; | |
845c1cbe | 555 | |
05e99c8c | 556 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 557 | nont = core_get_max_pstate(); |
285cb990 | 558 | ret = (value) & 255; |
93f0822d DB |
559 | if (ret <= nont) |
560 | ret = nont; | |
561 | return ret; | |
562 | } | |
563 | ||
b27580b0 DB |
564 | static inline int core_get_scaling(void) |
565 | { | |
566 | return 100000; | |
567 | } | |
568 | ||
007bea09 | 569 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
570 | { |
571 | u64 val; | |
572 | ||
573 | val = pstate << 8; | |
dd5fbf70 | 574 | if (limits.no_turbo && !limits.turbo_disabled) |
016c8150 DB |
575 | val |= (u64)1 << 32; |
576 | ||
bb18008f | 577 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
578 | } |
579 | ||
580 | static struct cpu_defaults core_params = { | |
581 | .pid_policy = { | |
582 | .sample_rate_ms = 10, | |
583 | .deadband = 0, | |
584 | .setpoint = 97, | |
585 | .p_gain_pct = 20, | |
586 | .d_gain_pct = 0, | |
587 | .i_gain_pct = 0, | |
588 | }, | |
589 | .funcs = { | |
590 | .get_max = core_get_max_pstate, | |
591 | .get_min = core_get_min_pstate, | |
592 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 593 | .get_scaling = core_get_scaling, |
016c8150 DB |
594 | .set = core_set_pstate, |
595 | }, | |
596 | }; | |
597 | ||
19e77c28 DB |
598 | static struct cpu_defaults byt_params = { |
599 | .pid_policy = { | |
600 | .sample_rate_ms = 10, | |
601 | .deadband = 0, | |
602 | .setpoint = 97, | |
603 | .p_gain_pct = 14, | |
604 | .d_gain_pct = 0, | |
605 | .i_gain_pct = 4, | |
606 | }, | |
607 | .funcs = { | |
608 | .get_max = byt_get_max_pstate, | |
609 | .get_min = byt_get_min_pstate, | |
61d8d2ab | 610 | .get_turbo = byt_get_turbo_pstate, |
007bea09 | 611 | .set = byt_set_pstate, |
b27580b0 | 612 | .get_scaling = byt_get_scaling, |
007bea09 | 613 | .get_vid = byt_get_vid, |
19e77c28 DB |
614 | }, |
615 | }; | |
616 | ||
93f0822d DB |
617 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
618 | { | |
619 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 620 | int max_perf_adj; |
93f0822d | 621 | int min_perf; |
845c1cbe | 622 | |
4521e1a0 | 623 | if (limits.no_turbo || limits.turbo_disabled) |
93f0822d DB |
624 | max_perf = cpu->pstate.max_pstate; |
625 | ||
e0d4c8f8 KCA |
626 | /* |
627 | * performance can be limited by user through sysfs, by cpufreq | |
628 | * policy, or by cpu specific default values determined through | |
629 | * experimentation. | |
630 | */ | |
7244cb62 DB |
631 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
632 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
633 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
634 | ||
635 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
2d8d1f18 | 636 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
637 | } |
638 | ||
639 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) | |
640 | { | |
641 | int max_perf, min_perf; | |
642 | ||
4521e1a0 GM |
643 | update_turbo_state(); |
644 | ||
93f0822d DB |
645 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
646 | ||
647 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
648 | ||
649 | if (pstate == cpu->pstate.current_pstate) | |
650 | return; | |
651 | ||
b27580b0 | 652 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 653 | |
93f0822d | 654 | cpu->pstate.current_pstate = pstate; |
93f0822d | 655 | |
007bea09 | 656 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
657 | } |
658 | ||
93f0822d DB |
659 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
660 | { | |
016c8150 DB |
661 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
662 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
663 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
b27580b0 | 664 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 665 | |
007bea09 DB |
666 | if (pstate_funcs.get_vid) |
667 | pstate_funcs.get_vid(cpu); | |
d40a63c4 | 668 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
669 | } |
670 | ||
6b17ddb2 | 671 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 672 | { |
6b17ddb2 | 673 | struct sample *sample = &cpu->sample; |
bf810222 | 674 | int64_t core_pct; |
93f0822d | 675 | |
bf810222 | 676 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 677 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 678 | |
fcb6a15c | 679 | sample->freq = fp_toint( |
b27580b0 DB |
680 | mul_fp(int_tofp( |
681 | cpu->pstate.max_pstate * cpu->pstate.scaling / 100), | |
682 | core_pct)); | |
fcb6a15c | 683 | |
bf810222 | 684 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
685 | } |
686 | ||
687 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
688 | { | |
93f0822d | 689 | u64 aperf, mperf; |
4ab60c3f | 690 | unsigned long flags; |
93f0822d | 691 | |
4ab60c3f | 692 | local_irq_save(flags); |
93f0822d DB |
693 | rdmsrl(MSR_IA32_APERF, aperf); |
694 | rdmsrl(MSR_IA32_MPERF, mperf); | |
4ab60c3f | 695 | local_irq_restore(flags); |
b69880f9 | 696 | |
c4ee841f DB |
697 | cpu->last_sample_time = cpu->sample.time; |
698 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
699 | cpu->sample.aperf = aperf; |
700 | cpu->sample.mperf = mperf; | |
d37e2b76 DB |
701 | cpu->sample.aperf -= cpu->prev_aperf; |
702 | cpu->sample.mperf -= cpu->prev_mperf; | |
1abc4b20 | 703 | |
6b17ddb2 | 704 | intel_pstate_calc_busy(cpu); |
93f0822d | 705 | |
93f0822d DB |
706 | cpu->prev_aperf = aperf; |
707 | cpu->prev_mperf = mperf; | |
708 | } | |
709 | ||
2f86dc4c DB |
710 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
711 | { | |
712 | int delay; | |
713 | ||
714 | delay = msecs_to_jiffies(50); | |
715 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
716 | } | |
717 | ||
93f0822d DB |
718 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
719 | { | |
abf013bf | 720 | int delay; |
93f0822d | 721 | |
abf013bf | 722 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
723 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
724 | } | |
725 | ||
d253d2a5 | 726 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 727 | { |
c4ee841f DB |
728 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
729 | u32 duration_us; | |
730 | u32 sample_time; | |
93f0822d | 731 | |
e0d4c8f8 KCA |
732 | /* |
733 | * core_busy is the ratio of actual performance to max | |
734 | * max_pstate is the max non turbo pstate available | |
735 | * current_pstate was the pstate that was requested during | |
736 | * the last sample period. | |
737 | * | |
738 | * We normalize core_busy, which was our actual percent | |
739 | * performance to what we requested during the last sample | |
740 | * period. The result will be a percentage of busy at a | |
741 | * specified pstate. | |
742 | */ | |
d37e2b76 | 743 | core_busy = cpu->sample.core_pct_busy; |
2134ed4d | 744 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 745 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 746 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 747 | |
e0d4c8f8 KCA |
748 | /* |
749 | * Since we have a deferred timer, it will not fire unless | |
750 | * we are in C0. So, determine if the actual elapsed time | |
751 | * is significantly greater (3x) than our sample interval. If it | |
752 | * is, then we were idle for a long enough period of time | |
753 | * to adjust our busyness. | |
754 | */ | |
285cb990 | 755 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
c4ee841f | 756 | duration_us = (u32) ktime_us_delta(cpu->sample.time, |
c410833a | 757 | cpu->last_sample_time); |
c4ee841f DB |
758 | if (duration_us > sample_time * 3) { |
759 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 760 | int_tofp(duration_us)); |
c4ee841f DB |
761 | core_busy = mul_fp(core_busy, sample_ratio); |
762 | } | |
763 | ||
f0fe3cd7 | 764 | return core_busy; |
93f0822d DB |
765 | } |
766 | ||
767 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
768 | { | |
d253d2a5 | 769 | int32_t busy_scaled; |
93f0822d | 770 | struct _pid *pid; |
4b707c89 | 771 | signed int ctl; |
93f0822d DB |
772 | |
773 | pid = &cpu->pid; | |
774 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
775 | ||
776 | ctl = pid_calc(pid, busy_scaled); | |
777 | ||
4b707c89 SK |
778 | /* Negative values of ctl increase the pstate and vice versa */ |
779 | intel_pstate_set_pstate(cpu, cpu->pstate.current_pstate - ctl); | |
93f0822d DB |
780 | } |
781 | ||
2f86dc4c DB |
782 | static void intel_hwp_timer_func(unsigned long __data) |
783 | { | |
784 | struct cpudata *cpu = (struct cpudata *) __data; | |
785 | ||
786 | intel_pstate_sample(cpu); | |
787 | intel_hwp_set_sample_time(cpu); | |
788 | } | |
789 | ||
93f0822d DB |
790 | static void intel_pstate_timer_func(unsigned long __data) |
791 | { | |
792 | struct cpudata *cpu = (struct cpudata *) __data; | |
b69880f9 | 793 | struct sample *sample; |
93f0822d DB |
794 | |
795 | intel_pstate_sample(cpu); | |
b69880f9 | 796 | |
d37e2b76 | 797 | sample = &cpu->sample; |
b69880f9 | 798 | |
ca182aee | 799 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 DB |
800 | |
801 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
802 | fp_toint(intel_pstate_get_scaled_busy(cpu)), | |
803 | cpu->pstate.current_pstate, | |
804 | sample->mperf, | |
805 | sample->aperf, | |
b69880f9 DB |
806 | sample->freq); |
807 | ||
93f0822d DB |
808 | intel_pstate_set_sample_time(cpu); |
809 | } | |
810 | ||
811 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
812 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
813 | (unsigned long)&policy } | |
93f0822d DB |
814 | |
815 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
816 | ICPU(0x2a, core_params), |
817 | ICPU(0x2d, core_params), | |
19e77c28 | 818 | ICPU(0x37, byt_params), |
016c8150 DB |
819 | ICPU(0x3a, core_params), |
820 | ICPU(0x3c, core_params), | |
c7e241df | 821 | ICPU(0x3d, core_params), |
016c8150 DB |
822 | ICPU(0x3e, core_params), |
823 | ICPU(0x3f, core_params), | |
824 | ICPU(0x45, core_params), | |
825 | ICPU(0x46, core_params), | |
43f8a966 | 826 | ICPU(0x47, core_params), |
16405f98 | 827 | ICPU(0x4c, byt_params), |
7ab0256e | 828 | ICPU(0x4e, core_params), |
c7e241df DB |
829 | ICPU(0x4f, core_params), |
830 | ICPU(0x56, core_params), | |
93f0822d DB |
831 | {} |
832 | }; | |
833 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
834 | ||
2f86dc4c DB |
835 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
836 | ICPU(0x56, core_params), | |
837 | {} | |
838 | }; | |
839 | ||
93f0822d DB |
840 | static int intel_pstate_init_cpu(unsigned int cpunum) |
841 | { | |
93f0822d DB |
842 | struct cpudata *cpu; |
843 | ||
c0348717 DB |
844 | if (!all_cpu_data[cpunum]) |
845 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
846 | GFP_KERNEL); | |
93f0822d DB |
847 | if (!all_cpu_data[cpunum]) |
848 | return -ENOMEM; | |
849 | ||
850 | cpu = all_cpu_data[cpunum]; | |
851 | ||
93f0822d | 852 | cpu->cpu = cpunum; |
179e8471 | 853 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 854 | |
93f0822d | 855 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 856 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 857 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
858 | |
859 | if (!hwp_active) | |
860 | cpu->timer.function = intel_pstate_timer_func; | |
861 | else | |
862 | cpu->timer.function = intel_hwp_timer_func; | |
863 | ||
93f0822d | 864 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 865 | intel_pstate_sample(cpu); |
93f0822d DB |
866 | |
867 | add_timer_on(&cpu->timer, cpunum); | |
868 | ||
ce717613 | 869 | pr_debug("Intel pstate controlling: cpu %d\n", cpunum); |
93f0822d DB |
870 | |
871 | return 0; | |
872 | } | |
873 | ||
874 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
875 | { | |
876 | struct sample *sample; | |
877 | struct cpudata *cpu; | |
878 | ||
879 | cpu = all_cpu_data[cpu_num]; | |
880 | if (!cpu) | |
881 | return 0; | |
d37e2b76 | 882 | sample = &cpu->sample; |
93f0822d DB |
883 | return sample->freq; |
884 | } | |
885 | ||
886 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
887 | { | |
d3929b83 DB |
888 | if (!policy->cpuinfo.max_freq) |
889 | return -ENODEV; | |
890 | ||
93f0822d DB |
891 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { |
892 | limits.min_perf_pct = 100; | |
893 | limits.min_perf = int_tofp(1); | |
36b4bed5 | 894 | limits.max_policy_pct = 100; |
93f0822d DB |
895 | limits.max_perf_pct = 100; |
896 | limits.max_perf = int_tofp(1); | |
4521e1a0 | 897 | limits.no_turbo = 0; |
d1b68485 | 898 | return 0; |
93f0822d | 899 | } |
2f86dc4c | 900 | |
d1b68485 SP |
901 | limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
902 | limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100); | |
903 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
904 | ||
285cb990 | 905 | limits.max_policy_pct = (policy->max * 100) / policy->cpuinfo.max_freq; |
d8f469e9 DB |
906 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); |
907 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 908 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d | 909 | |
2f86dc4c DB |
910 | if (hwp_active) |
911 | intel_pstate_hwp_set(); | |
912 | ||
93f0822d DB |
913 | return 0; |
914 | } | |
915 | ||
916 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
917 | { | |
be49e346 | 918 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 919 | |
285cb990 | 920 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 921 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
922 | return -EINVAL; |
923 | ||
924 | return 0; | |
925 | } | |
926 | ||
bb18008f | 927 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 928 | { |
bb18008f DB |
929 | int cpu_num = policy->cpu; |
930 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 931 | |
bb18008f DB |
932 | pr_info("intel_pstate CPU %d exiting\n", cpu_num); |
933 | ||
c2294a2f | 934 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
935 | if (hwp_active) |
936 | return; | |
937 | ||
bb18008f | 938 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
939 | } |
940 | ||
2760984f | 941 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 942 | { |
93f0822d | 943 | struct cpudata *cpu; |
52e0a509 | 944 | int rc; |
93f0822d DB |
945 | |
946 | rc = intel_pstate_init_cpu(policy->cpu); | |
947 | if (rc) | |
948 | return rc; | |
949 | ||
950 | cpu = all_cpu_data[policy->cpu]; | |
951 | ||
dd5fbf70 | 952 | if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100) |
93f0822d DB |
953 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
954 | else | |
955 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
956 | ||
b27580b0 DB |
957 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
958 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
959 | |
960 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
961 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
962 | policy->cpuinfo.max_freq = | |
963 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
964 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
965 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
966 | ||
967 | return 0; | |
968 | } | |
969 | ||
970 | static struct cpufreq_driver intel_pstate_driver = { | |
971 | .flags = CPUFREQ_CONST_LOOPS, | |
972 | .verify = intel_pstate_verify_policy, | |
973 | .setpolicy = intel_pstate_set_policy, | |
974 | .get = intel_pstate_get, | |
975 | .init = intel_pstate_cpu_init, | |
bb18008f | 976 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 977 | .name = "intel_pstate", |
93f0822d DB |
978 | }; |
979 | ||
6be26498 | 980 | static int __initdata no_load; |
2f86dc4c | 981 | static int __initdata no_hwp; |
aa4ea34d | 982 | static unsigned int force_load; |
6be26498 | 983 | |
b563b4e3 DB |
984 | static int intel_pstate_msrs_not_valid(void) |
985 | { | |
986 | /* Check that all the msr's we are using are valid. */ | |
987 | u64 aperf, mperf, tmp; | |
988 | ||
989 | rdmsrl(MSR_IA32_APERF, aperf); | |
990 | rdmsrl(MSR_IA32_MPERF, mperf); | |
991 | ||
016c8150 | 992 | if (!pstate_funcs.get_max() || |
c410833a SK |
993 | !pstate_funcs.get_min() || |
994 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
995 | return -ENODEV; |
996 | ||
997 | rdmsrl(MSR_IA32_APERF, tmp); | |
998 | if (!(tmp - aperf)) | |
999 | return -ENODEV; | |
1000 | ||
1001 | rdmsrl(MSR_IA32_MPERF, tmp); | |
1002 | if (!(tmp - mperf)) | |
1003 | return -ENODEV; | |
1004 | ||
1005 | return 0; | |
1006 | } | |
016c8150 | 1007 | |
e0a261a2 | 1008 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1009 | { |
1010 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
1011 | pid_params.p_gain_pct = policy->p_gain_pct; | |
1012 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1013 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1014 | pid_params.deadband = policy->deadband; | |
1015 | pid_params.setpoint = policy->setpoint; | |
1016 | } | |
1017 | ||
e0a261a2 | 1018 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1019 | { |
1020 | pstate_funcs.get_max = funcs->get_max; | |
1021 | pstate_funcs.get_min = funcs->get_min; | |
1022 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1023 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 1024 | pstate_funcs.set = funcs->set; |
007bea09 | 1025 | pstate_funcs.get_vid = funcs->get_vid; |
016c8150 DB |
1026 | } |
1027 | ||
fbbcdc07 AH |
1028 | #if IS_ENABLED(CONFIG_ACPI) |
1029 | #include <acpi/processor.h> | |
1030 | ||
1031 | static bool intel_pstate_no_acpi_pss(void) | |
1032 | { | |
1033 | int i; | |
1034 | ||
1035 | for_each_possible_cpu(i) { | |
1036 | acpi_status status; | |
1037 | union acpi_object *pss; | |
1038 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1039 | struct acpi_processor *pr = per_cpu(processors, i); | |
1040 | ||
1041 | if (!pr) | |
1042 | continue; | |
1043 | ||
1044 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1045 | if (ACPI_FAILURE(status)) | |
1046 | continue; | |
1047 | ||
1048 | pss = buffer.pointer; | |
1049 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1050 | kfree(pss); | |
1051 | return false; | |
1052 | } | |
1053 | ||
1054 | kfree(pss); | |
1055 | } | |
1056 | ||
1057 | return true; | |
1058 | } | |
1059 | ||
966916ea | 1060 | static bool intel_pstate_has_acpi_ppc(void) |
1061 | { | |
1062 | int i; | |
1063 | ||
1064 | for_each_possible_cpu(i) { | |
1065 | struct acpi_processor *pr = per_cpu(processors, i); | |
1066 | ||
1067 | if (!pr) | |
1068 | continue; | |
1069 | if (acpi_has_method(pr->handle, "_PPC")) | |
1070 | return true; | |
1071 | } | |
1072 | return false; | |
1073 | } | |
1074 | ||
1075 | enum { | |
1076 | PSS, | |
1077 | PPC, | |
1078 | }; | |
1079 | ||
fbbcdc07 AH |
1080 | struct hw_vendor_info { |
1081 | u16 valid; | |
1082 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1083 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1084 | int oem_pwr_table; |
fbbcdc07 AH |
1085 | }; |
1086 | ||
1087 | /* Hardware vendor-specific info that has its own power management modes */ | |
1088 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1089 | {1, "HP ", "ProLiant", PSS}, |
1090 | {1, "ORACLE", "X4-2 ", PPC}, | |
1091 | {1, "ORACLE", "X4-2L ", PPC}, | |
1092 | {1, "ORACLE", "X4-2B ", PPC}, | |
1093 | {1, "ORACLE", "X3-2 ", PPC}, | |
1094 | {1, "ORACLE", "X3-2L ", PPC}, | |
1095 | {1, "ORACLE", "X3-2B ", PPC}, | |
1096 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1097 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1098 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1099 | {1, "ORACLE", "X4170M2 ", PPC}, | |
fbbcdc07 AH |
1100 | {0, "", ""}, |
1101 | }; | |
1102 | ||
1103 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1104 | { | |
1105 | struct acpi_table_header hdr; | |
1106 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1107 | const struct x86_cpu_id *id; |
1108 | u64 misc_pwr; | |
1109 | ||
1110 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1111 | if (id) { | |
1112 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1113 | if ( misc_pwr & (1 << 8)) | |
1114 | return true; | |
1115 | } | |
fbbcdc07 | 1116 | |
c410833a SK |
1117 | if (acpi_disabled || |
1118 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1119 | return false; |
1120 | ||
1121 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1122 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1123 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1124 | ACPI_OEM_TABLE_ID_SIZE)) | |
1125 | switch (v_info->oem_pwr_table) { | |
1126 | case PSS: | |
1127 | return intel_pstate_no_acpi_pss(); | |
1128 | case PPC: | |
aa4ea34d EZ |
1129 | return intel_pstate_has_acpi_ppc() && |
1130 | (!force_load); | |
966916ea | 1131 | } |
fbbcdc07 AH |
1132 | } |
1133 | ||
1134 | return false; | |
1135 | } | |
1136 | #else /* CONFIG_ACPI not enabled */ | |
1137 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1138 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1139 | #endif /* CONFIG_ACPI */ |
1140 | ||
93f0822d DB |
1141 | static int __init intel_pstate_init(void) |
1142 | { | |
907cc908 | 1143 | int cpu, rc = 0; |
93f0822d | 1144 | const struct x86_cpu_id *id; |
016c8150 | 1145 | struct cpu_defaults *cpu_info; |
2f86dc4c | 1146 | struct cpuinfo_x86 *c = &boot_cpu_data; |
93f0822d | 1147 | |
6be26498 DB |
1148 | if (no_load) |
1149 | return -ENODEV; | |
1150 | ||
93f0822d DB |
1151 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1152 | if (!id) | |
1153 | return -ENODEV; | |
1154 | ||
fbbcdc07 AH |
1155 | /* |
1156 | * The Intel pstate driver will be ignored if the platform | |
1157 | * firmware has its own power management modes. | |
1158 | */ | |
1159 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1160 | return -ENODEV; | |
1161 | ||
016c8150 DB |
1162 | cpu_info = (struct cpu_defaults *)id->driver_data; |
1163 | ||
1164 | copy_pid_params(&cpu_info->pid_policy); | |
1165 | copy_cpu_funcs(&cpu_info->funcs); | |
1166 | ||
b563b4e3 DB |
1167 | if (intel_pstate_msrs_not_valid()) |
1168 | return -ENODEV; | |
1169 | ||
93f0822d DB |
1170 | pr_info("Intel P-state driver initializing.\n"); |
1171 | ||
b57ffac5 | 1172 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1173 | if (!all_cpu_data) |
1174 | return -ENOMEM; | |
93f0822d | 1175 | |
2f86dc4c DB |
1176 | if (cpu_has(c,X86_FEATURE_HWP) && !no_hwp) |
1177 | intel_pstate_hwp_enable(); | |
1178 | ||
93f0822d DB |
1179 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1180 | if (rc) | |
1181 | goto out; | |
1182 | ||
1183 | intel_pstate_debug_expose_params(); | |
1184 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1185 | |
93f0822d DB |
1186 | return rc; |
1187 | out: | |
907cc908 DB |
1188 | get_online_cpus(); |
1189 | for_each_online_cpu(cpu) { | |
1190 | if (all_cpu_data[cpu]) { | |
1191 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1192 | kfree(all_cpu_data[cpu]); | |
1193 | } | |
1194 | } | |
1195 | ||
1196 | put_online_cpus(); | |
1197 | vfree(all_cpu_data); | |
93f0822d DB |
1198 | return -ENODEV; |
1199 | } | |
1200 | device_initcall(intel_pstate_init); | |
1201 | ||
6be26498 DB |
1202 | static int __init intel_pstate_setup(char *str) |
1203 | { | |
1204 | if (!str) | |
1205 | return -EINVAL; | |
1206 | ||
1207 | if (!strcmp(str, "disable")) | |
1208 | no_load = 1; | |
2f86dc4c DB |
1209 | if (!strcmp(str, "no_hwp")) |
1210 | no_hwp = 1; | |
aa4ea34d EZ |
1211 | if (!strcmp(str, "force")) |
1212 | force_load = 1; | |
6be26498 DB |
1213 | return 0; |
1214 | } | |
1215 | early_param("intel_pstate", intel_pstate_setup); | |
1216 | ||
93f0822d DB |
1217 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1218 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1219 | MODULE_LICENSE("GPL"); |