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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
d6472302 | 29 | #include <linux/vmalloc.h> |
93f0822d DB |
30 | #include <trace/events/power.h> |
31 | ||
32 | #include <asm/div64.h> | |
33 | #include <asm/msr.h> | |
34 | #include <asm/cpu_device_id.h> | |
64df1fdf | 35 | #include <asm/cpufeature.h> |
93f0822d | 36 | |
938d21a2 PL |
37 | #define ATOM_RATIOS 0x66a |
38 | #define ATOM_VIDS 0x66b | |
39 | #define ATOM_TURBO_RATIOS 0x66c | |
40 | #define ATOM_TURBO_VIDS 0x66d | |
61d8d2ab | 41 | |
f0fe3cd7 | 42 | #define FRAC_BITS 8 |
93f0822d DB |
43 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
44 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 45 | |
93f0822d DB |
46 | static inline int32_t mul_fp(int32_t x, int32_t y) |
47 | { | |
48 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
49 | } | |
50 | ||
7180dddf | 51 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 52 | { |
7180dddf | 53 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
54 | } |
55 | ||
d022a65e DB |
56 | static inline int ceiling_fp(int32_t x) |
57 | { | |
58 | int mask, ret; | |
59 | ||
60 | ret = fp_toint(x); | |
61 | mask = (1 << FRAC_BITS) - 1; | |
62 | if (x & mask) | |
63 | ret += 1; | |
64 | return ret; | |
65 | } | |
66 | ||
93f0822d | 67 | struct sample { |
d253d2a5 | 68 | int32_t core_pct_busy; |
157386b6 | 69 | int32_t busy_scaled; |
93f0822d DB |
70 | u64 aperf; |
71 | u64 mperf; | |
4055fad3 | 72 | u64 tsc; |
93f0822d | 73 | int freq; |
a4675fbc | 74 | u64 time; |
93f0822d DB |
75 | }; |
76 | ||
77 | struct pstate_data { | |
78 | int current_pstate; | |
79 | int min_pstate; | |
80 | int max_pstate; | |
3bcc6fa9 | 81 | int max_pstate_physical; |
b27580b0 | 82 | int scaling; |
93f0822d DB |
83 | int turbo_pstate; |
84 | }; | |
85 | ||
007bea09 | 86 | struct vid_data { |
21855ff5 DB |
87 | int min; |
88 | int max; | |
89 | int turbo; | |
007bea09 DB |
90 | int32_t ratio; |
91 | }; | |
92 | ||
93f0822d DB |
93 | struct _pid { |
94 | int setpoint; | |
95 | int32_t integral; | |
96 | int32_t p_gain; | |
97 | int32_t i_gain; | |
98 | int32_t d_gain; | |
99 | int deadband; | |
d253d2a5 | 100 | int32_t last_err; |
93f0822d DB |
101 | }; |
102 | ||
103 | struct cpudata { | |
104 | int cpu; | |
105 | ||
a4675fbc | 106 | struct update_util_data update_util; |
93f0822d | 107 | |
93f0822d | 108 | struct pstate_data pstate; |
007bea09 | 109 | struct vid_data vid; |
93f0822d | 110 | struct _pid pid; |
93f0822d | 111 | |
a4675fbc | 112 | u64 last_sample_time; |
93f0822d DB |
113 | u64 prev_aperf; |
114 | u64 prev_mperf; | |
4055fad3 | 115 | u64 prev_tsc; |
63d1d656 | 116 | u64 prev_cummulative_iowait; |
d37e2b76 | 117 | struct sample sample; |
93f0822d DB |
118 | }; |
119 | ||
120 | static struct cpudata **all_cpu_data; | |
121 | struct pstate_adjust_policy { | |
122 | int sample_rate_ms; | |
a4675fbc | 123 | s64 sample_rate_ns; |
93f0822d DB |
124 | int deadband; |
125 | int setpoint; | |
126 | int p_gain_pct; | |
127 | int d_gain_pct; | |
128 | int i_gain_pct; | |
129 | }; | |
130 | ||
016c8150 DB |
131 | struct pstate_funcs { |
132 | int (*get_max)(void); | |
3bcc6fa9 | 133 | int (*get_max_physical)(void); |
016c8150 DB |
134 | int (*get_min)(void); |
135 | int (*get_turbo)(void); | |
b27580b0 | 136 | int (*get_scaling)(void); |
fdfdb2b1 | 137 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 138 | void (*get_vid)(struct cpudata *); |
157386b6 | 139 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
140 | }; |
141 | ||
016c8150 DB |
142 | struct cpu_defaults { |
143 | struct pstate_adjust_policy pid_policy; | |
144 | struct pstate_funcs funcs; | |
93f0822d DB |
145 | }; |
146 | ||
157386b6 | 147 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
e70eed2b | 148 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); |
157386b6 | 149 | |
016c8150 DB |
150 | static struct pstate_adjust_policy pid_params; |
151 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 152 | static int hwp_active; |
016c8150 | 153 | |
93f0822d DB |
154 | struct perf_limits { |
155 | int no_turbo; | |
dd5fbf70 | 156 | int turbo_disabled; |
93f0822d DB |
157 | int max_perf_pct; |
158 | int min_perf_pct; | |
159 | int32_t max_perf; | |
160 | int32_t min_perf; | |
d8f469e9 DB |
161 | int max_policy_pct; |
162 | int max_sysfs_pct; | |
a0475992 KCA |
163 | int min_policy_pct; |
164 | int min_sysfs_pct; | |
93f0822d DB |
165 | }; |
166 | ||
51443fbf PB |
167 | static struct perf_limits performance_limits = { |
168 | .no_turbo = 0, | |
169 | .turbo_disabled = 0, | |
170 | .max_perf_pct = 100, | |
171 | .max_perf = int_tofp(1), | |
172 | .min_perf_pct = 100, | |
173 | .min_perf = int_tofp(1), | |
174 | .max_policy_pct = 100, | |
175 | .max_sysfs_pct = 100, | |
176 | .min_policy_pct = 0, | |
177 | .min_sysfs_pct = 0, | |
178 | }; | |
179 | ||
180 | static struct perf_limits powersave_limits = { | |
93f0822d | 181 | .no_turbo = 0, |
4521e1a0 | 182 | .turbo_disabled = 0, |
93f0822d DB |
183 | .max_perf_pct = 100, |
184 | .max_perf = int_tofp(1), | |
185 | .min_perf_pct = 0, | |
186 | .min_perf = 0, | |
d8f469e9 DB |
187 | .max_policy_pct = 100, |
188 | .max_sysfs_pct = 100, | |
a0475992 KCA |
189 | .min_policy_pct = 0, |
190 | .min_sysfs_pct = 0, | |
93f0822d DB |
191 | }; |
192 | ||
51443fbf PB |
193 | #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE |
194 | static struct perf_limits *limits = &performance_limits; | |
195 | #else | |
196 | static struct perf_limits *limits = &powersave_limits; | |
197 | #endif | |
198 | ||
93f0822d | 199 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 200 | int deadband, int integral) { |
b54a0dfd PL |
201 | pid->setpoint = int_tofp(setpoint); |
202 | pid->deadband = int_tofp(deadband); | |
93f0822d | 203 | pid->integral = int_tofp(integral); |
d98d099b | 204 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
205 | } |
206 | ||
207 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
208 | { | |
209 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
210 | } | |
211 | ||
212 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
213 | { | |
214 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
215 | } | |
216 | ||
217 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
218 | { | |
93f0822d DB |
219 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
220 | } | |
221 | ||
d253d2a5 | 222 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 223 | { |
d253d2a5 | 224 | signed int result; |
93f0822d DB |
225 | int32_t pterm, dterm, fp_error; |
226 | int32_t integral_limit; | |
227 | ||
b54a0dfd | 228 | fp_error = pid->setpoint - busy; |
93f0822d | 229 | |
b54a0dfd | 230 | if (abs(fp_error) <= pid->deadband) |
93f0822d DB |
231 | return 0; |
232 | ||
233 | pterm = mul_fp(pid->p_gain, fp_error); | |
234 | ||
235 | pid->integral += fp_error; | |
236 | ||
e0d4c8f8 KCA |
237 | /* |
238 | * We limit the integral here so that it will never | |
239 | * get higher than 30. This prevents it from becoming | |
240 | * too large an input over long periods of time and allows | |
241 | * it to get factored out sooner. | |
242 | * | |
243 | * The value of 30 was chosen through experimentation. | |
244 | */ | |
93f0822d DB |
245 | integral_limit = int_tofp(30); |
246 | if (pid->integral > integral_limit) | |
247 | pid->integral = integral_limit; | |
248 | if (pid->integral < -integral_limit) | |
249 | pid->integral = -integral_limit; | |
250 | ||
d253d2a5 BS |
251 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
252 | pid->last_err = fp_error; | |
93f0822d DB |
253 | |
254 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 255 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
256 | return (signed int)fp_toint(result); |
257 | } | |
258 | ||
259 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
260 | { | |
016c8150 DB |
261 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
262 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
263 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 264 | |
2d8d1f18 | 265 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
266 | } |
267 | ||
93f0822d DB |
268 | static inline void intel_pstate_reset_all_pid(void) |
269 | { | |
270 | unsigned int cpu; | |
845c1cbe | 271 | |
93f0822d DB |
272 | for_each_online_cpu(cpu) { |
273 | if (all_cpu_data[cpu]) | |
274 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
275 | } | |
276 | } | |
277 | ||
4521e1a0 GM |
278 | static inline void update_turbo_state(void) |
279 | { | |
280 | u64 misc_en; | |
281 | struct cpudata *cpu; | |
282 | ||
283 | cpu = all_cpu_data[0]; | |
284 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
51443fbf | 285 | limits->turbo_disabled = |
4521e1a0 GM |
286 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
287 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
288 | } | |
289 | ||
41cfd64c | 290 | static void intel_pstate_hwp_set(const struct cpumask *cpumask) |
2f86dc4c | 291 | { |
74da56ce KCA |
292 | int min, hw_min, max, hw_max, cpu, range, adj_range; |
293 | u64 value, cap; | |
294 | ||
295 | rdmsrl(MSR_HWP_CAPABILITIES, cap); | |
296 | hw_min = HWP_LOWEST_PERF(cap); | |
297 | hw_max = HWP_HIGHEST_PERF(cap); | |
298 | range = hw_max - hw_min; | |
2f86dc4c | 299 | |
41cfd64c | 300 | for_each_cpu(cpu, cpumask) { |
2f86dc4c | 301 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
51443fbf | 302 | adj_range = limits->min_perf_pct * range / 100; |
74da56ce | 303 | min = hw_min + adj_range; |
2f86dc4c DB |
304 | value &= ~HWP_MIN_PERF(~0L); |
305 | value |= HWP_MIN_PERF(min); | |
306 | ||
51443fbf | 307 | adj_range = limits->max_perf_pct * range / 100; |
74da56ce | 308 | max = hw_min + adj_range; |
51443fbf | 309 | if (limits->no_turbo) { |
74da56ce KCA |
310 | hw_max = HWP_GUARANTEED_PERF(cap); |
311 | if (hw_max < max) | |
312 | max = hw_max; | |
2f86dc4c DB |
313 | } |
314 | ||
315 | value &= ~HWP_MAX_PERF(~0L); | |
316 | value |= HWP_MAX_PERF(max); | |
317 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
318 | } | |
41cfd64c | 319 | } |
2f86dc4c | 320 | |
41cfd64c VK |
321 | static void intel_pstate_hwp_set_online_cpus(void) |
322 | { | |
323 | get_online_cpus(); | |
324 | intel_pstate_hwp_set(cpu_online_mask); | |
2f86dc4c DB |
325 | put_online_cpus(); |
326 | } | |
327 | ||
93f0822d DB |
328 | /************************** debugfs begin ************************/ |
329 | static int pid_param_set(void *data, u64 val) | |
330 | { | |
331 | *(u32 *)data = val; | |
332 | intel_pstate_reset_all_pid(); | |
333 | return 0; | |
334 | } | |
845c1cbe | 335 | |
93f0822d DB |
336 | static int pid_param_get(void *data, u64 *val) |
337 | { | |
338 | *val = *(u32 *)data; | |
339 | return 0; | |
340 | } | |
2d8d1f18 | 341 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
342 | |
343 | struct pid_param { | |
344 | char *name; | |
345 | void *value; | |
346 | }; | |
347 | ||
348 | static struct pid_param pid_files[] = { | |
016c8150 DB |
349 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
350 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
351 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
352 | {"deadband", &pid_params.deadband}, | |
353 | {"setpoint", &pid_params.setpoint}, | |
354 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
355 | {NULL, NULL} |
356 | }; | |
357 | ||
317dd50e | 358 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 359 | { |
317dd50e | 360 | struct dentry *debugfs_parent; |
93f0822d DB |
361 | int i = 0; |
362 | ||
2f86dc4c DB |
363 | if (hwp_active) |
364 | return; | |
93f0822d DB |
365 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
366 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
367 | return; | |
368 | while (pid_files[i].name) { | |
369 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
370 | debugfs_parent, pid_files[i].value, |
371 | &fops_pid_param); | |
93f0822d DB |
372 | i++; |
373 | } | |
374 | } | |
375 | ||
376 | /************************** debugfs end ************************/ | |
377 | ||
378 | /************************** sysfs begin ************************/ | |
379 | #define show_one(file_name, object) \ | |
380 | static ssize_t show_##file_name \ | |
381 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
382 | { \ | |
51443fbf | 383 | return sprintf(buf, "%u\n", limits->object); \ |
93f0822d DB |
384 | } |
385 | ||
d01b1f48 KCA |
386 | static ssize_t show_turbo_pct(struct kobject *kobj, |
387 | struct attribute *attr, char *buf) | |
388 | { | |
389 | struct cpudata *cpu; | |
390 | int total, no_turbo, turbo_pct; | |
391 | uint32_t turbo_fp; | |
392 | ||
393 | cpu = all_cpu_data[0]; | |
394 | ||
395 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
396 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
397 | turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); | |
398 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); | |
399 | return sprintf(buf, "%u\n", turbo_pct); | |
400 | } | |
401 | ||
0522424e KCA |
402 | static ssize_t show_num_pstates(struct kobject *kobj, |
403 | struct attribute *attr, char *buf) | |
404 | { | |
405 | struct cpudata *cpu; | |
406 | int total; | |
407 | ||
408 | cpu = all_cpu_data[0]; | |
409 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
410 | return sprintf(buf, "%u\n", total); | |
411 | } | |
412 | ||
4521e1a0 GM |
413 | static ssize_t show_no_turbo(struct kobject *kobj, |
414 | struct attribute *attr, char *buf) | |
415 | { | |
416 | ssize_t ret; | |
417 | ||
418 | update_turbo_state(); | |
51443fbf PB |
419 | if (limits->turbo_disabled) |
420 | ret = sprintf(buf, "%u\n", limits->turbo_disabled); | |
4521e1a0 | 421 | else |
51443fbf | 422 | ret = sprintf(buf, "%u\n", limits->no_turbo); |
4521e1a0 GM |
423 | |
424 | return ret; | |
425 | } | |
426 | ||
93f0822d | 427 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 428 | const char *buf, size_t count) |
93f0822d DB |
429 | { |
430 | unsigned int input; | |
431 | int ret; | |
845c1cbe | 432 | |
93f0822d DB |
433 | ret = sscanf(buf, "%u", &input); |
434 | if (ret != 1) | |
435 | return -EINVAL; | |
4521e1a0 GM |
436 | |
437 | update_turbo_state(); | |
51443fbf | 438 | if (limits->turbo_disabled) { |
f16255eb | 439 | pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n"); |
4521e1a0 | 440 | return -EPERM; |
dd5fbf70 | 441 | } |
2f86dc4c | 442 | |
51443fbf | 443 | limits->no_turbo = clamp_t(int, input, 0, 1); |
4521e1a0 | 444 | |
2f86dc4c | 445 | if (hwp_active) |
41cfd64c | 446 | intel_pstate_hwp_set_online_cpus(); |
2f86dc4c | 447 | |
93f0822d DB |
448 | return count; |
449 | } | |
450 | ||
451 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 452 | const char *buf, size_t count) |
93f0822d DB |
453 | { |
454 | unsigned int input; | |
455 | int ret; | |
845c1cbe | 456 | |
93f0822d DB |
457 | ret = sscanf(buf, "%u", &input); |
458 | if (ret != 1) | |
459 | return -EINVAL; | |
460 | ||
51443fbf PB |
461 | limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); |
462 | limits->max_perf_pct = min(limits->max_policy_pct, | |
463 | limits->max_sysfs_pct); | |
464 | limits->max_perf_pct = max(limits->min_policy_pct, | |
465 | limits->max_perf_pct); | |
466 | limits->max_perf_pct = max(limits->min_perf_pct, | |
467 | limits->max_perf_pct); | |
468 | limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), | |
469 | int_tofp(100)); | |
845c1cbe | 470 | |
2f86dc4c | 471 | if (hwp_active) |
41cfd64c | 472 | intel_pstate_hwp_set_online_cpus(); |
93f0822d DB |
473 | return count; |
474 | } | |
475 | ||
476 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 477 | const char *buf, size_t count) |
93f0822d DB |
478 | { |
479 | unsigned int input; | |
480 | int ret; | |
845c1cbe | 481 | |
93f0822d DB |
482 | ret = sscanf(buf, "%u", &input); |
483 | if (ret != 1) | |
484 | return -EINVAL; | |
a0475992 | 485 | |
51443fbf PB |
486 | limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); |
487 | limits->min_perf_pct = max(limits->min_policy_pct, | |
488 | limits->min_sysfs_pct); | |
489 | limits->min_perf_pct = min(limits->max_policy_pct, | |
490 | limits->min_perf_pct); | |
491 | limits->min_perf_pct = min(limits->max_perf_pct, | |
492 | limits->min_perf_pct); | |
493 | limits->min_perf = div_fp(int_tofp(limits->min_perf_pct), | |
494 | int_tofp(100)); | |
93f0822d | 495 | |
2f86dc4c | 496 | if (hwp_active) |
41cfd64c | 497 | intel_pstate_hwp_set_online_cpus(); |
93f0822d DB |
498 | return count; |
499 | } | |
500 | ||
93f0822d DB |
501 | show_one(max_perf_pct, max_perf_pct); |
502 | show_one(min_perf_pct, min_perf_pct); | |
503 | ||
504 | define_one_global_rw(no_turbo); | |
505 | define_one_global_rw(max_perf_pct); | |
506 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 507 | define_one_global_ro(turbo_pct); |
0522424e | 508 | define_one_global_ro(num_pstates); |
93f0822d DB |
509 | |
510 | static struct attribute *intel_pstate_attributes[] = { | |
511 | &no_turbo.attr, | |
512 | &max_perf_pct.attr, | |
513 | &min_perf_pct.attr, | |
d01b1f48 | 514 | &turbo_pct.attr, |
0522424e | 515 | &num_pstates.attr, |
93f0822d DB |
516 | NULL |
517 | }; | |
518 | ||
519 | static struct attribute_group intel_pstate_attr_group = { | |
520 | .attrs = intel_pstate_attributes, | |
521 | }; | |
93f0822d | 522 | |
317dd50e | 523 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 524 | { |
317dd50e | 525 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
526 | int rc; |
527 | ||
528 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
529 | &cpu_subsys.dev_root->kobj); | |
530 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 531 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
532 | BUG_ON(rc); |
533 | } | |
93f0822d | 534 | /************************** sysfs end ************************/ |
2f86dc4c | 535 | |
ba88d433 | 536 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 537 | { |
f05c9665 SP |
538 | /* First disable HWP notification interrupt as we don't process them */ |
539 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
540 | ||
ba88d433 | 541 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
542 | } |
543 | ||
938d21a2 | 544 | static int atom_get_min_pstate(void) |
19e77c28 DB |
545 | { |
546 | u64 value; | |
845c1cbe | 547 | |
938d21a2 | 548 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 549 | return (value >> 8) & 0x7F; |
19e77c28 DB |
550 | } |
551 | ||
938d21a2 | 552 | static int atom_get_max_pstate(void) |
19e77c28 DB |
553 | { |
554 | u64 value; | |
845c1cbe | 555 | |
938d21a2 | 556 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 557 | return (value >> 16) & 0x7F; |
19e77c28 | 558 | } |
93f0822d | 559 | |
938d21a2 | 560 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
561 | { |
562 | u64 value; | |
845c1cbe | 563 | |
938d21a2 | 564 | rdmsrl(ATOM_TURBO_RATIOS, value); |
c16ed060 | 565 | return value & 0x7F; |
61d8d2ab DB |
566 | } |
567 | ||
fdfdb2b1 | 568 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
569 | { |
570 | u64 val; | |
571 | int32_t vid_fp; | |
572 | u32 vid; | |
573 | ||
144c8e17 | 574 | val = (u64)pstate << 8; |
51443fbf | 575 | if (limits->no_turbo && !limits->turbo_disabled) |
007bea09 DB |
576 | val |= (u64)1 << 32; |
577 | ||
578 | vid_fp = cpudata->vid.min + mul_fp( | |
579 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
580 | cpudata->vid.ratio); | |
581 | ||
582 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 583 | vid = ceiling_fp(vid_fp); |
007bea09 | 584 | |
21855ff5 DB |
585 | if (pstate > cpudata->pstate.max_pstate) |
586 | vid = cpudata->vid.turbo; | |
587 | ||
fdfdb2b1 | 588 | return val | vid; |
007bea09 DB |
589 | } |
590 | ||
1421df63 | 591 | static int silvermont_get_scaling(void) |
b27580b0 DB |
592 | { |
593 | u64 value; | |
594 | int i; | |
1421df63 PL |
595 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
596 | static int silvermont_freq_table[] = { | |
597 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
598 | |
599 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
600 | i = value & 0x7; |
601 | WARN_ON(i > 4); | |
b27580b0 | 602 | |
1421df63 PL |
603 | return silvermont_freq_table[i]; |
604 | } | |
b27580b0 | 605 | |
1421df63 PL |
606 | static int airmont_get_scaling(void) |
607 | { | |
608 | u64 value; | |
609 | int i; | |
610 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
611 | static int airmont_freq_table[] = { | |
612 | 83300, 100000, 133300, 116700, 80000, | |
613 | 93300, 90000, 88900, 87500}; | |
614 | ||
615 | rdmsrl(MSR_FSB_FREQ, value); | |
616 | i = value & 0xF; | |
617 | WARN_ON(i > 8); | |
618 | ||
619 | return airmont_freq_table[i]; | |
b27580b0 DB |
620 | } |
621 | ||
938d21a2 | 622 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
623 | { |
624 | u64 value; | |
625 | ||
938d21a2 | 626 | rdmsrl(ATOM_VIDS, value); |
c16ed060 DB |
627 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
628 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
629 | cpudata->vid.ratio = div_fp( |
630 | cpudata->vid.max - cpudata->vid.min, | |
631 | int_tofp(cpudata->pstate.max_pstate - | |
632 | cpudata->pstate.min_pstate)); | |
21855ff5 | 633 | |
938d21a2 | 634 | rdmsrl(ATOM_TURBO_VIDS, value); |
21855ff5 | 635 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
636 | } |
637 | ||
016c8150 | 638 | static int core_get_min_pstate(void) |
93f0822d DB |
639 | { |
640 | u64 value; | |
845c1cbe | 641 | |
05e99c8c | 642 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
643 | return (value >> 40) & 0xFF; |
644 | } | |
645 | ||
3bcc6fa9 | 646 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
647 | { |
648 | u64 value; | |
845c1cbe | 649 | |
05e99c8c | 650 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
651 | return (value >> 8) & 0xFF; |
652 | } | |
653 | ||
016c8150 | 654 | static int core_get_max_pstate(void) |
93f0822d | 655 | { |
6a35fc2d SP |
656 | u64 tar; |
657 | u64 plat_info; | |
658 | int max_pstate; | |
659 | int err; | |
660 | ||
661 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
662 | max_pstate = (plat_info >> 8) & 0xFF; | |
663 | ||
664 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); | |
665 | if (!err) { | |
666 | /* Do some sanity checking for safety */ | |
667 | if (plat_info & 0x600000000) { | |
668 | u64 tdp_ctrl; | |
669 | u64 tdp_ratio; | |
670 | int tdp_msr; | |
671 | ||
672 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
673 | if (err) | |
674 | goto skip_tar; | |
675 | ||
676 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; | |
677 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
678 | if (err) | |
679 | goto skip_tar; | |
680 | ||
681 | if (tdp_ratio - 1 == tar) { | |
682 | max_pstate = tar; | |
683 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
684 | } else { | |
685 | goto skip_tar; | |
686 | } | |
687 | } | |
688 | } | |
845c1cbe | 689 | |
6a35fc2d SP |
690 | skip_tar: |
691 | return max_pstate; | |
93f0822d DB |
692 | } |
693 | ||
016c8150 | 694 | static int core_get_turbo_pstate(void) |
93f0822d DB |
695 | { |
696 | u64 value; | |
697 | int nont, ret; | |
845c1cbe | 698 | |
05e99c8c | 699 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 700 | nont = core_get_max_pstate(); |
285cb990 | 701 | ret = (value) & 255; |
93f0822d DB |
702 | if (ret <= nont) |
703 | ret = nont; | |
704 | return ret; | |
705 | } | |
706 | ||
b27580b0 DB |
707 | static inline int core_get_scaling(void) |
708 | { | |
709 | return 100000; | |
710 | } | |
711 | ||
fdfdb2b1 | 712 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
713 | { |
714 | u64 val; | |
715 | ||
144c8e17 | 716 | val = (u64)pstate << 8; |
51443fbf | 717 | if (limits->no_turbo && !limits->turbo_disabled) |
016c8150 DB |
718 | val |= (u64)1 << 32; |
719 | ||
fdfdb2b1 | 720 | return val; |
016c8150 DB |
721 | } |
722 | ||
b34ef932 DC |
723 | static int knl_get_turbo_pstate(void) |
724 | { | |
725 | u64 value; | |
726 | int nont, ret; | |
727 | ||
728 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); | |
729 | nont = core_get_max_pstate(); | |
730 | ret = (((value) >> 8) & 0xFF); | |
731 | if (ret <= nont) | |
732 | ret = nont; | |
733 | return ret; | |
734 | } | |
735 | ||
016c8150 DB |
736 | static struct cpu_defaults core_params = { |
737 | .pid_policy = { | |
738 | .sample_rate_ms = 10, | |
739 | .deadband = 0, | |
740 | .setpoint = 97, | |
741 | .p_gain_pct = 20, | |
742 | .d_gain_pct = 0, | |
743 | .i_gain_pct = 0, | |
744 | }, | |
745 | .funcs = { | |
746 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 747 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
748 | .get_min = core_get_min_pstate, |
749 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 750 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 751 | .get_val = core_get_val, |
157386b6 | 752 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
753 | }, |
754 | }; | |
755 | ||
1421df63 PL |
756 | static struct cpu_defaults silvermont_params = { |
757 | .pid_policy = { | |
758 | .sample_rate_ms = 10, | |
759 | .deadband = 0, | |
760 | .setpoint = 60, | |
761 | .p_gain_pct = 14, | |
762 | .d_gain_pct = 0, | |
763 | .i_gain_pct = 4, | |
764 | }, | |
765 | .funcs = { | |
766 | .get_max = atom_get_max_pstate, | |
767 | .get_max_physical = atom_get_max_pstate, | |
768 | .get_min = atom_get_min_pstate, | |
769 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 770 | .get_val = atom_get_val, |
1421df63 PL |
771 | .get_scaling = silvermont_get_scaling, |
772 | .get_vid = atom_get_vid, | |
e70eed2b | 773 | .get_target_pstate = get_target_pstate_use_cpu_load, |
1421df63 PL |
774 | }, |
775 | }; | |
776 | ||
777 | static struct cpu_defaults airmont_params = { | |
19e77c28 DB |
778 | .pid_policy = { |
779 | .sample_rate_ms = 10, | |
780 | .deadband = 0, | |
6a82ba6d | 781 | .setpoint = 60, |
19e77c28 DB |
782 | .p_gain_pct = 14, |
783 | .d_gain_pct = 0, | |
784 | .i_gain_pct = 4, | |
785 | }, | |
786 | .funcs = { | |
938d21a2 PL |
787 | .get_max = atom_get_max_pstate, |
788 | .get_max_physical = atom_get_max_pstate, | |
789 | .get_min = atom_get_min_pstate, | |
790 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 791 | .get_val = atom_get_val, |
1421df63 | 792 | .get_scaling = airmont_get_scaling, |
938d21a2 | 793 | .get_vid = atom_get_vid, |
e70eed2b | 794 | .get_target_pstate = get_target_pstate_use_cpu_load, |
19e77c28 DB |
795 | }, |
796 | }; | |
797 | ||
b34ef932 DC |
798 | static struct cpu_defaults knl_params = { |
799 | .pid_policy = { | |
800 | .sample_rate_ms = 10, | |
801 | .deadband = 0, | |
802 | .setpoint = 97, | |
803 | .p_gain_pct = 20, | |
804 | .d_gain_pct = 0, | |
805 | .i_gain_pct = 0, | |
806 | }, | |
807 | .funcs = { | |
808 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 809 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
810 | .get_min = core_get_min_pstate, |
811 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 812 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 813 | .get_val = core_get_val, |
157386b6 | 814 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
815 | }, |
816 | }; | |
817 | ||
93f0822d DB |
818 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
819 | { | |
820 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 821 | int max_perf_adj; |
93f0822d | 822 | int min_perf; |
845c1cbe | 823 | |
51443fbf | 824 | if (limits->no_turbo || limits->turbo_disabled) |
93f0822d DB |
825 | max_perf = cpu->pstate.max_pstate; |
826 | ||
e0d4c8f8 KCA |
827 | /* |
828 | * performance can be limited by user through sysfs, by cpufreq | |
829 | * policy, or by cpu specific default values determined through | |
830 | * experimentation. | |
831 | */ | |
a158bed5 | 832 | max_perf_adj = fp_toint(max_perf * limits->max_perf); |
799281a3 RW |
833 | *max = clamp_t(int, max_perf_adj, |
834 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 835 | |
a158bed5 | 836 | min_perf = fp_toint(max_perf * limits->min_perf); |
799281a3 | 837 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
838 | } |
839 | ||
fdfdb2b1 | 840 | static inline void intel_pstate_record_pstate(struct cpudata *cpu, int pstate) |
93f0822d | 841 | { |
b27580b0 | 842 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
93f0822d | 843 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 | 844 | } |
93f0822d | 845 | |
fdfdb2b1 RW |
846 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
847 | { | |
848 | int pstate = cpu->pstate.min_pstate; | |
849 | ||
850 | intel_pstate_record_pstate(cpu, pstate); | |
851 | /* | |
852 | * Generally, there is no guarantee that this code will always run on | |
853 | * the CPU being updated, so force the register update to run on the | |
854 | * right CPU. | |
855 | */ | |
856 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
857 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
858 | } |
859 | ||
93f0822d DB |
860 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
861 | { | |
016c8150 DB |
862 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
863 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 864 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 865 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 866 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 867 | |
007bea09 DB |
868 | if (pstate_funcs.get_vid) |
869 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
870 | |
871 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
872 | } |
873 | ||
6b17ddb2 | 874 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 875 | { |
6b17ddb2 | 876 | struct sample *sample = &cpu->sample; |
bf810222 | 877 | int64_t core_pct; |
93f0822d | 878 | |
bf810222 | 879 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 880 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 881 | |
bf810222 | 882 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
883 | } |
884 | ||
4fec7ad5 | 885 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 886 | { |
93f0822d | 887 | u64 aperf, mperf; |
4ab60c3f | 888 | unsigned long flags; |
4055fad3 | 889 | u64 tsc; |
93f0822d | 890 | |
4ab60c3f | 891 | local_irq_save(flags); |
93f0822d DB |
892 | rdmsrl(MSR_IA32_APERF, aperf); |
893 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 894 | tsc = rdtsc(); |
4fec7ad5 | 895 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 896 | local_irq_restore(flags); |
4fec7ad5 | 897 | return false; |
8e601a9f | 898 | } |
4ab60c3f | 899 | local_irq_restore(flags); |
b69880f9 | 900 | |
c4ee841f | 901 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 902 | cpu->sample.time = time; |
d37e2b76 DB |
903 | cpu->sample.aperf = aperf; |
904 | cpu->sample.mperf = mperf; | |
4055fad3 | 905 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
906 | cpu->sample.aperf -= cpu->prev_aperf; |
907 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 908 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 909 | |
93f0822d DB |
910 | cpu->prev_aperf = aperf; |
911 | cpu->prev_mperf = mperf; | |
4055fad3 | 912 | cpu->prev_tsc = tsc; |
febce40f RW |
913 | /* |
914 | * First time this function is invoked in a given cycle, all of the | |
915 | * previous sample data fields are equal to zero or stale and they must | |
916 | * be populated with meaningful numbers for things to work, so assume | |
917 | * that sample.time will always be reset before setting the utilization | |
918 | * update hook and make the caller skip the sample then. | |
919 | */ | |
920 | return !!cpu->last_sample_time; | |
93f0822d DB |
921 | } |
922 | ||
8fa520af PL |
923 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
924 | { | |
925 | return div64_u64(cpu->pstate.max_pstate_physical * cpu->sample.aperf * | |
926 | cpu->pstate.scaling, cpu->sample.mperf); | |
927 | } | |
928 | ||
e70eed2b PL |
929 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
930 | { | |
931 | struct sample *sample = &cpu->sample; | |
63d1d656 PL |
932 | u64 cummulative_iowait, delta_iowait_us; |
933 | u64 delta_iowait_mperf; | |
934 | u64 mperf, now; | |
e70eed2b PL |
935 | int32_t cpu_load; |
936 | ||
63d1d656 PL |
937 | cummulative_iowait = get_cpu_iowait_time_us(cpu->cpu, &now); |
938 | ||
939 | /* | |
940 | * Convert iowait time into number of IO cycles spent at max_freq. | |
941 | * IO is considered as busy only for the cpu_load algorithm. For | |
942 | * performance this is not needed since we always try to reach the | |
943 | * maximum P-State, so we are already boosting the IOs. | |
944 | */ | |
945 | delta_iowait_us = cummulative_iowait - cpu->prev_cummulative_iowait; | |
946 | delta_iowait_mperf = div64_u64(delta_iowait_us * cpu->pstate.scaling * | |
947 | cpu->pstate.max_pstate, MSEC_PER_SEC); | |
948 | ||
949 | mperf = cpu->sample.mperf + delta_iowait_mperf; | |
950 | cpu->prev_cummulative_iowait = cummulative_iowait; | |
951 | ||
e70eed2b PL |
952 | /* |
953 | * The load can be estimated as the ratio of the mperf counter | |
954 | * running at a constant frequency during active periods | |
955 | * (C0) and the time stamp counter running at the same frequency | |
956 | * also during C-states. | |
957 | */ | |
63d1d656 | 958 | cpu_load = div64_u64(int_tofp(100) * mperf, sample->tsc); |
e70eed2b PL |
959 | cpu->sample.busy_scaled = cpu_load; |
960 | ||
961 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, cpu_load); | |
962 | } | |
963 | ||
157386b6 | 964 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 965 | { |
c4ee841f | 966 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
a4675fbc | 967 | u64 duration_ns; |
93f0822d | 968 | |
7349ec04 PL |
969 | intel_pstate_calc_busy(cpu); |
970 | ||
e0d4c8f8 KCA |
971 | /* |
972 | * core_busy is the ratio of actual performance to max | |
973 | * max_pstate is the max non turbo pstate available | |
974 | * current_pstate was the pstate that was requested during | |
975 | * the last sample period. | |
976 | * | |
977 | * We normalize core_busy, which was our actual percent | |
978 | * performance to what we requested during the last sample | |
979 | * period. The result will be a percentage of busy at a | |
980 | * specified pstate. | |
981 | */ | |
d37e2b76 | 982 | core_busy = cpu->sample.core_pct_busy; |
3bcc6fa9 | 983 | max_pstate = int_tofp(cpu->pstate.max_pstate_physical); |
93f0822d | 984 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 985 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 986 | |
e0d4c8f8 | 987 | /* |
a4675fbc RW |
988 | * Since our utilization update callback will not run unless we are |
989 | * in C0, check if the actual elapsed time is significantly greater (3x) | |
990 | * than our sample interval. If it is, then we were idle for a long | |
991 | * enough period of time to adjust our busyness. | |
e0d4c8f8 | 992 | */ |
a4675fbc | 993 | duration_ns = cpu->sample.time - cpu->last_sample_time; |
febce40f | 994 | if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { |
a4675fbc RW |
995 | sample_ratio = div_fp(int_tofp(pid_params.sample_rate_ns), |
996 | int_tofp(duration_ns)); | |
c4ee841f DB |
997 | core_busy = mul_fp(core_busy, sample_ratio); |
998 | } | |
999 | ||
157386b6 PL |
1000 | cpu->sample.busy_scaled = core_busy; |
1001 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, core_busy); | |
93f0822d DB |
1002 | } |
1003 | ||
fdfdb2b1 RW |
1004 | static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) |
1005 | { | |
1006 | int max_perf, min_perf; | |
1007 | ||
1008 | update_turbo_state(); | |
1009 | ||
1010 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); | |
1011 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
1012 | if (pstate == cpu->pstate.current_pstate) | |
1013 | return; | |
1014 | ||
1015 | intel_pstate_record_pstate(cpu, pstate); | |
1016 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); | |
1017 | } | |
1018 | ||
93f0822d DB |
1019 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) |
1020 | { | |
157386b6 | 1021 | int from, target_pstate; |
4055fad3 DS |
1022 | struct sample *sample; |
1023 | ||
1024 | from = cpu->pstate.current_pstate; | |
93f0822d | 1025 | |
157386b6 | 1026 | target_pstate = pstate_funcs.get_target_pstate(cpu); |
93f0822d | 1027 | |
fdfdb2b1 | 1028 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1029 | |
1030 | sample = &cpu->sample; | |
1031 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
157386b6 | 1032 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1033 | from, |
1034 | cpu->pstate.current_pstate, | |
1035 | sample->mperf, | |
1036 | sample->aperf, | |
1037 | sample->tsc, | |
8fa520af | 1038 | get_avg_frequency(cpu)); |
93f0822d DB |
1039 | } |
1040 | ||
a4675fbc RW |
1041 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
1042 | unsigned long util, unsigned long max) | |
93f0822d | 1043 | { |
a4675fbc RW |
1044 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
1045 | u64 delta_ns = time - cpu->sample.time; | |
b69880f9 | 1046 | |
a4675fbc | 1047 | if ((s64)delta_ns >= pid_params.sample_rate_ns) { |
4fec7ad5 RW |
1048 | bool sample_taken = intel_pstate_sample(cpu, time); |
1049 | ||
1050 | if (sample_taken && !hwp_active) | |
a4675fbc RW |
1051 | intel_pstate_adjust_busy_pstate(cpu); |
1052 | } | |
93f0822d DB |
1053 | } |
1054 | ||
1055 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1056 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1057 | (unsigned long)&policy } | |
93f0822d DB |
1058 | |
1059 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
1060 | ICPU(0x2a, core_params), |
1061 | ICPU(0x2d, core_params), | |
1421df63 | 1062 | ICPU(0x37, silvermont_params), |
016c8150 DB |
1063 | ICPU(0x3a, core_params), |
1064 | ICPU(0x3c, core_params), | |
c7e241df | 1065 | ICPU(0x3d, core_params), |
016c8150 DB |
1066 | ICPU(0x3e, core_params), |
1067 | ICPU(0x3f, core_params), | |
1068 | ICPU(0x45, core_params), | |
1069 | ICPU(0x46, core_params), | |
43f8a966 | 1070 | ICPU(0x47, core_params), |
1421df63 | 1071 | ICPU(0x4c, airmont_params), |
7ab0256e | 1072 | ICPU(0x4e, core_params), |
c7e241df | 1073 | ICPU(0x4f, core_params), |
1c939123 | 1074 | ICPU(0x5e, core_params), |
c7e241df | 1075 | ICPU(0x56, core_params), |
b34ef932 | 1076 | ICPU(0x57, knl_params), |
93f0822d DB |
1077 | {} |
1078 | }; | |
1079 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1080 | ||
2f86dc4c DB |
1081 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
1082 | ICPU(0x56, core_params), | |
1083 | {} | |
1084 | }; | |
1085 | ||
93f0822d DB |
1086 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1087 | { | |
93f0822d DB |
1088 | struct cpudata *cpu; |
1089 | ||
c0348717 DB |
1090 | if (!all_cpu_data[cpunum]) |
1091 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
1092 | GFP_KERNEL); | |
93f0822d DB |
1093 | if (!all_cpu_data[cpunum]) |
1094 | return -ENOMEM; | |
1095 | ||
1096 | cpu = all_cpu_data[cpunum]; | |
1097 | ||
93f0822d | 1098 | cpu->cpu = cpunum; |
ba88d433 | 1099 | |
a4675fbc | 1100 | if (hwp_active) { |
ba88d433 | 1101 | intel_pstate_hwp_enable(cpu); |
a4675fbc RW |
1102 | pid_params.sample_rate_ms = 50; |
1103 | pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; | |
1104 | } | |
ba88d433 | 1105 | |
179e8471 | 1106 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1107 | |
93f0822d | 1108 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 1109 | |
a4675fbc | 1110 | cpu->update_util.func = intel_pstate_update_util; |
93f0822d | 1111 | |
f16255eb | 1112 | pr_debug("intel_pstate: controlling: cpu %d\n", cpunum); |
93f0822d DB |
1113 | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1118 | { | |
1119 | struct sample *sample; | |
1120 | struct cpudata *cpu; | |
1121 | ||
1122 | cpu = all_cpu_data[cpu_num]; | |
1123 | if (!cpu) | |
1124 | return 0; | |
d37e2b76 | 1125 | sample = &cpu->sample; |
8fa520af | 1126 | return get_avg_frequency(cpu); |
93f0822d DB |
1127 | } |
1128 | ||
febce40f | 1129 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1130 | { |
febce40f RW |
1131 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1132 | ||
1133 | /* Prevent intel_pstate_update_util() from using stale data. */ | |
1134 | cpu->sample.time = 0; | |
1135 | cpufreq_set_update_util_data(cpu_num, &cpu->update_util); | |
bb6ab52f RW |
1136 | } |
1137 | ||
1138 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1139 | { | |
1140 | cpufreq_set_update_util_data(cpu, NULL); | |
1141 | synchronize_sched(); | |
1142 | } | |
1143 | ||
93f0822d DB |
1144 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
1145 | { | |
d3929b83 DB |
1146 | if (!policy->cpuinfo.max_freq) |
1147 | return -ENODEV; | |
1148 | ||
bb6ab52f RW |
1149 | intel_pstate_clear_update_util_hook(policy->cpu); |
1150 | ||
630ec286 SP |
1151 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && |
1152 | policy->max >= policy->cpuinfo.max_freq) { | |
51443fbf PB |
1153 | pr_debug("intel_pstate: set performance\n"); |
1154 | limits = &performance_limits; | |
bb6ab52f | 1155 | goto out; |
93f0822d | 1156 | } |
2f86dc4c | 1157 | |
51443fbf PB |
1158 | pr_debug("intel_pstate: set powersave\n"); |
1159 | limits = &powersave_limits; | |
1160 | limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; | |
1161 | limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); | |
8478f539 PB |
1162 | limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, |
1163 | policy->cpuinfo.max_freq); | |
51443fbf | 1164 | limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); |
43717aad CY |
1165 | |
1166 | /* Normalize user input to [min_policy_pct, max_policy_pct] */ | |
51443fbf PB |
1167 | limits->min_perf_pct = max(limits->min_policy_pct, |
1168 | limits->min_sysfs_pct); | |
1169 | limits->min_perf_pct = min(limits->max_policy_pct, | |
1170 | limits->min_perf_pct); | |
1171 | limits->max_perf_pct = min(limits->max_policy_pct, | |
1172 | limits->max_sysfs_pct); | |
1173 | limits->max_perf_pct = max(limits->min_policy_pct, | |
1174 | limits->max_perf_pct); | |
88b7b7c0 | 1175 | limits->max_perf = round_up(limits->max_perf, FRAC_BITS); |
43717aad CY |
1176 | |
1177 | /* Make sure min_perf_pct <= max_perf_pct */ | |
51443fbf | 1178 | limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); |
43717aad | 1179 | |
51443fbf PB |
1180 | limits->min_perf = div_fp(int_tofp(limits->min_perf_pct), |
1181 | int_tofp(100)); | |
1182 | limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), | |
1183 | int_tofp(100)); | |
93f0822d | 1184 | |
bb6ab52f RW |
1185 | out: |
1186 | intel_pstate_set_update_util_hook(policy->cpu); | |
1187 | ||
2f86dc4c | 1188 | if (hwp_active) |
41cfd64c | 1189 | intel_pstate_hwp_set(policy->cpus); |
2f86dc4c | 1190 | |
93f0822d DB |
1191 | return 0; |
1192 | } | |
1193 | ||
1194 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1195 | { | |
be49e346 | 1196 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1197 | |
285cb990 | 1198 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1199 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1200 | return -EINVAL; |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
bb18008f | 1205 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1206 | { |
bb18008f DB |
1207 | int cpu_num = policy->cpu; |
1208 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1209 | |
f16255eb | 1210 | pr_debug("intel_pstate: CPU %d exiting\n", cpu_num); |
bb18008f | 1211 | |
bb6ab52f | 1212 | intel_pstate_clear_update_util_hook(cpu_num); |
a4675fbc | 1213 | |
2f86dc4c DB |
1214 | if (hwp_active) |
1215 | return; | |
1216 | ||
fdfdb2b1 | 1217 | intel_pstate_set_min_pstate(cpu); |
93f0822d DB |
1218 | } |
1219 | ||
2760984f | 1220 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1221 | { |
93f0822d | 1222 | struct cpudata *cpu; |
52e0a509 | 1223 | int rc; |
93f0822d DB |
1224 | |
1225 | rc = intel_pstate_init_cpu(policy->cpu); | |
1226 | if (rc) | |
1227 | return rc; | |
1228 | ||
1229 | cpu = all_cpu_data[policy->cpu]; | |
1230 | ||
51443fbf | 1231 | if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) |
93f0822d DB |
1232 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1233 | else | |
1234 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1235 | ||
b27580b0 DB |
1236 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1237 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1238 | |
1239 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
1240 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1241 | policy->cpuinfo.max_freq = | |
1242 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1243 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1244 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1245 | ||
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | static struct cpufreq_driver intel_pstate_driver = { | |
1250 | .flags = CPUFREQ_CONST_LOOPS, | |
1251 | .verify = intel_pstate_verify_policy, | |
1252 | .setpolicy = intel_pstate_set_policy, | |
1253 | .get = intel_pstate_get, | |
1254 | .init = intel_pstate_cpu_init, | |
bb18008f | 1255 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1256 | .name = "intel_pstate", |
93f0822d DB |
1257 | }; |
1258 | ||
6be26498 | 1259 | static int __initdata no_load; |
2f86dc4c | 1260 | static int __initdata no_hwp; |
d64c3b0b | 1261 | static int __initdata hwp_only; |
aa4ea34d | 1262 | static unsigned int force_load; |
6be26498 | 1263 | |
b563b4e3 DB |
1264 | static int intel_pstate_msrs_not_valid(void) |
1265 | { | |
016c8150 | 1266 | if (!pstate_funcs.get_max() || |
c410833a SK |
1267 | !pstate_funcs.get_min() || |
1268 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1269 | return -ENODEV; |
1270 | ||
b563b4e3 DB |
1271 | return 0; |
1272 | } | |
016c8150 | 1273 | |
e0a261a2 | 1274 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1275 | { |
1276 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
a4675fbc | 1277 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
016c8150 DB |
1278 | pid_params.p_gain_pct = policy->p_gain_pct; |
1279 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1280 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1281 | pid_params.deadband = policy->deadband; | |
1282 | pid_params.setpoint = policy->setpoint; | |
1283 | } | |
1284 | ||
e0a261a2 | 1285 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1286 | { |
1287 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 1288 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
1289 | pstate_funcs.get_min = funcs->get_min; |
1290 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1291 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 1292 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 1293 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
1294 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
1295 | ||
016c8150 DB |
1296 | } |
1297 | ||
fbbcdc07 | 1298 | #if IS_ENABLED(CONFIG_ACPI) |
6ee11e41 | 1299 | #include <acpi/processor.h> |
fbbcdc07 AH |
1300 | |
1301 | static bool intel_pstate_no_acpi_pss(void) | |
1302 | { | |
1303 | int i; | |
1304 | ||
1305 | for_each_possible_cpu(i) { | |
1306 | acpi_status status; | |
1307 | union acpi_object *pss; | |
1308 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1309 | struct acpi_processor *pr = per_cpu(processors, i); | |
1310 | ||
1311 | if (!pr) | |
1312 | continue; | |
1313 | ||
1314 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1315 | if (ACPI_FAILURE(status)) | |
1316 | continue; | |
1317 | ||
1318 | pss = buffer.pointer; | |
1319 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1320 | kfree(pss); | |
1321 | return false; | |
1322 | } | |
1323 | ||
1324 | kfree(pss); | |
1325 | } | |
1326 | ||
1327 | return true; | |
1328 | } | |
1329 | ||
966916ea | 1330 | static bool intel_pstate_has_acpi_ppc(void) |
1331 | { | |
1332 | int i; | |
1333 | ||
1334 | for_each_possible_cpu(i) { | |
1335 | struct acpi_processor *pr = per_cpu(processors, i); | |
1336 | ||
1337 | if (!pr) | |
1338 | continue; | |
1339 | if (acpi_has_method(pr->handle, "_PPC")) | |
1340 | return true; | |
1341 | } | |
1342 | return false; | |
1343 | } | |
1344 | ||
1345 | enum { | |
1346 | PSS, | |
1347 | PPC, | |
1348 | }; | |
1349 | ||
fbbcdc07 AH |
1350 | struct hw_vendor_info { |
1351 | u16 valid; | |
1352 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1353 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1354 | int oem_pwr_table; |
fbbcdc07 AH |
1355 | }; |
1356 | ||
1357 | /* Hardware vendor-specific info that has its own power management modes */ | |
1358 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1359 | {1, "HP ", "ProLiant", PSS}, |
1360 | {1, "ORACLE", "X4-2 ", PPC}, | |
1361 | {1, "ORACLE", "X4-2L ", PPC}, | |
1362 | {1, "ORACLE", "X4-2B ", PPC}, | |
1363 | {1, "ORACLE", "X3-2 ", PPC}, | |
1364 | {1, "ORACLE", "X3-2L ", PPC}, | |
1365 | {1, "ORACLE", "X3-2B ", PPC}, | |
1366 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1367 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1368 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1369 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
1370 | {1, "ORACLE", "X4170 M3", PPC}, |
1371 | {1, "ORACLE", "X4275 M3", PPC}, | |
1372 | {1, "ORACLE", "X6-2 ", PPC}, | |
1373 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
1374 | {0, "", ""}, |
1375 | }; | |
1376 | ||
1377 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1378 | { | |
1379 | struct acpi_table_header hdr; | |
1380 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1381 | const struct x86_cpu_id *id; |
1382 | u64 misc_pwr; | |
1383 | ||
1384 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1385 | if (id) { | |
1386 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1387 | if ( misc_pwr & (1 << 8)) | |
1388 | return true; | |
1389 | } | |
fbbcdc07 | 1390 | |
c410833a SK |
1391 | if (acpi_disabled || |
1392 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1393 | return false; |
1394 | ||
1395 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1396 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1397 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1398 | ACPI_OEM_TABLE_ID_SIZE)) | |
1399 | switch (v_info->oem_pwr_table) { | |
1400 | case PSS: | |
1401 | return intel_pstate_no_acpi_pss(); | |
1402 | case PPC: | |
aa4ea34d EZ |
1403 | return intel_pstate_has_acpi_ppc() && |
1404 | (!force_load); | |
966916ea | 1405 | } |
fbbcdc07 AH |
1406 | } |
1407 | ||
1408 | return false; | |
1409 | } | |
1410 | #else /* CONFIG_ACPI not enabled */ | |
1411 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1412 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1413 | #endif /* CONFIG_ACPI */ |
1414 | ||
7791e4aa SP |
1415 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
1416 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
1417 | {} | |
1418 | }; | |
1419 | ||
93f0822d DB |
1420 | static int __init intel_pstate_init(void) |
1421 | { | |
907cc908 | 1422 | int cpu, rc = 0; |
93f0822d | 1423 | const struct x86_cpu_id *id; |
64df1fdf | 1424 | struct cpu_defaults *cpu_def; |
93f0822d | 1425 | |
6be26498 DB |
1426 | if (no_load) |
1427 | return -ENODEV; | |
1428 | ||
7791e4aa SP |
1429 | if (x86_match_cpu(hwp_support_ids) && !no_hwp) { |
1430 | copy_cpu_funcs(&core_params.funcs); | |
1431 | hwp_active++; | |
1432 | goto hwp_cpu_matched; | |
1433 | } | |
1434 | ||
93f0822d DB |
1435 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1436 | if (!id) | |
1437 | return -ENODEV; | |
1438 | ||
64df1fdf | 1439 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1440 | |
64df1fdf BP |
1441 | copy_pid_params(&cpu_def->pid_policy); |
1442 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1443 | |
b563b4e3 DB |
1444 | if (intel_pstate_msrs_not_valid()) |
1445 | return -ENODEV; | |
1446 | ||
7791e4aa SP |
1447 | hwp_cpu_matched: |
1448 | /* | |
1449 | * The Intel pstate driver will be ignored if the platform | |
1450 | * firmware has its own power management modes. | |
1451 | */ | |
1452 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1453 | return -ENODEV; | |
1454 | ||
93f0822d DB |
1455 | pr_info("Intel P-state driver initializing.\n"); |
1456 | ||
b57ffac5 | 1457 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1458 | if (!all_cpu_data) |
1459 | return -ENOMEM; | |
93f0822d | 1460 | |
d64c3b0b KCA |
1461 | if (!hwp_active && hwp_only) |
1462 | goto out; | |
1463 | ||
93f0822d DB |
1464 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1465 | if (rc) | |
1466 | goto out; | |
1467 | ||
1468 | intel_pstate_debug_expose_params(); | |
1469 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1470 | |
7791e4aa SP |
1471 | if (hwp_active) |
1472 | pr_info("intel_pstate: HWP enabled\n"); | |
1473 | ||
93f0822d DB |
1474 | return rc; |
1475 | out: | |
907cc908 DB |
1476 | get_online_cpus(); |
1477 | for_each_online_cpu(cpu) { | |
1478 | if (all_cpu_data[cpu]) { | |
bb6ab52f | 1479 | intel_pstate_clear_update_util_hook(cpu); |
907cc908 DB |
1480 | kfree(all_cpu_data[cpu]); |
1481 | } | |
1482 | } | |
1483 | ||
1484 | put_online_cpus(); | |
1485 | vfree(all_cpu_data); | |
93f0822d DB |
1486 | return -ENODEV; |
1487 | } | |
1488 | device_initcall(intel_pstate_init); | |
1489 | ||
6be26498 DB |
1490 | static int __init intel_pstate_setup(char *str) |
1491 | { | |
1492 | if (!str) | |
1493 | return -EINVAL; | |
1494 | ||
1495 | if (!strcmp(str, "disable")) | |
1496 | no_load = 1; | |
539342f6 PB |
1497 | if (!strcmp(str, "no_hwp")) { |
1498 | pr_info("intel_pstate: HWP disabled\n"); | |
2f86dc4c | 1499 | no_hwp = 1; |
539342f6 | 1500 | } |
aa4ea34d EZ |
1501 | if (!strcmp(str, "force")) |
1502 | force_load = 1; | |
d64c3b0b KCA |
1503 | if (!strcmp(str, "hwp_only")) |
1504 | hwp_only = 1; | |
6be26498 DB |
1505 | return 0; |
1506 | } | |
1507 | early_param("intel_pstate", intel_pstate_setup); | |
1508 | ||
93f0822d DB |
1509 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1510 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1511 | MODULE_LICENSE("GPL"); |