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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
93f0822d DB |
29 | #include <trace/events/power.h> |
30 | ||
31 | #include <asm/div64.h> | |
32 | #include <asm/msr.h> | |
33 | #include <asm/cpu_device_id.h> | |
34 | ||
35 | #define SAMPLE_COUNT 3 | |
36 | ||
61d8d2ab DB |
37 | #define BYT_RATIOS 0x66a |
38 | #define BYT_VIDS 0x66b | |
39 | #define BYT_TURBO_RATIOS 0x66c | |
21855ff5 | 40 | #define BYT_TURBO_VIDS 0x66d |
61d8d2ab | 41 | |
19e77c28 | 42 | |
e66c1768 | 43 | #define FRAC_BITS 6 |
93f0822d DB |
44 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
45 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
e66c1768 | 46 | #define FP_ROUNDUP(X) ((X) += 1 << FRAC_BITS) |
93f0822d DB |
47 | |
48 | static inline int32_t mul_fp(int32_t x, int32_t y) | |
49 | { | |
50 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
51 | } | |
52 | ||
53 | static inline int32_t div_fp(int32_t x, int32_t y) | |
54 | { | |
55 | return div_s64((int64_t)x << FRAC_BITS, (int64_t)y); | |
56 | } | |
57 | ||
58 | struct sample { | |
d253d2a5 | 59 | int32_t core_pct_busy; |
93f0822d DB |
60 | u64 aperf; |
61 | u64 mperf; | |
62 | int freq; | |
63 | }; | |
64 | ||
65 | struct pstate_data { | |
66 | int current_pstate; | |
67 | int min_pstate; | |
68 | int max_pstate; | |
69 | int turbo_pstate; | |
70 | }; | |
71 | ||
007bea09 | 72 | struct vid_data { |
21855ff5 DB |
73 | int min; |
74 | int max; | |
75 | int turbo; | |
007bea09 DB |
76 | int32_t ratio; |
77 | }; | |
78 | ||
93f0822d DB |
79 | struct _pid { |
80 | int setpoint; | |
81 | int32_t integral; | |
82 | int32_t p_gain; | |
83 | int32_t i_gain; | |
84 | int32_t d_gain; | |
85 | int deadband; | |
d253d2a5 | 86 | int32_t last_err; |
93f0822d DB |
87 | }; |
88 | ||
89 | struct cpudata { | |
90 | int cpu; | |
91 | ||
92 | char name[64]; | |
93 | ||
94 | struct timer_list timer; | |
95 | ||
93f0822d | 96 | struct pstate_data pstate; |
007bea09 | 97 | struct vid_data vid; |
93f0822d | 98 | struct _pid pid; |
93f0822d | 99 | |
93f0822d DB |
100 | u64 prev_aperf; |
101 | u64 prev_mperf; | |
d37e2b76 | 102 | struct sample sample; |
93f0822d DB |
103 | }; |
104 | ||
105 | static struct cpudata **all_cpu_data; | |
106 | struct pstate_adjust_policy { | |
107 | int sample_rate_ms; | |
108 | int deadband; | |
109 | int setpoint; | |
110 | int p_gain_pct; | |
111 | int d_gain_pct; | |
112 | int i_gain_pct; | |
113 | }; | |
114 | ||
016c8150 DB |
115 | struct pstate_funcs { |
116 | int (*get_max)(void); | |
117 | int (*get_min)(void); | |
118 | int (*get_turbo)(void); | |
007bea09 DB |
119 | void (*set)(struct cpudata*, int pstate); |
120 | void (*get_vid)(struct cpudata *); | |
93f0822d DB |
121 | }; |
122 | ||
016c8150 DB |
123 | struct cpu_defaults { |
124 | struct pstate_adjust_policy pid_policy; | |
125 | struct pstate_funcs funcs; | |
93f0822d DB |
126 | }; |
127 | ||
016c8150 DB |
128 | static struct pstate_adjust_policy pid_params; |
129 | static struct pstate_funcs pstate_funcs; | |
130 | ||
93f0822d DB |
131 | struct perf_limits { |
132 | int no_turbo; | |
133 | int max_perf_pct; | |
134 | int min_perf_pct; | |
135 | int32_t max_perf; | |
136 | int32_t min_perf; | |
d8f469e9 DB |
137 | int max_policy_pct; |
138 | int max_sysfs_pct; | |
93f0822d DB |
139 | }; |
140 | ||
141 | static struct perf_limits limits = { | |
142 | .no_turbo = 0, | |
143 | .max_perf_pct = 100, | |
144 | .max_perf = int_tofp(1), | |
145 | .min_perf_pct = 0, | |
146 | .min_perf = 0, | |
d8f469e9 DB |
147 | .max_policy_pct = 100, |
148 | .max_sysfs_pct = 100, | |
93f0822d DB |
149 | }; |
150 | ||
151 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, | |
152 | int deadband, int integral) { | |
153 | pid->setpoint = setpoint; | |
154 | pid->deadband = deadband; | |
155 | pid->integral = int_tofp(integral); | |
d98d099b | 156 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
157 | } |
158 | ||
159 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
160 | { | |
161 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
162 | } | |
163 | ||
164 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
165 | { | |
166 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
167 | } | |
168 | ||
169 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
170 | { | |
171 | ||
172 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
173 | } | |
174 | ||
d253d2a5 | 175 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 176 | { |
d253d2a5 | 177 | signed int result; |
93f0822d DB |
178 | int32_t pterm, dterm, fp_error; |
179 | int32_t integral_limit; | |
180 | ||
d253d2a5 | 181 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 182 | |
d253d2a5 | 183 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
184 | return 0; |
185 | ||
186 | pterm = mul_fp(pid->p_gain, fp_error); | |
187 | ||
188 | pid->integral += fp_error; | |
189 | ||
190 | /* limit the integral term */ | |
191 | integral_limit = int_tofp(30); | |
192 | if (pid->integral > integral_limit) | |
193 | pid->integral = integral_limit; | |
194 | if (pid->integral < -integral_limit) | |
195 | pid->integral = -integral_limit; | |
196 | ||
d253d2a5 BS |
197 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
198 | pid->last_err = fp_error; | |
93f0822d DB |
199 | |
200 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
201 | ||
202 | return (signed int)fp_toint(result); | |
203 | } | |
204 | ||
205 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
206 | { | |
016c8150 DB |
207 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
208 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
209 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d DB |
210 | |
211 | pid_reset(&cpu->pid, | |
016c8150 | 212 | pid_params.setpoint, |
93f0822d | 213 | 100, |
016c8150 | 214 | pid_params.deadband, |
93f0822d DB |
215 | 0); |
216 | } | |
217 | ||
93f0822d DB |
218 | static inline void intel_pstate_reset_all_pid(void) |
219 | { | |
220 | unsigned int cpu; | |
221 | for_each_online_cpu(cpu) { | |
222 | if (all_cpu_data[cpu]) | |
223 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
224 | } | |
225 | } | |
226 | ||
227 | /************************** debugfs begin ************************/ | |
228 | static int pid_param_set(void *data, u64 val) | |
229 | { | |
230 | *(u32 *)data = val; | |
231 | intel_pstate_reset_all_pid(); | |
232 | return 0; | |
233 | } | |
234 | static int pid_param_get(void *data, u64 *val) | |
235 | { | |
236 | *val = *(u32 *)data; | |
237 | return 0; | |
238 | } | |
239 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, | |
240 | pid_param_set, "%llu\n"); | |
241 | ||
242 | struct pid_param { | |
243 | char *name; | |
244 | void *value; | |
245 | }; | |
246 | ||
247 | static struct pid_param pid_files[] = { | |
016c8150 DB |
248 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
249 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
250 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
251 | {"deadband", &pid_params.deadband}, | |
252 | {"setpoint", &pid_params.setpoint}, | |
253 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
254 | {NULL, NULL} |
255 | }; | |
256 | ||
257 | static struct dentry *debugfs_parent; | |
258 | static void intel_pstate_debug_expose_params(void) | |
259 | { | |
260 | int i = 0; | |
261 | ||
262 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); | |
263 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
264 | return; | |
265 | while (pid_files[i].name) { | |
266 | debugfs_create_file(pid_files[i].name, 0660, | |
267 | debugfs_parent, pid_files[i].value, | |
268 | &fops_pid_param); | |
269 | i++; | |
270 | } | |
271 | } | |
272 | ||
273 | /************************** debugfs end ************************/ | |
274 | ||
275 | /************************** sysfs begin ************************/ | |
276 | #define show_one(file_name, object) \ | |
277 | static ssize_t show_##file_name \ | |
278 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
279 | { \ | |
280 | return sprintf(buf, "%u\n", limits.object); \ | |
281 | } | |
282 | ||
283 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, | |
284 | const char *buf, size_t count) | |
285 | { | |
286 | unsigned int input; | |
287 | int ret; | |
288 | ret = sscanf(buf, "%u", &input); | |
289 | if (ret != 1) | |
290 | return -EINVAL; | |
291 | limits.no_turbo = clamp_t(int, input, 0 , 1); | |
292 | ||
293 | return count; | |
294 | } | |
295 | ||
296 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
297 | const char *buf, size_t count) | |
298 | { | |
299 | unsigned int input; | |
300 | int ret; | |
301 | ret = sscanf(buf, "%u", &input); | |
302 | if (ret != 1) | |
303 | return -EINVAL; | |
304 | ||
d8f469e9 DB |
305 | limits.max_sysfs_pct = clamp_t(int, input, 0 , 100); |
306 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
93f0822d DB |
307 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
308 | return count; | |
309 | } | |
310 | ||
311 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
312 | const char *buf, size_t count) | |
313 | { | |
314 | unsigned int input; | |
315 | int ret; | |
316 | ret = sscanf(buf, "%u", &input); | |
317 | if (ret != 1) | |
318 | return -EINVAL; | |
319 | limits.min_perf_pct = clamp_t(int, input, 0 , 100); | |
320 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
321 | ||
322 | return count; | |
323 | } | |
324 | ||
325 | show_one(no_turbo, no_turbo); | |
326 | show_one(max_perf_pct, max_perf_pct); | |
327 | show_one(min_perf_pct, min_perf_pct); | |
328 | ||
329 | define_one_global_rw(no_turbo); | |
330 | define_one_global_rw(max_perf_pct); | |
331 | define_one_global_rw(min_perf_pct); | |
332 | ||
333 | static struct attribute *intel_pstate_attributes[] = { | |
334 | &no_turbo.attr, | |
335 | &max_perf_pct.attr, | |
336 | &min_perf_pct.attr, | |
337 | NULL | |
338 | }; | |
339 | ||
340 | static struct attribute_group intel_pstate_attr_group = { | |
341 | .attrs = intel_pstate_attributes, | |
342 | }; | |
343 | static struct kobject *intel_pstate_kobject; | |
344 | ||
345 | static void intel_pstate_sysfs_expose_params(void) | |
346 | { | |
347 | int rc; | |
348 | ||
349 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
350 | &cpu_subsys.dev_root->kobj); | |
351 | BUG_ON(!intel_pstate_kobject); | |
352 | rc = sysfs_create_group(intel_pstate_kobject, | |
353 | &intel_pstate_attr_group); | |
354 | BUG_ON(rc); | |
355 | } | |
356 | ||
357 | /************************** sysfs end ************************/ | |
19e77c28 DB |
358 | static int byt_get_min_pstate(void) |
359 | { | |
360 | u64 value; | |
361 | rdmsrl(BYT_RATIOS, value); | |
21855ff5 | 362 | return (value >> 8) & 0x3F; |
19e77c28 DB |
363 | } |
364 | ||
365 | static int byt_get_max_pstate(void) | |
366 | { | |
367 | u64 value; | |
368 | rdmsrl(BYT_RATIOS, value); | |
21855ff5 | 369 | return (value >> 16) & 0x3F; |
19e77c28 | 370 | } |
93f0822d | 371 | |
61d8d2ab DB |
372 | static int byt_get_turbo_pstate(void) |
373 | { | |
374 | u64 value; | |
375 | rdmsrl(BYT_TURBO_RATIOS, value); | |
376 | return value & 0x3F; | |
377 | } | |
378 | ||
007bea09 DB |
379 | static void byt_set_pstate(struct cpudata *cpudata, int pstate) |
380 | { | |
381 | u64 val; | |
382 | int32_t vid_fp; | |
383 | u32 vid; | |
384 | ||
385 | val = pstate << 8; | |
386 | if (limits.no_turbo) | |
387 | val |= (u64)1 << 32; | |
388 | ||
389 | vid_fp = cpudata->vid.min + mul_fp( | |
390 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
391 | cpudata->vid.ratio); | |
392 | ||
393 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
394 | vid = fp_toint(vid_fp); | |
395 | ||
21855ff5 DB |
396 | if (pstate > cpudata->pstate.max_pstate) |
397 | vid = cpudata->vid.turbo; | |
398 | ||
007bea09 DB |
399 | val |= vid; |
400 | ||
401 | wrmsrl(MSR_IA32_PERF_CTL, val); | |
402 | } | |
403 | ||
404 | static void byt_get_vid(struct cpudata *cpudata) | |
405 | { | |
406 | u64 value; | |
407 | ||
21855ff5 | 408 | |
007bea09 | 409 | rdmsrl(BYT_VIDS, value); |
21855ff5 DB |
410 | cpudata->vid.min = int_tofp((value >> 8) & 0x3f); |
411 | cpudata->vid.max = int_tofp((value >> 16) & 0x3f); | |
007bea09 DB |
412 | cpudata->vid.ratio = div_fp( |
413 | cpudata->vid.max - cpudata->vid.min, | |
414 | int_tofp(cpudata->pstate.max_pstate - | |
415 | cpudata->pstate.min_pstate)); | |
21855ff5 DB |
416 | |
417 | rdmsrl(BYT_TURBO_VIDS, value); | |
418 | cpudata->vid.turbo = value & 0x7f; | |
007bea09 DB |
419 | } |
420 | ||
421 | ||
016c8150 | 422 | static int core_get_min_pstate(void) |
93f0822d DB |
423 | { |
424 | u64 value; | |
05e99c8c | 425 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
426 | return (value >> 40) & 0xFF; |
427 | } | |
428 | ||
016c8150 | 429 | static int core_get_max_pstate(void) |
93f0822d DB |
430 | { |
431 | u64 value; | |
05e99c8c | 432 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
433 | return (value >> 8) & 0xFF; |
434 | } | |
435 | ||
016c8150 | 436 | static int core_get_turbo_pstate(void) |
93f0822d DB |
437 | { |
438 | u64 value; | |
439 | int nont, ret; | |
05e99c8c | 440 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 441 | nont = core_get_max_pstate(); |
93f0822d DB |
442 | ret = ((value) & 255); |
443 | if (ret <= nont) | |
444 | ret = nont; | |
445 | return ret; | |
446 | } | |
447 | ||
007bea09 | 448 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
449 | { |
450 | u64 val; | |
451 | ||
452 | val = pstate << 8; | |
453 | if (limits.no_turbo) | |
454 | val |= (u64)1 << 32; | |
455 | ||
bb18008f | 456 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
457 | } |
458 | ||
459 | static struct cpu_defaults core_params = { | |
460 | .pid_policy = { | |
461 | .sample_rate_ms = 10, | |
462 | .deadband = 0, | |
463 | .setpoint = 97, | |
464 | .p_gain_pct = 20, | |
465 | .d_gain_pct = 0, | |
466 | .i_gain_pct = 0, | |
467 | }, | |
468 | .funcs = { | |
469 | .get_max = core_get_max_pstate, | |
470 | .get_min = core_get_min_pstate, | |
471 | .get_turbo = core_get_turbo_pstate, | |
472 | .set = core_set_pstate, | |
473 | }, | |
474 | }; | |
475 | ||
19e77c28 DB |
476 | static struct cpu_defaults byt_params = { |
477 | .pid_policy = { | |
478 | .sample_rate_ms = 10, | |
479 | .deadband = 0, | |
480 | .setpoint = 97, | |
481 | .p_gain_pct = 14, | |
482 | .d_gain_pct = 0, | |
483 | .i_gain_pct = 4, | |
484 | }, | |
485 | .funcs = { | |
486 | .get_max = byt_get_max_pstate, | |
487 | .get_min = byt_get_min_pstate, | |
61d8d2ab | 488 | .get_turbo = byt_get_turbo_pstate, |
007bea09 DB |
489 | .set = byt_set_pstate, |
490 | .get_vid = byt_get_vid, | |
19e77c28 DB |
491 | }, |
492 | }; | |
493 | ||
494 | ||
93f0822d DB |
495 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
496 | { | |
497 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 498 | int max_perf_adj; |
93f0822d DB |
499 | int min_perf; |
500 | if (limits.no_turbo) | |
501 | max_perf = cpu->pstate.max_pstate; | |
502 | ||
7244cb62 DB |
503 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf)); |
504 | *max = clamp_t(int, max_perf_adj, | |
93f0822d DB |
505 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); |
506 | ||
507 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf)); | |
508 | *min = clamp_t(int, min_perf, | |
509 | cpu->pstate.min_pstate, max_perf); | |
510 | } | |
511 | ||
512 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate) | |
513 | { | |
514 | int max_perf, min_perf; | |
515 | ||
516 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); | |
517 | ||
518 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
519 | ||
520 | if (pstate == cpu->pstate.current_pstate) | |
521 | return; | |
522 | ||
93f0822d | 523 | trace_cpu_frequency(pstate * 100000, cpu->cpu); |
35363e94 | 524 | |
93f0822d | 525 | cpu->pstate.current_pstate = pstate; |
93f0822d | 526 | |
007bea09 | 527 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
528 | } |
529 | ||
530 | static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps) | |
531 | { | |
532 | int target; | |
533 | target = cpu->pstate.current_pstate + steps; | |
534 | ||
535 | intel_pstate_set_pstate(cpu, target); | |
536 | } | |
537 | ||
538 | static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps) | |
539 | { | |
540 | int target; | |
541 | target = cpu->pstate.current_pstate - steps; | |
542 | intel_pstate_set_pstate(cpu, target); | |
543 | } | |
544 | ||
545 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) | |
546 | { | |
547 | sprintf(cpu->name, "Intel 2nd generation core"); | |
548 | ||
016c8150 DB |
549 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
550 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
551 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); | |
93f0822d | 552 | |
007bea09 DB |
553 | if (pstate_funcs.get_vid) |
554 | pstate_funcs.get_vid(cpu); | |
d40a63c4 | 555 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
93f0822d DB |
556 | } |
557 | ||
558 | static inline void intel_pstate_calc_busy(struct cpudata *cpu, | |
559 | struct sample *sample) | |
560 | { | |
e66c1768 | 561 | int32_t core_pct; |
93f0822d | 562 | |
e66c1768 DB |
563 | core_pct = div_fp(int_tofp((sample->aperf)), |
564 | int_tofp((sample->mperf))); | |
565 | core_pct = mul_fp(core_pct, int_tofp(100)); | |
566 | FP_ROUNDUP(core_pct); | |
567 | ||
fcb6a15c | 568 | sample->freq = fp_toint( |
e66c1768 | 569 | mul_fp(int_tofp(cpu->pstate.max_pstate * 1000), core_pct)); |
fcb6a15c | 570 | |
adacdf3f | 571 | sample->core_pct_busy = core_pct; |
93f0822d DB |
572 | } |
573 | ||
574 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
575 | { | |
93f0822d DB |
576 | u64 aperf, mperf; |
577 | ||
93f0822d DB |
578 | rdmsrl(MSR_IA32_APERF, aperf); |
579 | rdmsrl(MSR_IA32_MPERF, mperf); | |
b69880f9 | 580 | |
e66c1768 DB |
581 | aperf = aperf >> FRAC_BITS; |
582 | mperf = mperf >> FRAC_BITS; | |
e66c1768 | 583 | |
d37e2b76 DB |
584 | cpu->sample.aperf = aperf; |
585 | cpu->sample.mperf = mperf; | |
d37e2b76 DB |
586 | cpu->sample.aperf -= cpu->prev_aperf; |
587 | cpu->sample.mperf -= cpu->prev_mperf; | |
1abc4b20 | 588 | |
d37e2b76 | 589 | intel_pstate_calc_busy(cpu, &cpu->sample); |
93f0822d | 590 | |
93f0822d DB |
591 | cpu->prev_aperf = aperf; |
592 | cpu->prev_mperf = mperf; | |
593 | } | |
594 | ||
595 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) | |
596 | { | |
597 | int sample_time, delay; | |
598 | ||
016c8150 | 599 | sample_time = pid_params.sample_rate_ms; |
93f0822d | 600 | delay = msecs_to_jiffies(sample_time); |
93f0822d DB |
601 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
602 | } | |
603 | ||
d253d2a5 | 604 | static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu) |
93f0822d | 605 | { |
2134ed4d | 606 | int32_t core_busy, max_pstate, current_pstate; |
93f0822d | 607 | |
d37e2b76 | 608 | core_busy = cpu->sample.core_pct_busy; |
2134ed4d | 609 | max_pstate = int_tofp(cpu->pstate.max_pstate); |
93f0822d | 610 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 DB |
611 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
612 | return FP_ROUNDUP(core_busy); | |
93f0822d DB |
613 | } |
614 | ||
615 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
616 | { | |
d253d2a5 | 617 | int32_t busy_scaled; |
93f0822d DB |
618 | struct _pid *pid; |
619 | signed int ctl = 0; | |
620 | int steps; | |
621 | ||
622 | pid = &cpu->pid; | |
623 | busy_scaled = intel_pstate_get_scaled_busy(cpu); | |
624 | ||
625 | ctl = pid_calc(pid, busy_scaled); | |
626 | ||
627 | steps = abs(ctl); | |
b69880f9 | 628 | |
93f0822d DB |
629 | if (ctl < 0) |
630 | intel_pstate_pstate_increase(cpu, steps); | |
631 | else | |
632 | intel_pstate_pstate_decrease(cpu, steps); | |
633 | } | |
634 | ||
93f0822d DB |
635 | static void intel_pstate_timer_func(unsigned long __data) |
636 | { | |
637 | struct cpudata *cpu = (struct cpudata *) __data; | |
b69880f9 | 638 | struct sample *sample; |
93f0822d DB |
639 | |
640 | intel_pstate_sample(cpu); | |
b69880f9 | 641 | |
d37e2b76 | 642 | sample = &cpu->sample; |
b69880f9 | 643 | |
ca182aee | 644 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 DB |
645 | |
646 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
647 | fp_toint(intel_pstate_get_scaled_busy(cpu)), | |
648 | cpu->pstate.current_pstate, | |
649 | sample->mperf, | |
650 | sample->aperf, | |
b69880f9 DB |
651 | sample->freq); |
652 | ||
93f0822d DB |
653 | intel_pstate_set_sample_time(cpu); |
654 | } | |
655 | ||
656 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
657 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
658 | (unsigned long)&policy } | |
93f0822d DB |
659 | |
660 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
661 | ICPU(0x2a, core_params), |
662 | ICPU(0x2d, core_params), | |
19e77c28 | 663 | ICPU(0x37, byt_params), |
016c8150 DB |
664 | ICPU(0x3a, core_params), |
665 | ICPU(0x3c, core_params), | |
666 | ICPU(0x3e, core_params), | |
667 | ICPU(0x3f, core_params), | |
668 | ICPU(0x45, core_params), | |
669 | ICPU(0x46, core_params), | |
93f0822d DB |
670 | {} |
671 | }; | |
672 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
673 | ||
674 | static int intel_pstate_init_cpu(unsigned int cpunum) | |
675 | { | |
676 | ||
677 | const struct x86_cpu_id *id; | |
678 | struct cpudata *cpu; | |
679 | ||
680 | id = x86_match_cpu(intel_pstate_cpu_ids); | |
681 | if (!id) | |
682 | return -ENODEV; | |
683 | ||
684 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL); | |
685 | if (!all_cpu_data[cpunum]) | |
686 | return -ENOMEM; | |
687 | ||
688 | cpu = all_cpu_data[cpunum]; | |
689 | ||
690 | intel_pstate_get_cpu_pstates(cpu); | |
691 | ||
692 | cpu->cpu = cpunum; | |
016c8150 | 693 | |
93f0822d DB |
694 | init_timer_deferrable(&cpu->timer); |
695 | cpu->timer.function = intel_pstate_timer_func; | |
696 | cpu->timer.data = | |
697 | (unsigned long)cpu; | |
698 | cpu->timer.expires = jiffies + HZ/100; | |
699 | intel_pstate_busy_pid_reset(cpu); | |
93f0822d | 700 | intel_pstate_sample(cpu); |
93f0822d DB |
701 | |
702 | add_timer_on(&cpu->timer, cpunum); | |
703 | ||
704 | pr_info("Intel pstate controlling: cpu %d\n", cpunum); | |
705 | ||
706 | return 0; | |
707 | } | |
708 | ||
709 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
710 | { | |
711 | struct sample *sample; | |
712 | struct cpudata *cpu; | |
713 | ||
714 | cpu = all_cpu_data[cpu_num]; | |
715 | if (!cpu) | |
716 | return 0; | |
d37e2b76 | 717 | sample = &cpu->sample; |
93f0822d DB |
718 | return sample->freq; |
719 | } | |
720 | ||
721 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
722 | { | |
723 | struct cpudata *cpu; | |
93f0822d DB |
724 | |
725 | cpu = all_cpu_data[policy->cpu]; | |
726 | ||
d3929b83 DB |
727 | if (!policy->cpuinfo.max_freq) |
728 | return -ENODEV; | |
729 | ||
93f0822d DB |
730 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { |
731 | limits.min_perf_pct = 100; | |
732 | limits.min_perf = int_tofp(1); | |
733 | limits.max_perf_pct = 100; | |
734 | limits.max_perf = int_tofp(1); | |
735 | limits.no_turbo = 0; | |
d1b68485 | 736 | return 0; |
93f0822d | 737 | } |
d1b68485 SP |
738 | limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
739 | limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100); | |
740 | limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100)); | |
741 | ||
d8f469e9 DB |
742 | limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq; |
743 | limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100); | |
744 | limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct); | |
d1b68485 | 745 | limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100)); |
93f0822d DB |
746 | |
747 | return 0; | |
748 | } | |
749 | ||
750 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
751 | { | |
be49e346 | 752 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d DB |
753 | |
754 | if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) && | |
755 | (policy->policy != CPUFREQ_POLICY_PERFORMANCE)) | |
756 | return -EINVAL; | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
bb18008f | 761 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 762 | { |
bb18008f DB |
763 | int cpu_num = policy->cpu; |
764 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 765 | |
bb18008f DB |
766 | pr_info("intel_pstate CPU %d exiting\n", cpu_num); |
767 | ||
c2294a2f | 768 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
bb18008f DB |
769 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate); |
770 | kfree(all_cpu_data[cpu_num]); | |
771 | all_cpu_data[cpu_num] = NULL; | |
93f0822d DB |
772 | } |
773 | ||
2760984f | 774 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 775 | { |
93f0822d | 776 | struct cpudata *cpu; |
52e0a509 | 777 | int rc; |
93f0822d DB |
778 | |
779 | rc = intel_pstate_init_cpu(policy->cpu); | |
780 | if (rc) | |
781 | return rc; | |
782 | ||
783 | cpu = all_cpu_data[policy->cpu]; | |
784 | ||
785 | if (!limits.no_turbo && | |
786 | limits.min_perf_pct == 100 && limits.max_perf_pct == 100) | |
787 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; | |
788 | else | |
789 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
790 | ||
52e0a509 DB |
791 | policy->min = cpu->pstate.min_pstate * 100000; |
792 | policy->max = cpu->pstate.turbo_pstate * 100000; | |
93f0822d DB |
793 | |
794 | /* cpuinfo and default policy values */ | |
795 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * 100000; | |
796 | policy->cpuinfo.max_freq = cpu->pstate.turbo_pstate * 100000; | |
797 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | |
798 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
799 | ||
800 | return 0; | |
801 | } | |
802 | ||
803 | static struct cpufreq_driver intel_pstate_driver = { | |
804 | .flags = CPUFREQ_CONST_LOOPS, | |
805 | .verify = intel_pstate_verify_policy, | |
806 | .setpolicy = intel_pstate_set_policy, | |
807 | .get = intel_pstate_get, | |
808 | .init = intel_pstate_cpu_init, | |
bb18008f | 809 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 810 | .name = "intel_pstate", |
93f0822d DB |
811 | }; |
812 | ||
6be26498 DB |
813 | static int __initdata no_load; |
814 | ||
b563b4e3 DB |
815 | static int intel_pstate_msrs_not_valid(void) |
816 | { | |
817 | /* Check that all the msr's we are using are valid. */ | |
818 | u64 aperf, mperf, tmp; | |
819 | ||
820 | rdmsrl(MSR_IA32_APERF, aperf); | |
821 | rdmsrl(MSR_IA32_MPERF, mperf); | |
822 | ||
016c8150 DB |
823 | if (!pstate_funcs.get_max() || |
824 | !pstate_funcs.get_min() || | |
825 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
826 | return -ENODEV; |
827 | ||
828 | rdmsrl(MSR_IA32_APERF, tmp); | |
829 | if (!(tmp - aperf)) | |
830 | return -ENODEV; | |
831 | ||
832 | rdmsrl(MSR_IA32_MPERF, tmp); | |
833 | if (!(tmp - mperf)) | |
834 | return -ENODEV; | |
835 | ||
836 | return 0; | |
837 | } | |
016c8150 | 838 | |
e0a261a2 | 839 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
840 | { |
841 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
842 | pid_params.p_gain_pct = policy->p_gain_pct; | |
843 | pid_params.i_gain_pct = policy->i_gain_pct; | |
844 | pid_params.d_gain_pct = policy->d_gain_pct; | |
845 | pid_params.deadband = policy->deadband; | |
846 | pid_params.setpoint = policy->setpoint; | |
847 | } | |
848 | ||
e0a261a2 | 849 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
850 | { |
851 | pstate_funcs.get_max = funcs->get_max; | |
852 | pstate_funcs.get_min = funcs->get_min; | |
853 | pstate_funcs.get_turbo = funcs->get_turbo; | |
854 | pstate_funcs.set = funcs->set; | |
007bea09 | 855 | pstate_funcs.get_vid = funcs->get_vid; |
016c8150 DB |
856 | } |
857 | ||
fbbcdc07 AH |
858 | #if IS_ENABLED(CONFIG_ACPI) |
859 | #include <acpi/processor.h> | |
860 | ||
861 | static bool intel_pstate_no_acpi_pss(void) | |
862 | { | |
863 | int i; | |
864 | ||
865 | for_each_possible_cpu(i) { | |
866 | acpi_status status; | |
867 | union acpi_object *pss; | |
868 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
869 | struct acpi_processor *pr = per_cpu(processors, i); | |
870 | ||
871 | if (!pr) | |
872 | continue; | |
873 | ||
874 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
875 | if (ACPI_FAILURE(status)) | |
876 | continue; | |
877 | ||
878 | pss = buffer.pointer; | |
879 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
880 | kfree(pss); | |
881 | return false; | |
882 | } | |
883 | ||
884 | kfree(pss); | |
885 | } | |
886 | ||
887 | return true; | |
888 | } | |
889 | ||
890 | struct hw_vendor_info { | |
891 | u16 valid; | |
892 | char oem_id[ACPI_OEM_ID_SIZE]; | |
893 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
894 | }; | |
895 | ||
896 | /* Hardware vendor-specific info that has its own power management modes */ | |
897 | static struct hw_vendor_info vendor_info[] = { | |
898 | {1, "HP ", "ProLiant"}, | |
899 | {0, "", ""}, | |
900 | }; | |
901 | ||
902 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
903 | { | |
904 | struct acpi_table_header hdr; | |
905 | struct hw_vendor_info *v_info; | |
906 | ||
907 | if (acpi_disabled | |
908 | || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
909 | return false; | |
910 | ||
911 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
912 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) | |
913 | && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) | |
914 | && intel_pstate_no_acpi_pss()) | |
915 | return true; | |
916 | } | |
917 | ||
918 | return false; | |
919 | } | |
920 | #else /* CONFIG_ACPI not enabled */ | |
921 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
922 | #endif /* CONFIG_ACPI */ | |
923 | ||
93f0822d DB |
924 | static int __init intel_pstate_init(void) |
925 | { | |
907cc908 | 926 | int cpu, rc = 0; |
93f0822d | 927 | const struct x86_cpu_id *id; |
016c8150 | 928 | struct cpu_defaults *cpu_info; |
93f0822d | 929 | |
6be26498 DB |
930 | if (no_load) |
931 | return -ENODEV; | |
932 | ||
93f0822d DB |
933 | id = x86_match_cpu(intel_pstate_cpu_ids); |
934 | if (!id) | |
935 | return -ENODEV; | |
936 | ||
fbbcdc07 AH |
937 | /* |
938 | * The Intel pstate driver will be ignored if the platform | |
939 | * firmware has its own power management modes. | |
940 | */ | |
941 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
942 | return -ENODEV; | |
943 | ||
016c8150 DB |
944 | cpu_info = (struct cpu_defaults *)id->driver_data; |
945 | ||
946 | copy_pid_params(&cpu_info->pid_policy); | |
947 | copy_cpu_funcs(&cpu_info->funcs); | |
948 | ||
b563b4e3 DB |
949 | if (intel_pstate_msrs_not_valid()) |
950 | return -ENODEV; | |
951 | ||
93f0822d DB |
952 | pr_info("Intel P-state driver initializing.\n"); |
953 | ||
b57ffac5 | 954 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
955 | if (!all_cpu_data) |
956 | return -ENOMEM; | |
93f0822d DB |
957 | |
958 | rc = cpufreq_register_driver(&intel_pstate_driver); | |
959 | if (rc) | |
960 | goto out; | |
961 | ||
962 | intel_pstate_debug_expose_params(); | |
963 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 964 | |
93f0822d DB |
965 | return rc; |
966 | out: | |
907cc908 DB |
967 | get_online_cpus(); |
968 | for_each_online_cpu(cpu) { | |
969 | if (all_cpu_data[cpu]) { | |
970 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
971 | kfree(all_cpu_data[cpu]); | |
972 | } | |
973 | } | |
974 | ||
975 | put_online_cpus(); | |
976 | vfree(all_cpu_data); | |
93f0822d DB |
977 | return -ENODEV; |
978 | } | |
979 | device_initcall(intel_pstate_init); | |
980 | ||
6be26498 DB |
981 | static int __init intel_pstate_setup(char *str) |
982 | { | |
983 | if (!str) | |
984 | return -EINVAL; | |
985 | ||
986 | if (!strcmp(str, "disable")) | |
987 | no_load = 1; | |
988 | return 0; | |
989 | } | |
990 | early_param("intel_pstate", intel_pstate_setup); | |
991 | ||
93f0822d DB |
992 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
993 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
994 | MODULE_LICENSE("GPL"); |