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cpufreq: dt: Add support for APM X-Gene 2
[mirror_ubuntu-zesty-kernel.git] / drivers / cpufreq / intel_pstate.c
CommitLineData
93f0822d 1/*
d1b68485 2 * intel_pstate.c: Native P state management for Intel processors
93f0822d
DB		 3 *
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 */
12
4836df17
JP		 13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
93f0822d
DB		 15#include <linux/kernel.h>
16#include <linux/kernel_stat.h>
17#include <linux/module.h>
18#include <linux/ktime.h>
19#include <linux/hrtimer.h>
20#include <linux/tick.h>
21#include <linux/slab.h>
22#include <linux/sched.h>
23#include <linux/list.h>
24#include <linux/cpu.h>
25#include <linux/cpufreq.h>
26#include <linux/sysfs.h>
27#include <linux/types.h>
28#include <linux/fs.h>
29#include <linux/debugfs.h>
fbbcdc07 30#include <linux/acpi.h>
d6472302 31#include <linux/vmalloc.h>
93f0822d
DB		 32#include <trace/events/power.h>
33
34#include <asm/div64.h>
35#include <asm/msr.h>
36#include <asm/cpu_device_id.h>
64df1fdf 37#include <asm/cpufeature.h>
5b20c944 38#include <asm/intel-family.h>
93f0822d 39
001c76f0
RW		 40#define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41
938d21a2
PL		 42#define ATOM_RATIOS 0x66a
43#define ATOM_VIDS 0x66b
44#define ATOM_TURBO_RATIOS 0x66c
45#define ATOM_TURBO_VIDS 0x66d
61d8d2ab 46
9522a2ff
SP		 47#ifdef CONFIG_ACPI
48#include <acpi/processor.h>
49#endif
50
f0fe3cd7 51#define FRAC_BITS 8
93f0822d
DB		 52#define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
53#define fp_toint(X) ((X) >> FRAC_BITS)
f0fe3cd7 54
a1c9787d
RW		 55#define EXT_BITS 6
56#define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
d5dd33d9
SP		 57#define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58#define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
a1c9787d 59
93f0822d
DB		 60static inline int32_t mul_fp(int32_t x, int32_t y)
61{
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63}
64
7180dddf 65static inline int32_t div_fp(s64 x, s64 y)
93f0822d 66{
7180dddf 67 return div64_s64((int64_t)x << FRAC_BITS, y);
93f0822d
DB		 68}
69
d022a65e
DB		 70static inline int ceiling_fp(int32_t x)
71{
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79}
80
a1c9787d
RW		 81static inline u64 mul_ext_fp(u64 x, u64 y)
82{
83 return (x * y) >> EXT_FRAC_BITS;
84}
85
86static inline u64 div_ext_fp(u64 x, u64 y)
87{
88 return div64_u64(x << EXT_FRAC_BITS, y);
89}
90
13ad7701
SP		 91/**
92 * struct sample - Store performance sample
a1c9787d 93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
13ad7701
SP		 94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
a1c9787d 96 * P state. This can be different than core_avg_perf
13ad7701
SP		 97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
103 * current sample
13ad7701
SP		 104 * @time: Current time from scheduler
105 *
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
108 */
93f0822d 109struct sample {
a1c9787d 110 int32_t core_avg_perf;
157386b6 111 int32_t busy_scaled;
93f0822d
DB		 112 u64 aperf;
113 u64 mperf;
4055fad3 114 u64 tsc;
a4675fbc 115 u64 time;
93f0822d
DB		 116};
117
13ad7701
SP		 118/**
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @scaling: Scaling factor to convert frequency to cpufreq
127 * frequency units
128 * @turbo_pstate: Max Turbo P state possible for this platform
001c76f0
RW		 129 * @max_freq: @max_pstate frequency in cpufreq units
130 * @turbo_freq: @turbo_pstate frequency in cpufreq units
13ad7701
SP		 131 *
132 * Stores the per cpu model P state limits and current P state.
133 */
93f0822d
DB		 134struct pstate_data {
135 int current_pstate;
136 int min_pstate;
137 int max_pstate;
3bcc6fa9 138 int max_pstate_physical;
b27580b0 139 int scaling;
93f0822d 140 int turbo_pstate;
001c76f0
RW		 141 unsigned int max_freq;
142 unsigned int turbo_freq;
93f0822d
DB		 143};
144
13ad7701
SP		 145/**
146 * struct vid_data - Stores voltage information data
147 * @min: VID data for this platform corresponding to
148 * the lowest P state
149 * @max: VID data corresponding to the highest P State.
150 * @turbo: VID data for turbo P state
151 * @ratio: Ratio of (vid max - vid min) /
152 * (max P state - Min P State)
153 *
154 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
155 * This data is used in Atom platforms, where in addition to target P state,
156 * the voltage data needs to be specified to select next P State.
157 */
007bea09 158struct vid_data {
21855ff5
DB		 159 int min;
160 int max;
161 int turbo;
007bea09
DB		 162 int32_t ratio;
163};
164
13ad7701
SP		 165/**
166 * struct _pid - Stores PID data
167 * @setpoint: Target set point for busyness or performance
168 * @integral: Storage for accumulated error values
169 * @p_gain: PID proportional gain
170 * @i_gain: PID integral gain
171 * @d_gain: PID derivative gain
172 * @deadband: PID deadband
173 * @last_err: Last error storage for integral part of PID calculation
174 *
175 * Stores PID coefficients and last error for PID controller.
176 */
93f0822d
DB		 177struct _pid {
178 int setpoint;
179 int32_t integral;
180 int32_t p_gain;
181 int32_t i_gain;
182 int32_t d_gain;
183 int deadband;
d253d2a5 184 int32_t last_err;
93f0822d
DB		 185};
186
eae48f04
SP		 187/**
188 * struct perf_limits - Store user and policy limits
189 * @no_turbo: User requested turbo state from intel_pstate sysfs
190 * @turbo_disabled: Platform turbo status either from msr
191 * MSR_IA32_MISC_ENABLE or when maximum available pstate
192 * matches the maximum turbo pstate
193 * @max_perf_pct: Effective maximum performance limit in percentage, this
194 * is minimum of either limits enforced by cpufreq policy
195 * or limits from user set limits via intel_pstate sysfs
196 * @min_perf_pct: Effective minimum performance limit in percentage, this
197 * is maximum of either limits enforced by cpufreq policy
198 * or limits from user set limits via intel_pstate sysfs
199 * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct
200 * This value is used to limit max pstate
201 * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct
202 * This value is used to limit min pstate
203 * @max_policy_pct: The maximum performance in percentage enforced by
204 * cpufreq setpolicy interface
205 * @max_sysfs_pct: The maximum performance in percentage enforced by
206 * intel pstate sysfs interface, unused when per cpu
207 * controls are enforced
208 * @min_policy_pct: The minimum performance in percentage enforced by
209 * cpufreq setpolicy interface
210 * @min_sysfs_pct: The minimum performance in percentage enforced by
211 * intel pstate sysfs interface, unused when per cpu
212 * controls are enforced
213 *
214 * Storage for user and policy defined limits.
215 */
216struct perf_limits {
217 int no_turbo;
218 int turbo_disabled;
219 int max_perf_pct;
220 int min_perf_pct;
221 int32_t max_perf;
222 int32_t min_perf;
223 int max_policy_pct;
224 int max_sysfs_pct;
225 int min_policy_pct;
226 int min_sysfs_pct;
227};
228
13ad7701
SP		 229/**
230 * struct cpudata - Per CPU instance data storage
231 * @cpu: CPU number for this instance data
2f1d407a 232 * @policy: CPUFreq policy value
13ad7701 233 * @update_util: CPUFreq utility callback information
4578ee7e 234 * @update_util_set: CPUFreq utility callback is set
09c448d3
RW		 235 * @iowait_boost: iowait-related boost fraction
236 * @last_update: Time of the last update.
13ad7701
SP		 237 * @pstate: Stores P state limits for this CPU
238 * @vid: Stores VID limits for this CPU
239 * @pid: Stores PID parameters for this CPU
240 * @last_sample_time: Last Sample time
241 * @prev_aperf: Last APERF value read from APERF MSR
242 * @prev_mperf: Last MPERF value read from MPERF MSR
243 * @prev_tsc: Last timestamp counter (TSC) value
244 * @prev_cummulative_iowait: IO Wait time difference from last and
245 * current sample
246 * @sample: Storage for storing last Sample data
eae48f04
SP		 247 * @perf_limits: Pointer to perf_limit unique to this CPU
248 * Not all field in the structure are applicable
249 * when per cpu controls are enforced
9522a2ff
SP		 250 * @acpi_perf_data: Stores ACPI perf information read from _PSS
251 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
984edbdc
SP		 252 * @epp_powersave: Last saved HWP energy performance preference
253 * (EPP) or energy performance bias (EPB),
254 * when policy switched to performance
8442885f 255 * @epp_policy: Last saved policy used to set EPP/EPB
984edbdc
SP		 256 * @epp_default: Power on default HWP energy performance
257 * preference/bias
258 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
259 * operation
13ad7701
SP		 260 *
261 * This structure stores per CPU instance data for all CPUs.
262 */
93f0822d
DB		 263struct cpudata {
264 int cpu;
265
2f1d407a 266 unsigned int policy;
a4675fbc 267 struct update_util_data update_util;
4578ee7e 268 bool update_util_set;
93f0822d 269
93f0822d 270 struct pstate_data pstate;
007bea09 271 struct vid_data vid;
93f0822d 272 struct _pid pid;
93f0822d 273
09c448d3 274 u64 last_update;
a4675fbc 275 u64 last_sample_time;
93f0822d
DB		 276 u64 prev_aperf;
277 u64 prev_mperf;
4055fad3 278 u64 prev_tsc;
63d1d656 279 u64 prev_cummulative_iowait;
d37e2b76 280 struct sample sample;
eae48f04 281 struct perf_limits *perf_limits;
9522a2ff
SP		 282#ifdef CONFIG_ACPI
283 struct acpi_processor_performance acpi_perf_data;
284 bool valid_pss_table;
285#endif
09c448d3 286 unsigned int iowait_boost;
984edbdc 287 s16 epp_powersave;
8442885f 288 s16 epp_policy;
984edbdc
SP		 289 s16 epp_default;
290 s16 epp_saved;
93f0822d
DB		 291};
292
293static struct cpudata **all_cpu_data;
13ad7701
SP		 294
295/**
3954517e 296 * struct pstate_adjust_policy - Stores static PID configuration data
13ad7701
SP		 297 * @sample_rate_ms: PID calculation sample rate in ms
298 * @sample_rate_ns: Sample rate calculation in ns
299 * @deadband: PID deadband
300 * @setpoint: PID Setpoint
301 * @p_gain_pct: PID proportional gain
302 * @i_gain_pct: PID integral gain
303 * @d_gain_pct: PID derivative gain
304 *
305 * Stores per CPU model static PID configuration data.
306 */
93f0822d
DB		 307struct pstate_adjust_policy {
308 int sample_rate_ms;
a4675fbc 309 s64 sample_rate_ns;
93f0822d
DB		 310 int deadband;
311 int setpoint;
312 int p_gain_pct;
313 int d_gain_pct;
314 int i_gain_pct;
315};
316
13ad7701
SP		 317/**
318 * struct pstate_funcs - Per CPU model specific callbacks
319 * @get_max: Callback to get maximum non turbo effective P state
320 * @get_max_physical: Callback to get maximum non turbo physical P state
321 * @get_min: Callback to get minimum P state
322 * @get_turbo: Callback to get turbo P state
323 * @get_scaling: Callback to get frequency scaling factor
324 * @get_val: Callback to convert P state to actual MSR write value
325 * @get_vid: Callback to get VID data for Atom platforms
326 * @get_target_pstate: Callback to a function to calculate next P state to use
327 *
328 * Core and Atom CPU models have different way to get P State limits. This
329 * structure is used to store those callbacks.
330 */
016c8150
DB		 331struct pstate_funcs {
332 int (*get_max)(void);
3bcc6fa9 333 int (*get_max_physical)(void);
016c8150
DB		 334 int (*get_min)(void);
335 int (*get_turbo)(void);
b27580b0 336 int (*get_scaling)(void);
fdfdb2b1 337 u64 (*get_val)(struct cpudata*, int pstate);
007bea09 338 void (*get_vid)(struct cpudata *);
157386b6 339 int32_t (*get_target_pstate)(struct cpudata *);
93f0822d
DB		 340};
341
13ad7701
SP		 342/**
343 * struct cpu_defaults- Per CPU model default config data
344 * @pid_policy: PID config data
345 * @funcs: Callback function data
346 */
016c8150
DB		 347struct cpu_defaults {
348 struct pstate_adjust_policy pid_policy;
349 struct pstate_funcs funcs;
93f0822d
DB		 350};
351
157386b6 352static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
e70eed2b 353static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
157386b6 354
4a7cb7a9
JZ		 355static struct pstate_adjust_policy pid_params __read_mostly;
356static struct pstate_funcs pstate_funcs __read_mostly;
357static int hwp_active __read_mostly;
eae48f04 358static bool per_cpu_limits __read_mostly;
016c8150 359
9522a2ff
SP		 360#ifdef CONFIG_ACPI
361static bool acpi_ppc;
362#endif
13ad7701 363
51443fbf
PB		 364static struct perf_limits performance_limits = {
365 .no_turbo = 0,
366 .turbo_disabled = 0,
367 .max_perf_pct = 100,
d5dd33d9 368 .max_perf = int_ext_tofp(1),
51443fbf 369 .min_perf_pct = 100,
d5dd33d9 370 .min_perf = int_ext_tofp(1),
51443fbf
PB		 371 .max_policy_pct = 100,
372 .max_sysfs_pct = 100,
373 .min_policy_pct = 0,
374 .min_sysfs_pct = 0,
375};
376
377static struct perf_limits powersave_limits = {
93f0822d 378 .no_turbo = 0,
4521e1a0 379 .turbo_disabled = 0,
93f0822d 380 .max_perf_pct = 100,
d5dd33d9 381 .max_perf = int_ext_tofp(1),
93f0822d
DB		 382 .min_perf_pct = 0,
383 .min_perf = 0,
d8f469e9
DB		 384 .max_policy_pct = 100,
385 .max_sysfs_pct = 100,
a0475992
KCA		 386 .min_policy_pct = 0,
387 .min_sysfs_pct = 0,
93f0822d
DB		 388};
389
51443fbf
PB		 390#ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE
391static struct perf_limits *limits = &performance_limits;
392#else
393static struct perf_limits *limits = &powersave_limits;
394#endif
395
a410c03d
SP		 396static DEFINE_MUTEX(intel_pstate_limits_lock);
397
9522a2ff 398#ifdef CONFIG_ACPI
2b3ec765
SP		 399
400static bool intel_pstate_get_ppc_enable_status(void)
401{
402 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
403 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
404 return true;
405
406 return acpi_ppc;
407}
408
9522a2ff
SP		 409static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
410{
411 struct cpudata *cpu;
9522a2ff
SP		 412 int ret;
413 int i;
414
e59a8f7f
SP		 415 if (hwp_active)
416 return;
417
2b3ec765 418 if (!intel_pstate_get_ppc_enable_status())
9522a2ff
SP		 419 return;
420
421 cpu = all_cpu_data[policy->cpu];
422
423 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
424 policy->cpu);
425 if (ret)
426 return;
427
428 /*
429 * Check if the control value in _PSS is for PERF_CTL MSR, which should
430 * guarantee that the states returned by it map to the states in our
431 * list directly.
432 */
433 if (cpu->acpi_perf_data.control_register.space_id !=
434 ACPI_ADR_SPACE_FIXED_HARDWARE)
435 goto err;
436
437 /*
438 * If there is only one entry _PSS, simply ignore _PSS and continue as
439 * usual without taking _PSS into account
440 */
441 if (cpu->acpi_perf_data.state_count < 2)
442 goto err;
443
444 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
445 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
446 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
447 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
448 (u32) cpu->acpi_perf_data.states[i].core_frequency,
449 (u32) cpu->acpi_perf_data.states[i].power,
450 (u32) cpu->acpi_perf_data.states[i].control);
451 }
452
453 /*
454 * The _PSS table doesn't contain whole turbo frequency range.
455 * This just contains +1 MHZ above the max non turbo frequency,
456 * with control value corresponding to max turbo ratio. But
457 * when cpufreq set policy is called, it will call with this
458 * max frequency, which will cause a reduced performance as
459 * this driver uses real max turbo frequency as the max
460 * frequency. So correct this frequency in _PSS table to
b00345d1 461 * correct max turbo frequency based on the turbo state.
9522a2ff
SP		 462 * Also need to convert to MHz as _PSS freq is in MHz.
463 */
b00345d1 464 if (!limits->turbo_disabled)
9522a2ff
SP		 465 cpu->acpi_perf_data.states[0].core_frequency =
466 policy->cpuinfo.max_freq / 1000;
467 cpu->valid_pss_table = true;
6cacd115 468 pr_debug("_PPC limits will be enforced\n");
9522a2ff
SP		 469
470 return;
471
472 err:
473 cpu->valid_pss_table = false;
474 acpi_processor_unregister_performance(policy->cpu);
475}
476
477static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
478{
479 struct cpudata *cpu;
480
481 cpu = all_cpu_data[policy->cpu];
482 if (!cpu->valid_pss_table)
483 return;
484
485 acpi_processor_unregister_performance(policy->cpu);
486}
487
488#else
7a3ba767 489static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 490{
491}
492
7a3ba767 493static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
9522a2ff
SP		 494{
495}
496#endif
497
93f0822d 498static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
c410833a 499 int deadband, int integral) {
b54a0dfd
PL		 500 pid->setpoint = int_tofp(setpoint);
501 pid->deadband = int_tofp(deadband);
93f0822d 502 pid->integral = int_tofp(integral);
d98d099b 503 pid->last_err = int_tofp(setpoint) - int_tofp(busy);
93f0822d
DB		 504}
505
506static inline void pid_p_gain_set(struct _pid *pid, int percent)
507{
22590efb 508 pid->p_gain = div_fp(percent, 100);
93f0822d
DB		 509}
510
511static inline void pid_i_gain_set(struct _pid *pid, int percent)
512{
22590efb 513 pid->i_gain = div_fp(percent, 100);
93f0822d
DB		 514}
515
516static inline void pid_d_gain_set(struct _pid *pid, int percent)
517{
22590efb 518 pid->d_gain = div_fp(percent, 100);
93f0822d
DB		 519}
520
d253d2a5 521static signed int pid_calc(struct _pid *pid, int32_t busy)
93f0822d 522{
d253d2a5 523 signed int result;
93f0822d
DB		 524 int32_t pterm, dterm, fp_error;
525 int32_t integral_limit;
526
b54a0dfd 527 fp_error = pid->setpoint - busy;
93f0822d 528
b54a0dfd 529 if (abs(fp_error) <= pid->deadband)
93f0822d
DB		 530 return 0;
531
532 pterm = mul_fp(pid->p_gain, fp_error);
533
534 pid->integral += fp_error;
535
e0d4c8f8
KCA		 536 /*
537 * We limit the integral here so that it will never
538 * get higher than 30. This prevents it from becoming
539 * too large an input over long periods of time and allows
540 * it to get factored out sooner.
541 *
542 * The value of 30 was chosen through experimentation.
543 */
93f0822d
DB		 544 integral_limit = int_tofp(30);
545 if (pid->integral > integral_limit)
546 pid->integral = integral_limit;
547 if (pid->integral < -integral_limit)
548 pid->integral = -integral_limit;
549
d253d2a5
BS		 550 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
551 pid->last_err = fp_error;
93f0822d
DB		 552
553 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
51d211e9 554 result = result + (1 << (FRAC_BITS-1));
93f0822d
DB		 555 return (signed int)fp_toint(result);
556}
557
558static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
559{
016c8150
DB		 560 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
561 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
562 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
93f0822d 563
2d8d1f18 564 pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
93f0822d
DB		 565}
566
93f0822d
DB		 567static inline void intel_pstate_reset_all_pid(void)
568{
569 unsigned int cpu;
845c1cbe 570
93f0822d
DB		 571 for_each_online_cpu(cpu) {
572 if (all_cpu_data[cpu])
573 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
574 }
575}
576
4521e1a0
GM		 577static inline void update_turbo_state(void)
578{
579 u64 misc_en;
580 struct cpudata *cpu;
581
582 cpu = all_cpu_data[0];
583 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
51443fbf 584 limits->turbo_disabled =
4521e1a0
GM		 585 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
586 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
587}
588
8442885f
SP		 589static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
590{
591 u64 epb;
592 int ret;
593
594 if (!static_cpu_has(X86_FEATURE_EPB))
595 return -ENXIO;
596
597 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
598 if (ret)
599 return (s16)ret;
600
601 return (s16)(epb & 0x0f);
602}
603
604static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
605{
606 s16 epp;
607
984edbdc
SP		 608 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
609 /*
610 * When hwp_req_data is 0, means that caller didn't read
611 * MSR_HWP_REQUEST, so need to read and get EPP.
612 */
613 if (!hwp_req_data) {
614 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
615 &hwp_req_data);
616 if (epp)
617 return epp;
618 }
8442885f 619 epp = (hwp_req_data >> 24) & 0xff;
984edbdc 620 } else {
8442885f
SP		 621 /* When there is no EPP present, HWP uses EPB settings */
622 epp = intel_pstate_get_epb(cpu_data);
984edbdc 623 }
8442885f
SP		 624
625 return epp;
626}
627
984edbdc 628static int intel_pstate_set_epb(int cpu, s16 pref)
8442885f
SP		 629{
630 u64 epb;
984edbdc 631 int ret;
8442885f
SP		 632
633 if (!static_cpu_has(X86_FEATURE_EPB))
984edbdc 634 return -ENXIO;
8442885f 635
984edbdc
SP		 636 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
637 if (ret)
638 return ret;
8442885f
SP		 639
640 epb = (epb & ~0x0f) | pref;
641 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
984edbdc
SP		 642
643 return 0;
8442885f
SP		 644}
645
984edbdc
SP		 646/*
647 * EPP/EPB display strings corresponding to EPP index in the
648 * energy_perf_strings[]
649 * index String
650 *-------------------------------------
651 * 0 default
652 * 1 performance
653 * 2 balance_performance
654 * 3 balance_power
655 * 4 power
656 */
657static const char * const energy_perf_strings[] = {
658 "default",
659 "performance",
660 "balance_performance",
661 "balance_power",
662 "power",
663 NULL
664};
665
666static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
667{
668 s16 epp;
669 int index = -EINVAL;
670
671 epp = intel_pstate_get_epp(cpu_data, 0);
672 if (epp < 0)
673 return epp;
674
675 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
676 /*
677 * Range:
678 * 0x00-0x3F : Performance
679 * 0x40-0x7F : Balance performance
680 * 0x80-0xBF : Balance power
681 * 0xC0-0xFF : Power
682 * The EPP is a 8 bit value, but our ranges restrict the
683 * value which can be set. Here only using top two bits
684 * effectively.
685 */
686 index = (epp >> 6) + 1;
687 } else if (static_cpu_has(X86_FEATURE_EPB)) {
688 /*
689 * Range:
690 * 0x00-0x03 : Performance
691 * 0x04-0x07 : Balance performance
692 * 0x08-0x0B : Balance power
693 * 0x0C-0x0F : Power
694 * The EPB is a 4 bit value, but our ranges restrict the
695 * value which can be set. Here only using top two bits
696 * effectively.
697 */
698 index = (epp >> 2) + 1;
699 }
700
701 return index;
702}
703
704static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
705 int pref_index)
706{
707 int epp = -EINVAL;
708 int ret;
709
710 if (!pref_index)
711 epp = cpu_data->epp_default;
712
713 mutex_lock(&intel_pstate_limits_lock);
714
715 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
716 u64 value;
717
718 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
719 if (ret)
720 goto return_pref;
721
722 value &= ~GENMASK_ULL(31, 24);
723
724 /*
725 * If epp is not default, convert from index into
726 * energy_perf_strings to epp value, by shifting 6
727 * bits left to use only top two bits in epp.
728 * The resultant epp need to shifted by 24 bits to
729 * epp position in MSR_HWP_REQUEST.
730 */
731 if (epp == -EINVAL)
732 epp = (pref_index - 1) << 6;
733
734 value |= (u64)epp << 24;
735 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
736 } else {
737 if (epp == -EINVAL)
738 epp = (pref_index - 1) << 2;
739 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
740 }
741return_pref:
742 mutex_unlock(&intel_pstate_limits_lock);
743
744 return ret;
745}
746
747static ssize_t show_energy_performance_available_preferences(
748 struct cpufreq_policy *policy, char *buf)
749{
750 int i = 0;
751 int ret = 0;
752
753 while (energy_perf_strings[i] != NULL)
754 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
755
756 ret += sprintf(&buf[ret], "\n");
757
758 return ret;
759}
760
761cpufreq_freq_attr_ro(energy_performance_available_preferences);
762
763static ssize_t store_energy_performance_preference(
764 struct cpufreq_policy *policy, const char *buf, size_t count)
765{
766 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
767 char str_preference[21];
768 int ret, i = 0;
769
770 ret = sscanf(buf, "%20s", str_preference);
771 if (ret != 1)
772 return -EINVAL;
773
774 while (energy_perf_strings[i] != NULL) {
775 if (!strcmp(str_preference, energy_perf_strings[i])) {
776 intel_pstate_set_energy_pref_index(cpu_data, i);
777 return count;
778 }
779 ++i;
780 }
781
782 return -EINVAL;
783}
784
785static ssize_t show_energy_performance_preference(
786 struct cpufreq_policy *policy, char *buf)
787{
788 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
789 int preference;
790
791 preference = intel_pstate_get_energy_pref_index(cpu_data);
792 if (preference < 0)
793 return preference;
794
795 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
796}
797
798cpufreq_freq_attr_rw(energy_performance_preference);
799
800static struct freq_attr *hwp_cpufreq_attrs[] = {
801 &energy_performance_preference,
802 &energy_performance_available_preferences,
803 NULL,
804};
805
111b8b3f 806static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
2f86dc4c 807{
74da56ce 808 int min, hw_min, max, hw_max, cpu, range, adj_range;
eae48f04 809 struct perf_limits *perf_limits = limits;
74da56ce
KCA		 810 u64 value, cap;
811
111b8b3f 812 for_each_cpu(cpu, policy->cpus) {
eae48f04 813 int max_perf_pct, min_perf_pct;
8442885f
SP		 814 struct cpudata *cpu_data = all_cpu_data[cpu];
815 s16 epp;
eae48f04
SP		 816
817 if (per_cpu_limits)
818 perf_limits = all_cpu_data[cpu]->perf_limits;
819
f9f4872d
SP		 820 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
821 hw_min = HWP_LOWEST_PERF(cap);
822 hw_max = HWP_HIGHEST_PERF(cap);
823 range = hw_max - hw_min;
824
eae48f04
SP		 825 max_perf_pct = perf_limits->max_perf_pct;
826 min_perf_pct = perf_limits->min_perf_pct;
827
2f86dc4c 828 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
eae48f04 829 adj_range = min_perf_pct * range / 100;
74da56ce 830 min = hw_min + adj_range;
2f86dc4c
DB		 831 value &= ~HWP_MIN_PERF(~0L);
832 value |= HWP_MIN_PERF(min);
833
eae48f04 834 adj_range = max_perf_pct * range / 100;
74da56ce 835 max = hw_min + adj_range;
51443fbf 836 if (limits->no_turbo) {
74da56ce
KCA		 837 hw_max = HWP_GUARANTEED_PERF(cap);
838 if (hw_max < max)
839 max = hw_max;
2f86dc4c
DB		 840 }
841
842 value &= ~HWP_MAX_PERF(~0L);
843 value |= HWP_MAX_PERF(max);
8442885f
SP		 844
845 if (cpu_data->epp_policy == cpu_data->policy)
846 goto skip_epp;
847
848 cpu_data->epp_policy = cpu_data->policy;
849
984edbdc
SP		 850 if (cpu_data->epp_saved >= 0) {
851 epp = cpu_data->epp_saved;
852 cpu_data->epp_saved = -EINVAL;
853 goto update_epp;
854 }
855
8442885f
SP		 856 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
857 epp = intel_pstate_get_epp(cpu_data, value);
984edbdc 858 cpu_data->epp_powersave = epp;
8442885f 859 /* If EPP read was failed, then don't try to write */
984edbdc 860 if (epp < 0)
8442885f 861 goto skip_epp;
8442885f 862
8442885f
SP		 863
864 epp = 0;
865 } else {
866 /* skip setting EPP, when saved value is invalid */
984edbdc 867 if (cpu_data->epp_powersave < 0)
8442885f
SP		 868 goto skip_epp;
869
870 /*
871 * No need to restore EPP when it is not zero. This
872 * means:
873 * - Policy is not changed
874 * - user has manually changed
875 * - Error reading EPB
876 */
877 epp = intel_pstate_get_epp(cpu_data, value);
878 if (epp)
879 goto skip_epp;
880
984edbdc 881 epp = cpu_data->epp_powersave;
8442885f 882 }
984edbdc 883update_epp:
8442885f
SP		 884 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
885 value &= ~GENMASK_ULL(31, 24);
886 value |= (u64)epp << 24;
887 } else {
888 intel_pstate_set_epb(cpu, epp);
889 }
890skip_epp:
2f86dc4c
DB		 891 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
892 }
41cfd64c 893}
2f86dc4c 894
ba41e1bc
RW		 895static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
896{
897 if (hwp_active)
111b8b3f 898 intel_pstate_hwp_set(policy);
ba41e1bc
RW		 899
900 return 0;
901}
902
984edbdc
SP		 903static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
904{
905 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
906
907 if (!hwp_active)
908 return 0;
909
910 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
911
912 return 0;
913}
914
8442885f
SP		 915static int intel_pstate_resume(struct cpufreq_policy *policy)
916{
aa439248
RW		 917 int ret;
918
8442885f
SP		 919 if (!hwp_active)
920 return 0;
921
aa439248
RW		 922 mutex_lock(&intel_pstate_limits_lock);
923
8442885f 924 all_cpu_data[policy->cpu]->epp_policy = 0;
8442885f 925
aa439248
RW		 926 ret = intel_pstate_hwp_set_policy(policy);
927
928 mutex_unlock(&intel_pstate_limits_lock);
929
930 return ret;
8442885f
SP		 931}
932
111b8b3f 933static void intel_pstate_update_policies(void)
41cfd64c 934{
111b8b3f
RW		 935 int cpu;
936
937 for_each_possible_cpu(cpu)
938 cpufreq_update_policy(cpu);
2f86dc4c
DB		 939}
940
93f0822d
DB		 941/************************** debugfs begin ************************/
942static int pid_param_set(void *data, u64 val)
943{
944 *(u32 *)data = val;
945 intel_pstate_reset_all_pid();
946 return 0;
947}
845c1cbe 948
93f0822d
DB		 949static int pid_param_get(void *data, u64 *val)
950{
951 *val = *(u32 *)data;
952 return 0;
953}
2d8d1f18 954DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
93f0822d
DB		 955
956struct pid_param {
957 char *name;
958 void *value;
959};
960
961static struct pid_param pid_files[] = {
016c8150
DB		 962 {"sample_rate_ms", &pid_params.sample_rate_ms},
963 {"d_gain_pct", &pid_params.d_gain_pct},
964 {"i_gain_pct", &pid_params.i_gain_pct},
965 {"deadband", &pid_params.deadband},
966 {"setpoint", &pid_params.setpoint},
967 {"p_gain_pct", &pid_params.p_gain_pct},
93f0822d
DB		 968 {NULL, NULL}
969};
970
317dd50e 971static void __init intel_pstate_debug_expose_params(void)
93f0822d 972{
317dd50e 973 struct dentry *debugfs_parent;
93f0822d
DB		 974 int i = 0;
975
976 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
977 if (IS_ERR_OR_NULL(debugfs_parent))
978 return;
979 while (pid_files[i].name) {
980 debugfs_create_file(pid_files[i].name, 0660,
c410833a
SK		 981 debugfs_parent, pid_files[i].value,
982 &fops_pid_param);
93f0822d
DB		 983 i++;
984 }
985}
986
987/************************** debugfs end ************************/
988
989/************************** sysfs begin ************************/
990#define show_one(file_name, object) \
991 static ssize_t show_##file_name \
992 (struct kobject *kobj, struct attribute *attr, char *buf) \
993 { \
51443fbf 994 return sprintf(buf, "%u\n", limits->object); \
93f0822d
DB		 995 }
996
d01b1f48
KCA		 997static ssize_t show_turbo_pct(struct kobject *kobj,
998 struct attribute *attr, char *buf)
999{
1000 struct cpudata *cpu;
1001 int total, no_turbo, turbo_pct;
1002 uint32_t turbo_fp;
1003
1004 cpu = all_cpu_data[0];
1005
1006 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1007 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
22590efb 1008 turbo_fp = div_fp(no_turbo, total);
d01b1f48
KCA		 1009 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1010 return sprintf(buf, "%u\n", turbo_pct);
1011}
1012
0522424e
KCA		 1013static ssize_t show_num_pstates(struct kobject *kobj,
1014 struct attribute *attr, char *buf)
1015{
1016 struct cpudata *cpu;
1017 int total;
1018
1019 cpu = all_cpu_data[0];
1020 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1021 return sprintf(buf, "%u\n", total);
1022}
1023
4521e1a0
GM		 1024static ssize_t show_no_turbo(struct kobject *kobj,
1025 struct attribute *attr, char *buf)
1026{
1027 ssize_t ret;
1028
1029 update_turbo_state();
51443fbf
PB		 1030 if (limits->turbo_disabled)
1031 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
4521e1a0 1032 else
51443fbf 1033 ret = sprintf(buf, "%u\n", limits->no_turbo);
4521e1a0
GM		 1034
1035 return ret;
1036}
1037
93f0822d 1038static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
c410833a 1039 const char *buf, size_t count)
93f0822d
DB		 1040{
1041 unsigned int input;
1042 int ret;
845c1cbe 1043
93f0822d
DB		 1044 ret = sscanf(buf, "%u", &input);
1045 if (ret != 1)
1046 return -EINVAL;
4521e1a0 1047
a410c03d
SP		 1048 mutex_lock(&intel_pstate_limits_lock);
1049
4521e1a0 1050 update_turbo_state();
51443fbf 1051 if (limits->turbo_disabled) {
4836df17 1052 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
a410c03d 1053 mutex_unlock(&intel_pstate_limits_lock);
4521e1a0 1054 return -EPERM;
dd5fbf70 1055 }
2f86dc4c 1056
51443fbf 1057 limits->no_turbo = clamp_t(int, input, 0, 1);
4521e1a0 1058
b59fe540
SP		 1059 mutex_unlock(&intel_pstate_limits_lock);
1060
111b8b3f
RW		 1061 intel_pstate_update_policies();
1062
93f0822d
DB		 1063 return count;
1064}
1065
1066static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1067 const char *buf, size_t count)
93f0822d
DB		 1068{
1069 unsigned int input;
1070 int ret;
845c1cbe 1071
93f0822d
DB		 1072 ret = sscanf(buf, "%u", &input);
1073 if (ret != 1)
1074 return -EINVAL;
1075
a410c03d
SP		 1076 mutex_lock(&intel_pstate_limits_lock);
1077
51443fbf
PB		 1078 limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1079 limits->max_perf_pct = min(limits->max_policy_pct,
1080 limits->max_sysfs_pct);
1081 limits->max_perf_pct = max(limits->min_policy_pct,
1082 limits->max_perf_pct);
1083 limits->max_perf_pct = max(limits->min_perf_pct,
1084 limits->max_perf_pct);
d5dd33d9 1085 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
845c1cbe 1086
b59fe540
SP		 1087 mutex_unlock(&intel_pstate_limits_lock);
1088
111b8b3f
RW		 1089 intel_pstate_update_policies();
1090
93f0822d
DB		 1091 return count;
1092}
1093
1094static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
c410833a 1095 const char *buf, size_t count)
93f0822d
DB		 1096{
1097 unsigned int input;
1098 int ret;
845c1cbe 1099
93f0822d
DB		 1100 ret = sscanf(buf, "%u", &input);
1101 if (ret != 1)
1102 return -EINVAL;
a0475992 1103
a410c03d
SP		 1104 mutex_lock(&intel_pstate_limits_lock);
1105
51443fbf
PB		 1106 limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1107 limits->min_perf_pct = max(limits->min_policy_pct,
1108 limits->min_sysfs_pct);
1109 limits->min_perf_pct = min(limits->max_policy_pct,
1110 limits->min_perf_pct);
1111 limits->min_perf_pct = min(limits->max_perf_pct,
1112 limits->min_perf_pct);
d5dd33d9 1113 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
93f0822d 1114
b59fe540
SP		 1115 mutex_unlock(&intel_pstate_limits_lock);
1116
111b8b3f
RW		 1117 intel_pstate_update_policies();
1118
93f0822d
DB		 1119 return count;
1120}
1121
93f0822d
DB		 1122show_one(max_perf_pct, max_perf_pct);
1123show_one(min_perf_pct, min_perf_pct);
1124
1125define_one_global_rw(no_turbo);
1126define_one_global_rw(max_perf_pct);
1127define_one_global_rw(min_perf_pct);
d01b1f48 1128define_one_global_ro(turbo_pct);
0522424e 1129define_one_global_ro(num_pstates);
93f0822d
DB		 1130
1131static struct attribute *intel_pstate_attributes[] = {
1132 &no_turbo.attr,
d01b1f48 1133 &turbo_pct.attr,
0522424e 1134 &num_pstates.attr,
93f0822d
DB		 1135 NULL
1136};
1137
1138static struct attribute_group intel_pstate_attr_group = {
1139 .attrs = intel_pstate_attributes,
1140};
93f0822d 1141
317dd50e 1142static void __init intel_pstate_sysfs_expose_params(void)
93f0822d 1143{
317dd50e 1144 struct kobject *intel_pstate_kobject;
93f0822d
DB		 1145 int rc;
1146
1147 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1148 &cpu_subsys.dev_root->kobj);
eae48f04
SP		 1149 if (WARN_ON(!intel_pstate_kobject))
1150 return;
1151
2d8d1f18 1152 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
eae48f04
SP		 1153 if (WARN_ON(rc))
1154 return;
1155
1156 /*
1157 * If per cpu limits are enforced there are no global limits, so
1158 * return without creating max/min_perf_pct attributes
1159 */
1160 if (per_cpu_limits)
1161 return;
1162
1163 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1164 WARN_ON(rc);
1165
1166 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1167 WARN_ON(rc);
1168
93f0822d 1169}
93f0822d 1170/************************** sysfs end ************************/
2f86dc4c 1171
ba88d433 1172static void intel_pstate_hwp_enable(struct cpudata *cpudata)
2f86dc4c 1173{
f05c9665 1174 /* First disable HWP notification interrupt as we don't process them */
da7de91c
SP		 1175 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1176 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
f05c9665 1177
ba88d433 1178 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
8442885f 1179 cpudata->epp_policy = 0;
984edbdc
SP		 1180 if (cpudata->epp_default == -EINVAL)
1181 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
2f86dc4c
DB		 1182}
1183
938d21a2 1184static int atom_get_min_pstate(void)
19e77c28
DB		 1185{
1186 u64 value;
845c1cbe 1187
938d21a2 1188 rdmsrl(ATOM_RATIOS, value);
c16ed060 1189 return (value >> 8) & 0x7F;
19e77c28
DB		 1190}
1191
938d21a2 1192static int atom_get_max_pstate(void)
19e77c28
DB		 1193{
1194 u64 value;
845c1cbe 1195
938d21a2 1196 rdmsrl(ATOM_RATIOS, value);
c16ed060 1197 return (value >> 16) & 0x7F;
19e77c28 1198}
93f0822d 1199
938d21a2 1200static int atom_get_turbo_pstate(void)
61d8d2ab
DB		 1201{
1202 u64 value;
845c1cbe 1203
938d21a2 1204 rdmsrl(ATOM_TURBO_RATIOS, value);
c16ed060 1205 return value & 0x7F;
61d8d2ab
DB		 1206}
1207
fdfdb2b1 1208static u64 atom_get_val(struct cpudata *cpudata, int pstate)
007bea09
DB		 1209{
1210 u64 val;
1211 int32_t vid_fp;
1212 u32 vid;
1213
144c8e17 1214 val = (u64)pstate << 8;
51443fbf 1215 if (limits->no_turbo && !limits->turbo_disabled)
007bea09
DB		 1216 val |= (u64)1 << 32;
1217
1218 vid_fp = cpudata->vid.min + mul_fp(
1219 int_tofp(pstate - cpudata->pstate.min_pstate),
1220 cpudata->vid.ratio);
1221
1222 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
d022a65e 1223 vid = ceiling_fp(vid_fp);
007bea09 1224
21855ff5
DB		 1225 if (pstate > cpudata->pstate.max_pstate)
1226 vid = cpudata->vid.turbo;
1227
fdfdb2b1 1228 return val | vid;
007bea09
DB		 1229}
1230
1421df63 1231static int silvermont_get_scaling(void)
b27580b0
DB		 1232{
1233 u64 value;
1234 int i;
1421df63
PL		 1235 /* Defined in Table 35-6 from SDM (Sept 2015) */
1236 static int silvermont_freq_table[] = {
1237 83300, 100000, 133300, 116700, 80000};
b27580b0
DB		 1238
1239 rdmsrl(MSR_FSB_FREQ, value);
1421df63
PL		 1240 i = value & 0x7;
1241 WARN_ON(i > 4);
b27580b0 1242
1421df63
PL		 1243 return silvermont_freq_table[i];
1244}
b27580b0 1245
1421df63
PL		 1246static int airmont_get_scaling(void)
1247{
1248 u64 value;
1249 int i;
1250 /* Defined in Table 35-10 from SDM (Sept 2015) */
1251 static int airmont_freq_table[] = {
1252 83300, 100000, 133300, 116700, 80000,
1253 93300, 90000, 88900, 87500};
1254
1255 rdmsrl(MSR_FSB_FREQ, value);
1256 i = value & 0xF;
1257 WARN_ON(i > 8);
1258
1259 return airmont_freq_table[i];
b27580b0
DB		 1260}
1261
938d21a2 1262static void atom_get_vid(struct cpudata *cpudata)
007bea09
DB		 1263{
1264 u64 value;
1265
938d21a2 1266 rdmsrl(ATOM_VIDS, value);
c16ed060
DB		 1267 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1268 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
007bea09
DB		 1269 cpudata->vid.ratio = div_fp(
1270 cpudata->vid.max - cpudata->vid.min,
1271 int_tofp(cpudata->pstate.max_pstate -
1272 cpudata->pstate.min_pstate));
21855ff5 1273
938d21a2 1274 rdmsrl(ATOM_TURBO_VIDS, value);
21855ff5 1275 cpudata->vid.turbo = value & 0x7f;
007bea09
DB		 1276}
1277
016c8150 1278static int core_get_min_pstate(void)
93f0822d
DB		 1279{
1280 u64 value;
845c1cbe 1281
05e99c8c 1282 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1283 return (value >> 40) & 0xFF;
1284}
1285
3bcc6fa9 1286static int core_get_max_pstate_physical(void)
93f0822d
DB		 1287{
1288 u64 value;
845c1cbe 1289
05e99c8c 1290 rdmsrl(MSR_PLATFORM_INFO, value);
93f0822d
DB		 1291 return (value >> 8) & 0xFF;
1292}
1293
016c8150 1294static int core_get_max_pstate(void)
93f0822d 1295{
6a35fc2d
SP		 1296 u64 tar;
1297 u64 plat_info;
1298 int max_pstate;
1299 int err;
1300
1301 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1302 max_pstate = (plat_info >> 8) & 0xFF;
1303
1304 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1305 if (!err) {
1306 /* Do some sanity checking for safety */
1307 if (plat_info & 0x600000000) {
1308 u64 tdp_ctrl;
1309 u64 tdp_ratio;
1310 int tdp_msr;
1311
1312 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1313 if (err)
1314 goto skip_tar;
1315
5fc8f707 1316 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3);
6a35fc2d
SP		 1317 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1318 if (err)
1319 goto skip_tar;
1320
1becf035
SP		 1321 /* For level 1 and 2, bits[23:16] contain the ratio */
1322 if (tdp_ctrl)
1323 tdp_ratio >>= 16;
1324
1325 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
6a35fc2d
SP		 1326 if (tdp_ratio - 1 == tar) {
1327 max_pstate = tar;
1328 pr_debug("max_pstate=TAC %x\n", max_pstate);
1329 } else {
1330 goto skip_tar;
1331 }
1332 }
1333 }
845c1cbe 1334
6a35fc2d
SP		 1335skip_tar:
1336 return max_pstate;
93f0822d
DB		 1337}
1338
016c8150 1339static int core_get_turbo_pstate(void)
93f0822d
DB		 1340{
1341 u64 value;
1342 int nont, ret;
845c1cbe 1343
100cf6f2 1344 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
016c8150 1345 nont = core_get_max_pstate();
285cb990 1346 ret = (value) & 255;
93f0822d
DB		 1347 if (ret <= nont)
1348 ret = nont;
1349 return ret;
1350}
1351
b27580b0
DB		 1352static inline int core_get_scaling(void)
1353{
1354 return 100000;
1355}
1356
fdfdb2b1 1357static u64 core_get_val(struct cpudata *cpudata, int pstate)
016c8150
DB		 1358{
1359 u64 val;
1360
144c8e17 1361 val = (u64)pstate << 8;
51443fbf 1362 if (limits->no_turbo && !limits->turbo_disabled)
016c8150
DB		 1363 val |= (u64)1 << 32;
1364
fdfdb2b1 1365 return val;
016c8150
DB		 1366}
1367
b34ef932
DC		 1368static int knl_get_turbo_pstate(void)
1369{
1370 u64 value;
1371 int nont, ret;
1372
100cf6f2 1373 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
b34ef932
DC		 1374 nont = core_get_max_pstate();
1375 ret = (((value) >> 8) & 0xFF);
1376 if (ret <= nont)
1377 ret = nont;
1378 return ret;
1379}
1380
016c8150
DB		 1381static struct cpu_defaults core_params = {
1382 .pid_policy = {
1383 .sample_rate_ms = 10,
1384 .deadband = 0,
1385 .setpoint = 97,
1386 .p_gain_pct = 20,
1387 .d_gain_pct = 0,
1388 .i_gain_pct = 0,
1389 },
1390 .funcs = {
1391 .get_max = core_get_max_pstate,
3bcc6fa9 1392 .get_max_physical = core_get_max_pstate_physical,
016c8150
DB		 1393 .get_min = core_get_min_pstate,
1394 .get_turbo = core_get_turbo_pstate,
b27580b0 1395 .get_scaling = core_get_scaling,
fdfdb2b1 1396 .get_val = core_get_val,
157386b6 1397 .get_target_pstate = get_target_pstate_use_performance,
016c8150
DB		 1398 },
1399};
1400
42ce8921 1401static const struct cpu_defaults silvermont_params = {
1421df63
PL		 1402 .pid_policy = {
1403 .sample_rate_ms = 10,
1404 .deadband = 0,
1405 .setpoint = 60,
1406 .p_gain_pct = 14,
1407 .d_gain_pct = 0,
1408 .i_gain_pct = 4,
1409 },
1410 .funcs = {
1411 .get_max = atom_get_max_pstate,
1412 .get_max_physical = atom_get_max_pstate,
1413 .get_min = atom_get_min_pstate,
1414 .get_turbo = atom_get_turbo_pstate,
fdfdb2b1 1415 .get_val = atom_get_val,
1421df63
PL		 1416 .get_scaling = silvermont_get_scaling,
1417 .get_vid = atom_get_vid,
e70eed2b 1418 .get_target_pstate = get_target_pstate_use_cpu_load,
1421df63
PL		 1419 },
1420};
1421
42ce8921 1422static const struct cpu_defaults airmont_params = {
19e77c28
DB		 1423 .pid_policy = {
1424 .sample_rate_ms = 10,
1425 .deadband = 0,
6a82ba6d 1426 .setpoint = 60,
19e77c28
DB		 1427 .p_gain_pct = 14,
1428 .d_gain_pct = 0,
1429 .i_gain_pct = 4,
1430 },
1431 .funcs = {
938d21a2
PL		 1432 .get_max = atom_get_max_pstate,
1433 .get_max_physical = atom_get_max_pstate,
1434 .get_min = atom_get_min_pstate,
1435 .get_turbo = atom_get_turbo_pstate,
fdfdb2b1 1436 .get_val = atom_get_val,
1421df63 1437 .get_scaling = airmont_get_scaling,
938d21a2 1438 .get_vid = atom_get_vid,
e70eed2b 1439 .get_target_pstate = get_target_pstate_use_cpu_load,
19e77c28
DB		 1440 },
1441};
1442
42ce8921 1443static const struct cpu_defaults knl_params = {
b34ef932
DC		 1444 .pid_policy = {
1445 .sample_rate_ms = 10,
1446 .deadband = 0,
1447 .setpoint = 97,
1448 .p_gain_pct = 20,
1449 .d_gain_pct = 0,
1450 .i_gain_pct = 0,
1451 },
1452 .funcs = {
1453 .get_max = core_get_max_pstate,
3bcc6fa9 1454 .get_max_physical = core_get_max_pstate_physical,
b34ef932
DC		 1455 .get_min = core_get_min_pstate,
1456 .get_turbo = knl_get_turbo_pstate,
69cefc27 1457 .get_scaling = core_get_scaling,
fdfdb2b1 1458 .get_val = core_get_val,
157386b6 1459 .get_target_pstate = get_target_pstate_use_performance,
b34ef932
DC		 1460 },
1461};
1462
42ce8921 1463static const struct cpu_defaults bxt_params = {
41bad47f
SP		 1464 .pid_policy = {
1465 .sample_rate_ms = 10,
1466 .deadband = 0,
1467 .setpoint = 60,
1468 .p_gain_pct = 14,
1469 .d_gain_pct = 0,
1470 .i_gain_pct = 4,
1471 },
1472 .funcs = {
1473 .get_max = core_get_max_pstate,
1474 .get_max_physical = core_get_max_pstate_physical,
1475 .get_min = core_get_min_pstate,
1476 .get_turbo = core_get_turbo_pstate,
1477 .get_scaling = core_get_scaling,
1478 .get_val = core_get_val,
1479 .get_target_pstate = get_target_pstate_use_cpu_load,
1480 },
1481};
1482
93f0822d
DB		 1483static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1484{
1485 int max_perf = cpu->pstate.turbo_pstate;
7244cb62 1486 int max_perf_adj;
93f0822d 1487 int min_perf;
eae48f04 1488 struct perf_limits *perf_limits = limits;
845c1cbe 1489
51443fbf 1490 if (limits->no_turbo || limits->turbo_disabled)
93f0822d
DB		 1491 max_perf = cpu->pstate.max_pstate;
1492
eae48f04
SP		 1493 if (per_cpu_limits)
1494 perf_limits = cpu->perf_limits;
1495
e0d4c8f8
KCA		 1496 /*
1497 * performance can be limited by user through sysfs, by cpufreq
1498 * policy, or by cpu specific default values determined through
1499 * experimentation.
1500 */
d5dd33d9 1501 max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
799281a3
RW		 1502 *max = clamp_t(int, max_perf_adj,
1503 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
93f0822d 1504
d5dd33d9 1505 min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
799281a3 1506 *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
93f0822d
DB		 1507}
1508
a6c6ead1 1509static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
fdfdb2b1 1510{
bc95a454
RW		 1511 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1512 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1513 /*
1514 * Generally, there is no guarantee that this code will always run on
1515 * the CPU being updated, so force the register update to run on the
1516 * right CPU.
1517 */
1518 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1519 pstate_funcs.get_val(cpu, pstate));
93f0822d
DB		 1520}
1521
a6c6ead1
RW		 1522static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1523{
1524 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1525}
1526
1527static void intel_pstate_max_within_limits(struct cpudata *cpu)
1528{
1529 int min_pstate, max_pstate;
1530
1531 update_turbo_state();
1532 intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1533 intel_pstate_set_pstate(cpu, max_pstate);
1534}
1535
93f0822d
DB		 1536static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1537{
016c8150
DB		 1538 cpu->pstate.min_pstate = pstate_funcs.get_min();
1539 cpu->pstate.max_pstate = pstate_funcs.get_max();
3bcc6fa9 1540 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
016c8150 1541 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
b27580b0 1542 cpu->pstate.scaling = pstate_funcs.get_scaling();
001c76f0
RW		 1543 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1544 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d 1545
007bea09
DB		 1546 if (pstate_funcs.get_vid)
1547 pstate_funcs.get_vid(cpu);
fdfdb2b1
RW		 1548
1549 intel_pstate_set_min_pstate(cpu);
93f0822d
DB		 1550}
1551
a1c9787d 1552static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
93f0822d 1553{
6b17ddb2 1554 struct sample *sample = &cpu->sample;
e66c1768 1555
a1c9787d 1556 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
93f0822d
DB		 1557}
1558
4fec7ad5 1559static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
93f0822d 1560{
93f0822d 1561 u64 aperf, mperf;
4ab60c3f 1562 unsigned long flags;
4055fad3 1563 u64 tsc;
93f0822d 1564
4ab60c3f 1565 local_irq_save(flags);
93f0822d
DB		 1566 rdmsrl(MSR_IA32_APERF, aperf);
1567 rdmsrl(MSR_IA32_MPERF, mperf);
e70eed2b 1568 tsc = rdtsc();
4fec7ad5 1569 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
8e601a9f 1570 local_irq_restore(flags);
4fec7ad5 1571 return false;
8e601a9f 1572 }
4ab60c3f 1573 local_irq_restore(flags);
b69880f9 1574
c4ee841f 1575 cpu->last_sample_time = cpu->sample.time;
a4675fbc 1576 cpu->sample.time = time;
d37e2b76
DB		 1577 cpu->sample.aperf = aperf;
1578 cpu->sample.mperf = mperf;
4055fad3 1579 cpu->sample.tsc = tsc;
d37e2b76
DB		 1580 cpu->sample.aperf -= cpu->prev_aperf;
1581 cpu->sample.mperf -= cpu->prev_mperf;
4055fad3 1582 cpu->sample.tsc -= cpu->prev_tsc;
1abc4b20 1583
93f0822d
DB		 1584 cpu->prev_aperf = aperf;
1585 cpu->prev_mperf = mperf;
4055fad3 1586 cpu->prev_tsc = tsc;
febce40f
RW		 1587 /*
1588 * First time this function is invoked in a given cycle, all of the
1589 * previous sample data fields are equal to zero or stale and they must
1590 * be populated with meaningful numbers for things to work, so assume
1591 * that sample.time will always be reset before setting the utilization
1592 * update hook and make the caller skip the sample then.
1593 */
1594 return !!cpu->last_sample_time;
93f0822d
DB		 1595}
1596
8fa520af
PL		 1597static inline int32_t get_avg_frequency(struct cpudata *cpu)
1598{
a1c9787d
RW		 1599 return mul_ext_fp(cpu->sample.core_avg_perf,
1600 cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
8fa520af
PL		 1601}
1602
bdcaa23f
PL		 1603static inline int32_t get_avg_pstate(struct cpudata *cpu)
1604{
8edb0a6e
RW		 1605 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1606 cpu->sample.core_avg_perf);
bdcaa23f
PL		 1607}
1608
e70eed2b
PL		 1609static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1610{
1611 struct sample *sample = &cpu->sample;
09c448d3 1612 int32_t busy_frac, boost;
0843e83c 1613 int target, avg_pstate;
e70eed2b 1614
09c448d3 1615 busy_frac = div_fp(sample->mperf, sample->tsc);
63d1d656 1616
09c448d3
RW		 1617 boost = cpu->iowait_boost;
1618 cpu->iowait_boost >>= 1;
63d1d656 1619
09c448d3
RW		 1620 if (busy_frac < boost)
1621 busy_frac = boost;
63d1d656 1622
09c448d3 1623 sample->busy_scaled = busy_frac * 100;
0843e83c
RW		 1624
1625 target = limits->no_turbo || limits->turbo_disabled ?
1626 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1627 target += target >> 2;
1628 target = mul_fp(target, busy_frac);
1629 if (target < cpu->pstate.min_pstate)
1630 target = cpu->pstate.min_pstate;
1631
1632 /*
1633 * If the average P-state during the previous cycle was higher than the
1634 * current target, add 50% of the difference to the target to reduce
1635 * possible performance oscillations and offset possible performance
1636 * loss related to moving the workload from one CPU to another within
1637 * a package/module.
1638 */
1639 avg_pstate = get_avg_pstate(cpu);
1640 if (avg_pstate > target)
1641 target += (avg_pstate - target) >> 1;
1642
1643 return target;
e70eed2b
PL		 1644}
1645
157386b6 1646static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
93f0822d 1647{
1aa7a6e2 1648 int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
a4675fbc 1649 u64 duration_ns;
93f0822d 1650
e0d4c8f8 1651 /*
f00593a4
RW		 1652 * perf_scaled is the ratio of the average P-state during the last
1653 * sampling period to the P-state requested last time (in percent).
1654 *
1655 * That measures the system's response to the previous P-state
1656 * selection.
e0d4c8f8 1657 */
22590efb
RW		 1658 max_pstate = cpu->pstate.max_pstate_physical;
1659 current_pstate = cpu->pstate.current_pstate;
1aa7a6e2 1660 perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
a1c9787d 1661 div_fp(100 * max_pstate, current_pstate));
c4ee841f 1662
e0d4c8f8 1663 /*
a4675fbc
RW		 1664 * Since our utilization update callback will not run unless we are
1665 * in C0, check if the actual elapsed time is significantly greater (3x)
1666 * than our sample interval. If it is, then we were idle for a long
1aa7a6e2 1667 * enough period of time to adjust our performance metric.
e0d4c8f8 1668 */
a4675fbc 1669 duration_ns = cpu->sample.time - cpu->last_sample_time;
febce40f 1670 if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
22590efb 1671 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1aa7a6e2 1672 perf_scaled = mul_fp(perf_scaled, sample_ratio);
ffb81056
RW		 1673 } else {
1674 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1675 if (sample_ratio < int_tofp(1))
1aa7a6e2 1676 perf_scaled = 0;
c4ee841f
DB		 1677 }
1678
1aa7a6e2
RW		 1679 cpu->sample.busy_scaled = perf_scaled;
1680 return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
93f0822d
DB		 1681}
1682
001c76f0 1683static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
fdfdb2b1
RW		 1684{
1685 int max_perf, min_perf;
1686
fdfdb2b1
RW		 1687 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1688 pstate = clamp_t(int, pstate, min_perf, max_perf);
bc95a454 1689 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
001c76f0
RW		 1690 return pstate;
1691}
1692
1693static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1694{
1695 pstate = intel_pstate_prepare_request(cpu, pstate);
fdfdb2b1
RW		 1696 if (pstate == cpu->pstate.current_pstate)
1697 return;
1698
bc95a454 1699 cpu->pstate.current_pstate = pstate;
fdfdb2b1
RW		 1700 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1701}
1702
93f0822d
DB		 1703static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1704{
157386b6 1705 int from, target_pstate;
4055fad3
DS		 1706 struct sample *sample;
1707
1708 from = cpu->pstate.current_pstate;
93f0822d 1709
2f1d407a
RW		 1710 target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1711 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
93f0822d 1712
001c76f0
RW		 1713 update_turbo_state();
1714
fdfdb2b1 1715 intel_pstate_update_pstate(cpu, target_pstate);
4055fad3
DS		 1716
1717 sample = &cpu->sample;
a1c9787d 1718 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
157386b6 1719 fp_toint(sample->busy_scaled),
4055fad3
DS		 1720 from,
1721 cpu->pstate.current_pstate,
1722 sample->mperf,
1723 sample->aperf,
1724 sample->tsc,
3ba7bcaa
SP		 1725 get_avg_frequency(cpu),
1726 fp_toint(cpu->iowait_boost * 100));
93f0822d
DB		 1727}
1728
a4675fbc 1729static void intel_pstate_update_util(struct update_util_data *data, u64 time,
58919e83 1730 unsigned int flags)
93f0822d 1731{
a4675fbc 1732 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
09c448d3
RW		 1733 u64 delta_ns;
1734
1d29815e 1735 if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
09c448d3
RW		 1736 if (flags & SCHED_CPUFREQ_IOWAIT) {
1737 cpu->iowait_boost = int_tofp(1);
1738 } else if (cpu->iowait_boost) {
1739 /* Clear iowait_boost if the CPU may have been idle. */
1740 delta_ns = time - cpu->last_update;
1741 if (delta_ns > TICK_NSEC)
1742 cpu->iowait_boost = 0;
1743 }
1744 cpu->last_update = time;
1745 }
b69880f9 1746
09c448d3 1747 delta_ns = time - cpu->sample.time;
a4675fbc 1748 if ((s64)delta_ns >= pid_params.sample_rate_ns) {
4fec7ad5
RW		 1749 bool sample_taken = intel_pstate_sample(cpu, time);
1750
6d45b719 1751 if (sample_taken) {
a1c9787d 1752 intel_pstate_calc_avg_perf(cpu);
6d45b719
RW		 1753 if (!hwp_active)
1754 intel_pstate_adjust_busy_pstate(cpu);
1755 }
a4675fbc 1756 }
93f0822d
DB		 1757}
1758
1759#define ICPU(model, policy) \
6cbd7ee1
DB		 1760 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1761 (unsigned long)&policy }
93f0822d
DB		 1762
1763static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
5b20c944
DH		 1764 ICPU(INTEL_FAM6_SANDYBRIDGE, core_params),
1765 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params),
1766 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params),
1767 ICPU(INTEL_FAM6_IVYBRIDGE, core_params),
1768 ICPU(INTEL_FAM6_HASWELL_CORE, core_params),
1769 ICPU(INTEL_FAM6_BROADWELL_CORE, core_params),
1770 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params),
1771 ICPU(INTEL_FAM6_HASWELL_X, core_params),
1772 ICPU(INTEL_FAM6_HASWELL_ULT, core_params),
1773 ICPU(INTEL_FAM6_HASWELL_GT3E, core_params),
1774 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params),
1775 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params),
1776 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params),
1777 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1778 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params),
1779 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1780 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params),
58bf4542 1781 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_params),
41bad47f 1782 ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params),
93f0822d
DB		 1783 {}
1784};
1785MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1786
29327c84 1787static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
5b20c944 1788 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
65c1262f
SP		 1789 ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1790 ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
2f86dc4c
DB		 1791 {}
1792};
1793
93f0822d
DB		 1794static int intel_pstate_init_cpu(unsigned int cpunum)
1795{
93f0822d
DB		 1796 struct cpudata *cpu;
1797
eae48f04
SP		 1798 cpu = all_cpu_data[cpunum];
1799
1800 if (!cpu) {
1801 unsigned int size = sizeof(struct cpudata);
1802
1803 if (per_cpu_limits)
1804 size += sizeof(struct perf_limits);
1805
1806 cpu = kzalloc(size, GFP_KERNEL);
1807 if (!cpu)
1808 return -ENOMEM;
1809
1810 all_cpu_data[cpunum] = cpu;
1811 if (per_cpu_limits)
1812 cpu->perf_limits = (struct perf_limits *)(cpu + 1);
1813
984edbdc
SP		 1814 cpu->epp_default = -EINVAL;
1815 cpu->epp_powersave = -EINVAL;
1816 cpu->epp_saved = -EINVAL;
eae48f04 1817 }
93f0822d
DB		 1818
1819 cpu = all_cpu_data[cpunum];
1820
93f0822d 1821 cpu->cpu = cpunum;
ba88d433 1822
a4675fbc 1823 if (hwp_active) {
ba88d433 1824 intel_pstate_hwp_enable(cpu);
a4675fbc
RW		 1825 pid_params.sample_rate_ms = 50;
1826 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
1827 }
ba88d433 1828
179e8471 1829 intel_pstate_get_cpu_pstates(cpu);
016c8150 1830
93f0822d 1831 intel_pstate_busy_pid_reset(cpu);
93f0822d 1832
4836df17 1833 pr_debug("controlling: cpu %d\n", cpunum);
93f0822d
DB		 1834
1835 return 0;
1836}
1837
1838static unsigned int intel_pstate_get(unsigned int cpu_num)
1839{
f96fd0c8 1840 struct cpudata *cpu = all_cpu_data[cpu_num];
93f0822d 1841
f96fd0c8 1842 return cpu ? get_avg_frequency(cpu) : 0;
93f0822d
DB		 1843}
1844
febce40f 1845static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
bb6ab52f 1846{
febce40f
RW		 1847 struct cpudata *cpu = all_cpu_data[cpu_num];
1848
5ab666e0
RW		 1849 if (cpu->update_util_set)
1850 return;
1851
febce40f
RW		 1852 /* Prevent intel_pstate_update_util() from using stale data. */
1853 cpu->sample.time = 0;
0bed612b
RW		 1854 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1855 intel_pstate_update_util);
4578ee7e 1856 cpu->update_util_set = true;
bb6ab52f
RW		 1857}
1858
1859static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1860{
4578ee7e
CY		 1861 struct cpudata *cpu_data = all_cpu_data[cpu];
1862
1863 if (!cpu_data->update_util_set)
1864 return;
1865
0bed612b 1866 cpufreq_remove_update_util_hook(cpu);
4578ee7e 1867 cpu_data->update_util_set = false;
bb6ab52f
RW		 1868 synchronize_sched();
1869}
1870
30a39153
SP		 1871static void intel_pstate_set_performance_limits(struct perf_limits *limits)
1872{
1873 limits->no_turbo = 0;
1874 limits->turbo_disabled = 0;
1875 limits->max_perf_pct = 100;
d5dd33d9 1876 limits->max_perf = int_ext_tofp(1);
30a39153 1877 limits->min_perf_pct = 100;
d5dd33d9 1878 limits->min_perf = int_ext_tofp(1);
30a39153
SP		 1879 limits->max_policy_pct = 100;
1880 limits->max_sysfs_pct = 100;
1881 limits->min_policy_pct = 0;
1882 limits->min_sysfs_pct = 0;
1883}
1884
eae48f04
SP		 1885static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1886 struct perf_limits *limits)
1887{
a410c03d 1888
eae48f04
SP		 1889 limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
1890 policy->cpuinfo.max_freq);
1891 limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
5879f877
SP		 1892 if (policy->max == policy->min) {
1893 limits->min_policy_pct = limits->max_policy_pct;
1894 } else {
46992d6b
SP		 1895 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
1896 policy->cpuinfo.max_freq);
5879f877
SP		 1897 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
1898 0, 100);
1899 }
eae48f04
SP		 1900
1901 /* Normalize user input to [min_policy_pct, max_policy_pct] */
1902 limits->min_perf_pct = max(limits->min_policy_pct,
1903 limits->min_sysfs_pct);
1904 limits->min_perf_pct = min(limits->max_policy_pct,
1905 limits->min_perf_pct);
1906 limits->max_perf_pct = min(limits->max_policy_pct,
1907 limits->max_sysfs_pct);
1908 limits->max_perf_pct = max(limits->min_policy_pct,
1909 limits->max_perf_pct);
1910
1911 /* Make sure min_perf_pct <= max_perf_pct */
1912 limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
1913
d5dd33d9
SP		 1914 limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1915 limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1916 limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
1917 limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
eae48f04
SP		 1918
1919 pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
1920 limits->max_perf_pct, limits->min_perf_pct);
1921}
1922
93f0822d
DB		 1923static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1924{
3be9200d 1925 struct cpudata *cpu;
eae48f04 1926 struct perf_limits *perf_limits = NULL;
3be9200d 1927
d3929b83
DB		 1928 if (!policy->cpuinfo.max_freq)
1929 return -ENODEV;
1930
2c2c1af4
SP		 1931 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1932 policy->cpuinfo.max_freq, policy->max);
1933
a6c6ead1 1934 cpu = all_cpu_data[policy->cpu];
2f1d407a
RW		 1935 cpu->policy = policy->policy;
1936
c749c64f
RW		 1937 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
1938 policy->max < policy->cpuinfo.max_freq &&
1939 policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
1940 pr_debug("policy->max > max non turbo frequency\n");
1941 policy->max = policy->cpuinfo.max_freq;
3be9200d
SP		 1942 }
1943
eae48f04
SP		 1944 if (per_cpu_limits)
1945 perf_limits = cpu->perf_limits;
1946
b59fe540
SP		 1947 mutex_lock(&intel_pstate_limits_lock);
1948
eae48f04
SP		 1949 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
1950 if (!perf_limits) {
1951 limits = &performance_limits;
1952 perf_limits = limits;
1953 }
30a39153 1954 if (policy->max >= policy->cpuinfo.max_freq) {
4836df17 1955 pr_debug("set performance\n");
eae48f04 1956 intel_pstate_set_performance_limits(perf_limits);
30a39153
SP		 1957 goto out;
1958 }
1959 } else {
4836df17 1960 pr_debug("set powersave\n");
eae48f04
SP		 1961 if (!perf_limits) {
1962 limits = &powersave_limits;
1963 perf_limits = limits;
1964 }
43717aad 1965
eae48f04 1966 }
93f0822d 1967
eae48f04 1968 intel_pstate_update_perf_limits(policy, perf_limits);
bb6ab52f 1969 out:
2f1d407a 1970 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
a6c6ead1
RW		 1971 /*
1972 * NOHZ_FULL CPUs need this as the governor callback may not
1973 * be invoked on them.
1974 */
1975 intel_pstate_clear_update_util_hook(policy->cpu);
1976 intel_pstate_max_within_limits(cpu);
1977 }
1978
bb6ab52f
RW		 1979 intel_pstate_set_update_util_hook(policy->cpu);
1980
ba41e1bc 1981 intel_pstate_hwp_set_policy(policy);
2f86dc4c 1982
b59fe540
SP		 1983 mutex_unlock(&intel_pstate_limits_lock);
1984
93f0822d
DB		 1985 return 0;
1986}
1987
1988static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
1989{
be49e346 1990 cpufreq_verify_within_cpu_limits(policy);
93f0822d 1991
285cb990 1992 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
c410833a 1993 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
93f0822d
DB		 1994 return -EINVAL;
1995
1996 return 0;
1997}
1998
001c76f0
RW		 1999static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2000{
2001 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2002}
2003
bb18008f 2004static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
93f0822d 2005{
001c76f0 2006 pr_debug("CPU %d exiting\n", policy->cpu);
93f0822d 2007
001c76f0 2008 intel_pstate_clear_update_util_hook(policy->cpu);
984edbdc
SP		 2009 if (hwp_active)
2010 intel_pstate_hwp_save_state(policy);
2011 else
001c76f0
RW		 2012 intel_cpufreq_stop_cpu(policy);
2013}
bb18008f 2014
001c76f0
RW		 2015static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2016{
2017 intel_pstate_exit_perf_limits(policy);
a4675fbc 2018
001c76f0 2019 policy->fast_switch_possible = false;
2f86dc4c 2020
001c76f0 2021 return 0;
93f0822d
DB		 2022}
2023
001c76f0 2024static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
93f0822d 2025{
93f0822d 2026 struct cpudata *cpu;
52e0a509 2027 int rc;
93f0822d
DB		 2028
2029 rc = intel_pstate_init_cpu(policy->cpu);
2030 if (rc)
2031 return rc;
2032
2033 cpu = all_cpu_data[policy->cpu];
2034
eae48f04
SP		 2035 /*
2036 * We need sane value in the cpu->perf_limits, so inherit from global
2037 * perf_limits limits, which are seeded with values based on the
2038 * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2039 */
2040 if (per_cpu_limits)
2041 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2042
b27580b0
DB		 2043 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2044 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
93f0822d
DB		 2045
2046 /* cpuinfo and default policy values */
b27580b0 2047 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
983e600e
SP		 2048 update_turbo_state();
2049 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2050 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2051 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2052
9522a2ff 2053 intel_pstate_init_acpi_perf_limits(policy);
93f0822d
DB		 2054 cpumask_set_cpu(policy->cpu, policy->cpus);
2055
001c76f0
RW		 2056 policy->fast_switch_possible = true;
2057
93f0822d
DB		 2058 return 0;
2059}
2060
001c76f0 2061static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
9522a2ff 2062{
001c76f0
RW		 2063 int ret = __intel_pstate_cpu_init(policy);
2064
2065 if (ret)
2066 return ret;
2067
2068 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2069 if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2070 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2071 else
2072 policy->policy = CPUFREQ_POLICY_POWERSAVE;
9522a2ff
SP		 2073
2074 return 0;
2075}
2076
001c76f0 2077static struct cpufreq_driver intel_pstate = {
93f0822d
DB		 2078 .flags = CPUFREQ_CONST_LOOPS,
2079 .verify = intel_pstate_verify_policy,
2080 .setpolicy = intel_pstate_set_policy,
984edbdc 2081 .suspend = intel_pstate_hwp_save_state,
8442885f 2082 .resume = intel_pstate_resume,
93f0822d
DB		 2083 .get = intel_pstate_get,
2084 .init = intel_pstate_cpu_init,
9522a2ff 2085 .exit = intel_pstate_cpu_exit,
bb18008f 2086 .stop_cpu = intel_pstate_stop_cpu,
93f0822d 2087 .name = "intel_pstate",
93f0822d
DB		 2088};
2089
001c76f0
RW		 2090static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2091{
2092 struct cpudata *cpu = all_cpu_data[policy->cpu];
2093 struct perf_limits *perf_limits = limits;
2094
2095 update_turbo_state();
2096 policy->cpuinfo.max_freq = limits->turbo_disabled ?
2097 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2098
2099 cpufreq_verify_within_cpu_limits(policy);
2100
2101 if (per_cpu_limits)
2102 perf_limits = cpu->perf_limits;
2103
cad30467
RW		 2104 mutex_lock(&intel_pstate_limits_lock);
2105
001c76f0
RW		 2106 intel_pstate_update_perf_limits(policy, perf_limits);
2107
cad30467
RW		 2108 mutex_unlock(&intel_pstate_limits_lock);
2109
001c76f0
RW		 2110 return 0;
2111}
2112
2113static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2114 struct cpufreq_policy *policy,
2115 unsigned int target_freq)
2116{
2117 unsigned int max_freq;
2118
2119 update_turbo_state();
2120
2121 max_freq = limits->no_turbo || limits->turbo_disabled ?
2122 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2123 policy->cpuinfo.max_freq = max_freq;
2124 if (policy->max > max_freq)
2125 policy->max = max_freq;
2126
2127 if (target_freq > max_freq)
2128 target_freq = max_freq;
2129
2130 return target_freq;
2131}
2132
2133static int intel_cpufreq_target(struct cpufreq_policy *policy,
2134 unsigned int target_freq,
2135 unsigned int relation)
2136{
2137 struct cpudata *cpu = all_cpu_data[policy->cpu];
2138 struct cpufreq_freqs freqs;
2139 int target_pstate;
2140
2141 freqs.old = policy->cur;
2142 freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2143
2144 cpufreq_freq_transition_begin(policy, &freqs);
2145 switch (relation) {
2146 case CPUFREQ_RELATION_L:
2147 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2148 break;
2149 case CPUFREQ_RELATION_H:
2150 target_pstate = freqs.new / cpu->pstate.scaling;
2151 break;
2152 default:
2153 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2154 break;
2155 }
2156 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2157 if (target_pstate != cpu->pstate.current_pstate) {
2158 cpu->pstate.current_pstate = target_pstate;
2159 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2160 pstate_funcs.get_val(cpu, target_pstate));
2161 }
2162 cpufreq_freq_transition_end(policy, &freqs, false);
2163
2164 return 0;
2165}
2166
2167static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2168 unsigned int target_freq)
2169{
2170 struct cpudata *cpu = all_cpu_data[policy->cpu];
2171 int target_pstate;
2172
2173 target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2174 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2175 intel_pstate_update_pstate(cpu, target_pstate);
2176 return target_freq;
2177}
2178
2179static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2180{
2181 int ret = __intel_pstate_cpu_init(policy);
2182
2183 if (ret)
2184 return ret;
2185
2186 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2187 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2188 policy->cur = policy->cpuinfo.min_freq;
2189
2190 return 0;
2191}
2192
2193static struct cpufreq_driver intel_cpufreq = {
2194 .flags = CPUFREQ_CONST_LOOPS,
2195 .verify = intel_cpufreq_verify_policy,
2196 .target = intel_cpufreq_target,
2197 .fast_switch = intel_cpufreq_fast_switch,
2198 .init = intel_cpufreq_cpu_init,
2199 .exit = intel_pstate_cpu_exit,
2200 .stop_cpu = intel_cpufreq_stop_cpu,
2201 .name = "intel_cpufreq",
2202};
2203
2204static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2205
eed43609
JZ		 2206static int no_load __initdata;
2207static int no_hwp __initdata;
2208static int hwp_only __initdata;
29327c84 2209static unsigned int force_load __initdata;
6be26498 2210
29327c84 2211static int __init intel_pstate_msrs_not_valid(void)
b563b4e3 2212{
016c8150 2213 if (!pstate_funcs.get_max() ||
c410833a
SK		 2214 !pstate_funcs.get_min() ||
2215 !pstate_funcs.get_turbo())
b563b4e3
DB		 2216 return -ENODEV;
2217
b563b4e3
DB		 2218 return 0;
2219}
016c8150 2220
29327c84 2221static void __init copy_pid_params(struct pstate_adjust_policy *policy)
016c8150
DB		 2222{
2223 pid_params.sample_rate_ms = policy->sample_rate_ms;
a4675fbc 2224 pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
016c8150
DB		 2225 pid_params.p_gain_pct = policy->p_gain_pct;
2226 pid_params.i_gain_pct = policy->i_gain_pct;
2227 pid_params.d_gain_pct = policy->d_gain_pct;
2228 pid_params.deadband = policy->deadband;
2229 pid_params.setpoint = policy->setpoint;
2230}
2231
7f7a516e
SP		 2232#ifdef CONFIG_ACPI
2233static void intel_pstate_use_acpi_profile(void)
2234{
2235 if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2236 pstate_funcs.get_target_pstate =
2237 get_target_pstate_use_cpu_load;
2238}
2239#else
2240static void intel_pstate_use_acpi_profile(void)
2241{
2242}
2243#endif
2244
29327c84 2245static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
016c8150
DB		 2246{
2247 pstate_funcs.get_max = funcs->get_max;
3bcc6fa9 2248 pstate_funcs.get_max_physical = funcs->get_max_physical;
016c8150
DB		 2249 pstate_funcs.get_min = funcs->get_min;
2250 pstate_funcs.get_turbo = funcs->get_turbo;
b27580b0 2251 pstate_funcs.get_scaling = funcs->get_scaling;
fdfdb2b1 2252 pstate_funcs.get_val = funcs->get_val;
007bea09 2253 pstate_funcs.get_vid = funcs->get_vid;
157386b6
PL		 2254 pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2255
7f7a516e 2256 intel_pstate_use_acpi_profile();
016c8150
DB		 2257}
2258
9522a2ff 2259#ifdef CONFIG_ACPI
fbbcdc07 2260
29327c84 2261static bool __init intel_pstate_no_acpi_pss(void)
fbbcdc07
AH		 2262{
2263 int i;
2264
2265 for_each_possible_cpu(i) {
2266 acpi_status status;
2267 union acpi_object *pss;
2268 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2269 struct acpi_processor *pr = per_cpu(processors, i);
2270
2271 if (!pr)
2272 continue;
2273
2274 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2275 if (ACPI_FAILURE(status))
2276 continue;
2277
2278 pss = buffer.pointer;
2279 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2280 kfree(pss);
2281 return false;
2282 }
2283
2284 kfree(pss);
2285 }
2286
2287 return true;
2288}
2289
29327c84 2290static bool __init intel_pstate_has_acpi_ppc(void)
966916ea 2291{
2292 int i;
2293
2294 for_each_possible_cpu(i) {
2295 struct acpi_processor *pr = per_cpu(processors, i);
2296
2297 if (!pr)
2298 continue;
2299 if (acpi_has_method(pr->handle, "_PPC"))
2300 return true;
2301 }
2302 return false;
2303}
2304
2305enum {
2306 PSS,
2307 PPC,
2308};
2309
fbbcdc07
AH		 2310struct hw_vendor_info {
2311 u16 valid;
2312 char oem_id[ACPI_OEM_ID_SIZE];
2313 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
966916ea 2314 int oem_pwr_table;
fbbcdc07
AH		 2315};
2316
2317/* Hardware vendor-specific info that has its own power management modes */
29327c84 2318static struct hw_vendor_info vendor_info[] __initdata = {
966916ea 2319 {1, "HP ", "ProLiant", PSS},
2320 {1, "ORACLE", "X4-2 ", PPC},
2321 {1, "ORACLE", "X4-2L ", PPC},
2322 {1, "ORACLE", "X4-2B ", PPC},
2323 {1, "ORACLE", "X3-2 ", PPC},
2324 {1, "ORACLE", "X3-2L ", PPC},
2325 {1, "ORACLE", "X3-2B ", PPC},
2326 {1, "ORACLE", "X4470M2 ", PPC},
2327 {1, "ORACLE", "X4270M3 ", PPC},
2328 {1, "ORACLE", "X4270M2 ", PPC},
2329 {1, "ORACLE", "X4170M2 ", PPC},
5aecc3c8
EZ		 2330 {1, "ORACLE", "X4170 M3", PPC},
2331 {1, "ORACLE", "X4275 M3", PPC},
2332 {1, "ORACLE", "X6-2 ", PPC},
2333 {1, "ORACLE", "Sudbury ", PPC},
fbbcdc07
AH		 2334 {0, "", ""},
2335};
2336
29327c84 2337static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
fbbcdc07
AH		 2338{
2339 struct acpi_table_header hdr;
2340 struct hw_vendor_info *v_info;
2f86dc4c
DB		 2341 const struct x86_cpu_id *id;
2342 u64 misc_pwr;
2343
2344 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2345 if (id) {
2346 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2347 if ( misc_pwr & (1 << 8))
2348 return true;
2349 }
fbbcdc07 2350
c410833a
SK		 2351 if (acpi_disabled ||
2352 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
fbbcdc07
AH		 2353 return false;
2354
2355 for (v_info = vendor_info; v_info->valid; v_info++) {
c410833a 2356 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
966916ea 2357 !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2358 ACPI_OEM_TABLE_ID_SIZE))
2359 switch (v_info->oem_pwr_table) {
2360 case PSS:
2361 return intel_pstate_no_acpi_pss();
2362 case PPC:
aa4ea34d
EZ		 2363 return intel_pstate_has_acpi_ppc() &&
2364 (!force_load);
966916ea 2365 }
fbbcdc07
AH		 2366 }
2367
2368 return false;
2369}
d0ea59e1
RW		 2370
2371static void intel_pstate_request_control_from_smm(void)
2372{
2373 /*
2374 * It may be unsafe to request P-states control from SMM if _PPC support
2375 * has not been enabled.
2376 */
2377 if (acpi_ppc)
2378 acpi_processor_pstate_control();
2379}
fbbcdc07
AH		 2380#else /* CONFIG_ACPI not enabled */
2381static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
966916ea 2382static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
d0ea59e1 2383static inline void intel_pstate_request_control_from_smm(void) {}
fbbcdc07
AH		 2384#endif /* CONFIG_ACPI */
2385
7791e4aa
SP		 2386static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2387 { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2388 {}
2389};
2390
93f0822d
DB		 2391static int __init intel_pstate_init(void)
2392{
907cc908 2393 int cpu, rc = 0;
93f0822d 2394 const struct x86_cpu_id *id;
64df1fdf 2395 struct cpu_defaults *cpu_def;
93f0822d 2396
6be26498
DB		 2397 if (no_load)
2398 return -ENODEV;
2399
7791e4aa
SP		 2400 if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2401 copy_cpu_funcs(&core_params.funcs);
2402 hwp_active++;
984edbdc 2403 intel_pstate.attr = hwp_cpufreq_attrs;
7791e4aa
SP		 2404 goto hwp_cpu_matched;
2405 }
2406
93f0822d
DB		 2407 id = x86_match_cpu(intel_pstate_cpu_ids);
2408 if (!id)
2409 return -ENODEV;
2410
64df1fdf 2411 cpu_def = (struct cpu_defaults *)id->driver_data;
016c8150 2412
64df1fdf
BP		 2413 copy_pid_params(&cpu_def->pid_policy);
2414 copy_cpu_funcs(&cpu_def->funcs);
016c8150 2415
b563b4e3
DB		 2416 if (intel_pstate_msrs_not_valid())
2417 return -ENODEV;
2418
7791e4aa
SP		 2419hwp_cpu_matched:
2420 /*
2421 * The Intel pstate driver will be ignored if the platform
2422 * firmware has its own power management modes.
2423 */
2424 if (intel_pstate_platform_pwr_mgmt_exists())
2425 return -ENODEV;
2426
4836df17 2427 pr_info("Intel P-state driver initializing\n");
93f0822d 2428
b57ffac5 2429 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
93f0822d
DB		 2430 if (!all_cpu_data)
2431 return -ENOMEM;
93f0822d 2432
d64c3b0b
KCA		 2433 if (!hwp_active && hwp_only)
2434 goto out;
2435
d0ea59e1
RW		 2436 intel_pstate_request_control_from_smm();
2437
001c76f0 2438 rc = cpufreq_register_driver(intel_pstate_driver);
93f0822d
DB		 2439 if (rc)
2440 goto out;
2441
366430b5
RW		 2442 if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2443 pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2444 intel_pstate_debug_expose_params();
2445
93f0822d 2446 intel_pstate_sysfs_expose_params();
b69880f9 2447
7791e4aa 2448 if (hwp_active)
4836df17 2449 pr_info("HWP enabled\n");
7791e4aa 2450
93f0822d
DB		 2451 return rc;
2452out:
907cc908
DB		 2453 get_online_cpus();
2454 for_each_online_cpu(cpu) {
2455 if (all_cpu_data[cpu]) {
001c76f0
RW		 2456 if (intel_pstate_driver == &intel_pstate)
2457 intel_pstate_clear_update_util_hook(cpu);
2458
907cc908
DB		 2459 kfree(all_cpu_data[cpu]);
2460 }
2461 }
2462
2463 put_online_cpus();
2464 vfree(all_cpu_data);
93f0822d
DB		 2465 return -ENODEV;
2466}
2467device_initcall(intel_pstate_init);
2468
6be26498
DB		 2469static int __init intel_pstate_setup(char *str)
2470{
2471 if (!str)
2472 return -EINVAL;
2473
001c76f0 2474 if (!strcmp(str, "disable")) {
6be26498 2475 no_load = 1;
001c76f0
RW		 2476 } else if (!strcmp(str, "passive")) {
2477 pr_info("Passive mode enabled\n");
2478 intel_pstate_driver = &intel_cpufreq;
2479 no_hwp = 1;
2480 }
539342f6 2481 if (!strcmp(str, "no_hwp")) {
4836df17 2482 pr_info("HWP disabled\n");
2f86dc4c 2483 no_hwp = 1;
539342f6 2484 }
aa4ea34d
EZ		 2485 if (!strcmp(str, "force"))
2486 force_load = 1;
d64c3b0b
KCA		 2487 if (!strcmp(str, "hwp_only"))
2488 hwp_only = 1;
eae48f04
SP		 2489 if (!strcmp(str, "per_cpu_perf_limits"))
2490 per_cpu_limits = true;
9522a2ff
SP		 2491
2492#ifdef CONFIG_ACPI
2493 if (!strcmp(str, "support_acpi_ppc"))
2494 acpi_ppc = true;
2495#endif
2496
6be26498
DB		 2497 return 0;
2498}
2499early_param("intel_pstate", intel_pstate_setup);
2500
93f0822d
DB		 2501MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2502MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2503MODULE_LICENSE("GPL");
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