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Commit | Line | Data |
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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/ktime.h> | |
17 | #include <linux/hrtimer.h> | |
18 | #include <linux/tick.h> | |
19 | #include <linux/slab.h> | |
20 | #include <linux/sched.h> | |
21 | #include <linux/list.h> | |
22 | #include <linux/cpu.h> | |
23 | #include <linux/cpufreq.h> | |
24 | #include <linux/sysfs.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/fs.h> | |
27 | #include <linux/debugfs.h> | |
fbbcdc07 | 28 | #include <linux/acpi.h> |
d6472302 | 29 | #include <linux/vmalloc.h> |
93f0822d DB |
30 | #include <trace/events/power.h> |
31 | ||
32 | #include <asm/div64.h> | |
33 | #include <asm/msr.h> | |
34 | #include <asm/cpu_device_id.h> | |
64df1fdf | 35 | #include <asm/cpufeature.h> |
93f0822d | 36 | |
938d21a2 PL |
37 | #define ATOM_RATIOS 0x66a |
38 | #define ATOM_VIDS 0x66b | |
39 | #define ATOM_TURBO_RATIOS 0x66c | |
40 | #define ATOM_TURBO_VIDS 0x66d | |
61d8d2ab | 41 | |
f0fe3cd7 | 42 | #define FRAC_BITS 8 |
93f0822d DB |
43 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
44 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 45 | |
93f0822d DB |
46 | static inline int32_t mul_fp(int32_t x, int32_t y) |
47 | { | |
48 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
49 | } | |
50 | ||
7180dddf | 51 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 52 | { |
7180dddf | 53 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
54 | } |
55 | ||
d022a65e DB |
56 | static inline int ceiling_fp(int32_t x) |
57 | { | |
58 | int mask, ret; | |
59 | ||
60 | ret = fp_toint(x); | |
61 | mask = (1 << FRAC_BITS) - 1; | |
62 | if (x & mask) | |
63 | ret += 1; | |
64 | return ret; | |
65 | } | |
66 | ||
93f0822d | 67 | struct sample { |
d253d2a5 | 68 | int32_t core_pct_busy; |
157386b6 | 69 | int32_t busy_scaled; |
93f0822d DB |
70 | u64 aperf; |
71 | u64 mperf; | |
4055fad3 | 72 | u64 tsc; |
93f0822d | 73 | int freq; |
c4ee841f | 74 | ktime_t time; |
93f0822d DB |
75 | }; |
76 | ||
77 | struct pstate_data { | |
78 | int current_pstate; | |
79 | int min_pstate; | |
80 | int max_pstate; | |
3bcc6fa9 | 81 | int max_pstate_physical; |
b27580b0 | 82 | int scaling; |
93f0822d DB |
83 | int turbo_pstate; |
84 | }; | |
85 | ||
007bea09 | 86 | struct vid_data { |
21855ff5 DB |
87 | int min; |
88 | int max; | |
89 | int turbo; | |
007bea09 DB |
90 | int32_t ratio; |
91 | }; | |
92 | ||
93f0822d DB |
93 | struct _pid { |
94 | int setpoint; | |
95 | int32_t integral; | |
96 | int32_t p_gain; | |
97 | int32_t i_gain; | |
98 | int32_t d_gain; | |
99 | int deadband; | |
d253d2a5 | 100 | int32_t last_err; |
93f0822d DB |
101 | }; |
102 | ||
103 | struct cpudata { | |
104 | int cpu; | |
105 | ||
93f0822d DB |
106 | struct timer_list timer; |
107 | ||
93f0822d | 108 | struct pstate_data pstate; |
007bea09 | 109 | struct vid_data vid; |
93f0822d | 110 | struct _pid pid; |
93f0822d | 111 | |
c4ee841f | 112 | ktime_t last_sample_time; |
93f0822d DB |
113 | u64 prev_aperf; |
114 | u64 prev_mperf; | |
4055fad3 | 115 | u64 prev_tsc; |
d37e2b76 | 116 | struct sample sample; |
93f0822d DB |
117 | }; |
118 | ||
119 | static struct cpudata **all_cpu_data; | |
120 | struct pstate_adjust_policy { | |
121 | int sample_rate_ms; | |
122 | int deadband; | |
123 | int setpoint; | |
124 | int p_gain_pct; | |
125 | int d_gain_pct; | |
126 | int i_gain_pct; | |
127 | }; | |
128 | ||
016c8150 DB |
129 | struct pstate_funcs { |
130 | int (*get_max)(void); | |
3bcc6fa9 | 131 | int (*get_max_physical)(void); |
016c8150 DB |
132 | int (*get_min)(void); |
133 | int (*get_turbo)(void); | |
b27580b0 | 134 | int (*get_scaling)(void); |
007bea09 DB |
135 | void (*set)(struct cpudata*, int pstate); |
136 | void (*get_vid)(struct cpudata *); | |
157386b6 | 137 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
138 | }; |
139 | ||
016c8150 DB |
140 | struct cpu_defaults { |
141 | struct pstate_adjust_policy pid_policy; | |
142 | struct pstate_funcs funcs; | |
93f0822d DB |
143 | }; |
144 | ||
157386b6 | 145 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
e70eed2b | 146 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); |
157386b6 | 147 | |
016c8150 DB |
148 | static struct pstate_adjust_policy pid_params; |
149 | static struct pstate_funcs pstate_funcs; | |
2f86dc4c | 150 | static int hwp_active; |
016c8150 | 151 | |
93f0822d DB |
152 | struct perf_limits { |
153 | int no_turbo; | |
dd5fbf70 | 154 | int turbo_disabled; |
93f0822d DB |
155 | int max_perf_pct; |
156 | int min_perf_pct; | |
157 | int32_t max_perf; | |
158 | int32_t min_perf; | |
d8f469e9 DB |
159 | int max_policy_pct; |
160 | int max_sysfs_pct; | |
a0475992 KCA |
161 | int min_policy_pct; |
162 | int min_sysfs_pct; | |
93f0822d DB |
163 | }; |
164 | ||
51443fbf PB |
165 | static struct perf_limits performance_limits = { |
166 | .no_turbo = 0, | |
167 | .turbo_disabled = 0, | |
168 | .max_perf_pct = 100, | |
169 | .max_perf = int_tofp(1), | |
170 | .min_perf_pct = 100, | |
171 | .min_perf = int_tofp(1), | |
172 | .max_policy_pct = 100, | |
173 | .max_sysfs_pct = 100, | |
174 | .min_policy_pct = 0, | |
175 | .min_sysfs_pct = 0, | |
176 | }; | |
177 | ||
178 | static struct perf_limits powersave_limits = { | |
93f0822d | 179 | .no_turbo = 0, |
4521e1a0 | 180 | .turbo_disabled = 0, |
93f0822d DB |
181 | .max_perf_pct = 100, |
182 | .max_perf = int_tofp(1), | |
183 | .min_perf_pct = 0, | |
184 | .min_perf = 0, | |
d8f469e9 DB |
185 | .max_policy_pct = 100, |
186 | .max_sysfs_pct = 100, | |
a0475992 KCA |
187 | .min_policy_pct = 0, |
188 | .min_sysfs_pct = 0, | |
93f0822d DB |
189 | }; |
190 | ||
51443fbf PB |
191 | #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE |
192 | static struct perf_limits *limits = &performance_limits; | |
193 | #else | |
194 | static struct perf_limits *limits = &powersave_limits; | |
195 | #endif | |
196 | ||
93f0822d | 197 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 198 | int deadband, int integral) { |
93f0822d DB |
199 | pid->setpoint = setpoint; |
200 | pid->deadband = deadband; | |
201 | pid->integral = int_tofp(integral); | |
d98d099b | 202 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
203 | } |
204 | ||
205 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
206 | { | |
207 | pid->p_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
208 | } | |
209 | ||
210 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
211 | { | |
212 | pid->i_gain = div_fp(int_tofp(percent), int_tofp(100)); | |
213 | } | |
214 | ||
215 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
216 | { | |
93f0822d DB |
217 | pid->d_gain = div_fp(int_tofp(percent), int_tofp(100)); |
218 | } | |
219 | ||
d253d2a5 | 220 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 221 | { |
d253d2a5 | 222 | signed int result; |
93f0822d DB |
223 | int32_t pterm, dterm, fp_error; |
224 | int32_t integral_limit; | |
225 | ||
d253d2a5 | 226 | fp_error = int_tofp(pid->setpoint) - busy; |
93f0822d | 227 | |
d253d2a5 | 228 | if (abs(fp_error) <= int_tofp(pid->deadband)) |
93f0822d DB |
229 | return 0; |
230 | ||
231 | pterm = mul_fp(pid->p_gain, fp_error); | |
232 | ||
233 | pid->integral += fp_error; | |
234 | ||
e0d4c8f8 KCA |
235 | /* |
236 | * We limit the integral here so that it will never | |
237 | * get higher than 30. This prevents it from becoming | |
238 | * too large an input over long periods of time and allows | |
239 | * it to get factored out sooner. | |
240 | * | |
241 | * The value of 30 was chosen through experimentation. | |
242 | */ | |
93f0822d DB |
243 | integral_limit = int_tofp(30); |
244 | if (pid->integral > integral_limit) | |
245 | pid->integral = integral_limit; | |
246 | if (pid->integral < -integral_limit) | |
247 | pid->integral = -integral_limit; | |
248 | ||
d253d2a5 BS |
249 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
250 | pid->last_err = fp_error; | |
93f0822d DB |
251 | |
252 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 253 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
254 | return (signed int)fp_toint(result); |
255 | } | |
256 | ||
257 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
258 | { | |
016c8150 DB |
259 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
260 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
261 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 262 | |
2d8d1f18 | 263 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
264 | } |
265 | ||
93f0822d DB |
266 | static inline void intel_pstate_reset_all_pid(void) |
267 | { | |
268 | unsigned int cpu; | |
845c1cbe | 269 | |
93f0822d DB |
270 | for_each_online_cpu(cpu) { |
271 | if (all_cpu_data[cpu]) | |
272 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
273 | } | |
274 | } | |
275 | ||
4521e1a0 GM |
276 | static inline void update_turbo_state(void) |
277 | { | |
278 | u64 misc_en; | |
279 | struct cpudata *cpu; | |
280 | ||
281 | cpu = all_cpu_data[0]; | |
282 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
51443fbf | 283 | limits->turbo_disabled = |
4521e1a0 GM |
284 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
285 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
286 | } | |
287 | ||
2f86dc4c DB |
288 | static void intel_pstate_hwp_set(void) |
289 | { | |
74da56ce KCA |
290 | int min, hw_min, max, hw_max, cpu, range, adj_range; |
291 | u64 value, cap; | |
292 | ||
293 | rdmsrl(MSR_HWP_CAPABILITIES, cap); | |
294 | hw_min = HWP_LOWEST_PERF(cap); | |
295 | hw_max = HWP_HIGHEST_PERF(cap); | |
296 | range = hw_max - hw_min; | |
2f86dc4c DB |
297 | |
298 | get_online_cpus(); | |
299 | ||
300 | for_each_online_cpu(cpu) { | |
301 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); | |
51443fbf | 302 | adj_range = limits->min_perf_pct * range / 100; |
74da56ce | 303 | min = hw_min + adj_range; |
2f86dc4c DB |
304 | value &= ~HWP_MIN_PERF(~0L); |
305 | value |= HWP_MIN_PERF(min); | |
306 | ||
51443fbf | 307 | adj_range = limits->max_perf_pct * range / 100; |
74da56ce | 308 | max = hw_min + adj_range; |
51443fbf | 309 | if (limits->no_turbo) { |
74da56ce KCA |
310 | hw_max = HWP_GUARANTEED_PERF(cap); |
311 | if (hw_max < max) | |
312 | max = hw_max; | |
2f86dc4c DB |
313 | } |
314 | ||
315 | value &= ~HWP_MAX_PERF(~0L); | |
316 | value |= HWP_MAX_PERF(max); | |
317 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
318 | } | |
319 | ||
320 | put_online_cpus(); | |
321 | } | |
322 | ||
93f0822d DB |
323 | /************************** debugfs begin ************************/ |
324 | static int pid_param_set(void *data, u64 val) | |
325 | { | |
326 | *(u32 *)data = val; | |
327 | intel_pstate_reset_all_pid(); | |
328 | return 0; | |
329 | } | |
845c1cbe | 330 | |
93f0822d DB |
331 | static int pid_param_get(void *data, u64 *val) |
332 | { | |
333 | *val = *(u32 *)data; | |
334 | return 0; | |
335 | } | |
2d8d1f18 | 336 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
337 | |
338 | struct pid_param { | |
339 | char *name; | |
340 | void *value; | |
341 | }; | |
342 | ||
343 | static struct pid_param pid_files[] = { | |
016c8150 DB |
344 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
345 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
346 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
347 | {"deadband", &pid_params.deadband}, | |
348 | {"setpoint", &pid_params.setpoint}, | |
349 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
350 | {NULL, NULL} |
351 | }; | |
352 | ||
317dd50e | 353 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 354 | { |
317dd50e | 355 | struct dentry *debugfs_parent; |
93f0822d DB |
356 | int i = 0; |
357 | ||
2f86dc4c DB |
358 | if (hwp_active) |
359 | return; | |
93f0822d DB |
360 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
361 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
362 | return; | |
363 | while (pid_files[i].name) { | |
364 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
365 | debugfs_parent, pid_files[i].value, |
366 | &fops_pid_param); | |
93f0822d DB |
367 | i++; |
368 | } | |
369 | } | |
370 | ||
371 | /************************** debugfs end ************************/ | |
372 | ||
373 | /************************** sysfs begin ************************/ | |
374 | #define show_one(file_name, object) \ | |
375 | static ssize_t show_##file_name \ | |
376 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
377 | { \ | |
51443fbf | 378 | return sprintf(buf, "%u\n", limits->object); \ |
93f0822d DB |
379 | } |
380 | ||
d01b1f48 KCA |
381 | static ssize_t show_turbo_pct(struct kobject *kobj, |
382 | struct attribute *attr, char *buf) | |
383 | { | |
384 | struct cpudata *cpu; | |
385 | int total, no_turbo, turbo_pct; | |
386 | uint32_t turbo_fp; | |
387 | ||
388 | cpu = all_cpu_data[0]; | |
389 | ||
390 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
391 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
392 | turbo_fp = div_fp(int_tofp(no_turbo), int_tofp(total)); | |
393 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); | |
394 | return sprintf(buf, "%u\n", turbo_pct); | |
395 | } | |
396 | ||
0522424e KCA |
397 | static ssize_t show_num_pstates(struct kobject *kobj, |
398 | struct attribute *attr, char *buf) | |
399 | { | |
400 | struct cpudata *cpu; | |
401 | int total; | |
402 | ||
403 | cpu = all_cpu_data[0]; | |
404 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
405 | return sprintf(buf, "%u\n", total); | |
406 | } | |
407 | ||
4521e1a0 GM |
408 | static ssize_t show_no_turbo(struct kobject *kobj, |
409 | struct attribute *attr, char *buf) | |
410 | { | |
411 | ssize_t ret; | |
412 | ||
413 | update_turbo_state(); | |
51443fbf PB |
414 | if (limits->turbo_disabled) |
415 | ret = sprintf(buf, "%u\n", limits->turbo_disabled); | |
4521e1a0 | 416 | else |
51443fbf | 417 | ret = sprintf(buf, "%u\n", limits->no_turbo); |
4521e1a0 GM |
418 | |
419 | return ret; | |
420 | } | |
421 | ||
93f0822d | 422 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 423 | const char *buf, size_t count) |
93f0822d DB |
424 | { |
425 | unsigned int input; | |
426 | int ret; | |
845c1cbe | 427 | |
93f0822d DB |
428 | ret = sscanf(buf, "%u", &input); |
429 | if (ret != 1) | |
430 | return -EINVAL; | |
4521e1a0 GM |
431 | |
432 | update_turbo_state(); | |
51443fbf | 433 | if (limits->turbo_disabled) { |
f16255eb | 434 | pr_warn("intel_pstate: Turbo disabled by BIOS or unavailable on processor\n"); |
4521e1a0 | 435 | return -EPERM; |
dd5fbf70 | 436 | } |
2f86dc4c | 437 | |
51443fbf | 438 | limits->no_turbo = clamp_t(int, input, 0, 1); |
4521e1a0 | 439 | |
2f86dc4c DB |
440 | if (hwp_active) |
441 | intel_pstate_hwp_set(); | |
442 | ||
93f0822d DB |
443 | return count; |
444 | } | |
445 | ||
446 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 447 | const char *buf, size_t count) |
93f0822d DB |
448 | { |
449 | unsigned int input; | |
450 | int ret; | |
845c1cbe | 451 | |
93f0822d DB |
452 | ret = sscanf(buf, "%u", &input); |
453 | if (ret != 1) | |
454 | return -EINVAL; | |
455 | ||
51443fbf PB |
456 | limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); |
457 | limits->max_perf_pct = min(limits->max_policy_pct, | |
458 | limits->max_sysfs_pct); | |
459 | limits->max_perf_pct = max(limits->min_policy_pct, | |
460 | limits->max_perf_pct); | |
461 | limits->max_perf_pct = max(limits->min_perf_pct, | |
462 | limits->max_perf_pct); | |
463 | limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), | |
464 | int_tofp(100)); | |
845c1cbe | 465 | |
2f86dc4c DB |
466 | if (hwp_active) |
467 | intel_pstate_hwp_set(); | |
93f0822d DB |
468 | return count; |
469 | } | |
470 | ||
471 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 472 | const char *buf, size_t count) |
93f0822d DB |
473 | { |
474 | unsigned int input; | |
475 | int ret; | |
845c1cbe | 476 | |
93f0822d DB |
477 | ret = sscanf(buf, "%u", &input); |
478 | if (ret != 1) | |
479 | return -EINVAL; | |
a0475992 | 480 | |
51443fbf PB |
481 | limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); |
482 | limits->min_perf_pct = max(limits->min_policy_pct, | |
483 | limits->min_sysfs_pct); | |
484 | limits->min_perf_pct = min(limits->max_policy_pct, | |
485 | limits->min_perf_pct); | |
486 | limits->min_perf_pct = min(limits->max_perf_pct, | |
487 | limits->min_perf_pct); | |
488 | limits->min_perf = div_fp(int_tofp(limits->min_perf_pct), | |
489 | int_tofp(100)); | |
93f0822d | 490 | |
2f86dc4c DB |
491 | if (hwp_active) |
492 | intel_pstate_hwp_set(); | |
93f0822d DB |
493 | return count; |
494 | } | |
495 | ||
93f0822d DB |
496 | show_one(max_perf_pct, max_perf_pct); |
497 | show_one(min_perf_pct, min_perf_pct); | |
498 | ||
499 | define_one_global_rw(no_turbo); | |
500 | define_one_global_rw(max_perf_pct); | |
501 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 502 | define_one_global_ro(turbo_pct); |
0522424e | 503 | define_one_global_ro(num_pstates); |
93f0822d DB |
504 | |
505 | static struct attribute *intel_pstate_attributes[] = { | |
506 | &no_turbo.attr, | |
507 | &max_perf_pct.attr, | |
508 | &min_perf_pct.attr, | |
d01b1f48 | 509 | &turbo_pct.attr, |
0522424e | 510 | &num_pstates.attr, |
93f0822d DB |
511 | NULL |
512 | }; | |
513 | ||
514 | static struct attribute_group intel_pstate_attr_group = { | |
515 | .attrs = intel_pstate_attributes, | |
516 | }; | |
93f0822d | 517 | |
317dd50e | 518 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 519 | { |
317dd50e | 520 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
521 | int rc; |
522 | ||
523 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
524 | &cpu_subsys.dev_root->kobj); | |
525 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 526 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
527 | BUG_ON(rc); |
528 | } | |
93f0822d | 529 | /************************** sysfs end ************************/ |
2f86dc4c | 530 | |
ba88d433 | 531 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 532 | { |
ba88d433 | 533 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
534 | } |
535 | ||
938d21a2 | 536 | static int atom_get_min_pstate(void) |
19e77c28 DB |
537 | { |
538 | u64 value; | |
845c1cbe | 539 | |
938d21a2 | 540 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 541 | return (value >> 8) & 0x7F; |
19e77c28 DB |
542 | } |
543 | ||
938d21a2 | 544 | static int atom_get_max_pstate(void) |
19e77c28 DB |
545 | { |
546 | u64 value; | |
845c1cbe | 547 | |
938d21a2 | 548 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 549 | return (value >> 16) & 0x7F; |
19e77c28 | 550 | } |
93f0822d | 551 | |
938d21a2 | 552 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
553 | { |
554 | u64 value; | |
845c1cbe | 555 | |
938d21a2 | 556 | rdmsrl(ATOM_TURBO_RATIOS, value); |
c16ed060 | 557 | return value & 0x7F; |
61d8d2ab DB |
558 | } |
559 | ||
938d21a2 | 560 | static void atom_set_pstate(struct cpudata *cpudata, int pstate) |
007bea09 DB |
561 | { |
562 | u64 val; | |
563 | int32_t vid_fp; | |
564 | u32 vid; | |
565 | ||
144c8e17 | 566 | val = (u64)pstate << 8; |
51443fbf | 567 | if (limits->no_turbo && !limits->turbo_disabled) |
007bea09 DB |
568 | val |= (u64)1 << 32; |
569 | ||
570 | vid_fp = cpudata->vid.min + mul_fp( | |
571 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
572 | cpudata->vid.ratio); | |
573 | ||
574 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 575 | vid = ceiling_fp(vid_fp); |
007bea09 | 576 | |
21855ff5 DB |
577 | if (pstate > cpudata->pstate.max_pstate) |
578 | vid = cpudata->vid.turbo; | |
579 | ||
007bea09 DB |
580 | val |= vid; |
581 | ||
0dd23f94 | 582 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
007bea09 DB |
583 | } |
584 | ||
1421df63 | 585 | static int silvermont_get_scaling(void) |
b27580b0 DB |
586 | { |
587 | u64 value; | |
588 | int i; | |
1421df63 PL |
589 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
590 | static int silvermont_freq_table[] = { | |
591 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
592 | |
593 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
594 | i = value & 0x7; |
595 | WARN_ON(i > 4); | |
b27580b0 | 596 | |
1421df63 PL |
597 | return silvermont_freq_table[i]; |
598 | } | |
b27580b0 | 599 | |
1421df63 PL |
600 | static int airmont_get_scaling(void) |
601 | { | |
602 | u64 value; | |
603 | int i; | |
604 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
605 | static int airmont_freq_table[] = { | |
606 | 83300, 100000, 133300, 116700, 80000, | |
607 | 93300, 90000, 88900, 87500}; | |
608 | ||
609 | rdmsrl(MSR_FSB_FREQ, value); | |
610 | i = value & 0xF; | |
611 | WARN_ON(i > 8); | |
612 | ||
613 | return airmont_freq_table[i]; | |
b27580b0 DB |
614 | } |
615 | ||
938d21a2 | 616 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
617 | { |
618 | u64 value; | |
619 | ||
938d21a2 | 620 | rdmsrl(ATOM_VIDS, value); |
c16ed060 DB |
621 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
622 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
623 | cpudata->vid.ratio = div_fp( |
624 | cpudata->vid.max - cpudata->vid.min, | |
625 | int_tofp(cpudata->pstate.max_pstate - | |
626 | cpudata->pstate.min_pstate)); | |
21855ff5 | 627 | |
938d21a2 | 628 | rdmsrl(ATOM_TURBO_VIDS, value); |
21855ff5 | 629 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
630 | } |
631 | ||
016c8150 | 632 | static int core_get_min_pstate(void) |
93f0822d DB |
633 | { |
634 | u64 value; | |
845c1cbe | 635 | |
05e99c8c | 636 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
637 | return (value >> 40) & 0xFF; |
638 | } | |
639 | ||
3bcc6fa9 | 640 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
641 | { |
642 | u64 value; | |
845c1cbe | 643 | |
05e99c8c | 644 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
645 | return (value >> 8) & 0xFF; |
646 | } | |
647 | ||
016c8150 | 648 | static int core_get_max_pstate(void) |
93f0822d | 649 | { |
6a35fc2d SP |
650 | u64 tar; |
651 | u64 plat_info; | |
652 | int max_pstate; | |
653 | int err; | |
654 | ||
655 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
656 | max_pstate = (plat_info >> 8) & 0xFF; | |
657 | ||
658 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); | |
659 | if (!err) { | |
660 | /* Do some sanity checking for safety */ | |
661 | if (plat_info & 0x600000000) { | |
662 | u64 tdp_ctrl; | |
663 | u64 tdp_ratio; | |
664 | int tdp_msr; | |
665 | ||
666 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
667 | if (err) | |
668 | goto skip_tar; | |
669 | ||
670 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + tdp_ctrl; | |
671 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); | |
672 | if (err) | |
673 | goto skip_tar; | |
674 | ||
675 | if (tdp_ratio - 1 == tar) { | |
676 | max_pstate = tar; | |
677 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
678 | } else { | |
679 | goto skip_tar; | |
680 | } | |
681 | } | |
682 | } | |
845c1cbe | 683 | |
6a35fc2d SP |
684 | skip_tar: |
685 | return max_pstate; | |
93f0822d DB |
686 | } |
687 | ||
016c8150 | 688 | static int core_get_turbo_pstate(void) |
93f0822d DB |
689 | { |
690 | u64 value; | |
691 | int nont, ret; | |
845c1cbe | 692 | |
05e99c8c | 693 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); |
016c8150 | 694 | nont = core_get_max_pstate(); |
285cb990 | 695 | ret = (value) & 255; |
93f0822d DB |
696 | if (ret <= nont) |
697 | ret = nont; | |
698 | return ret; | |
699 | } | |
700 | ||
b27580b0 DB |
701 | static inline int core_get_scaling(void) |
702 | { | |
703 | return 100000; | |
704 | } | |
705 | ||
007bea09 | 706 | static void core_set_pstate(struct cpudata *cpudata, int pstate) |
016c8150 DB |
707 | { |
708 | u64 val; | |
709 | ||
144c8e17 | 710 | val = (u64)pstate << 8; |
51443fbf | 711 | if (limits->no_turbo && !limits->turbo_disabled) |
016c8150 DB |
712 | val |= (u64)1 << 32; |
713 | ||
bb18008f | 714 | wrmsrl_on_cpu(cpudata->cpu, MSR_IA32_PERF_CTL, val); |
016c8150 DB |
715 | } |
716 | ||
b34ef932 DC |
717 | static int knl_get_turbo_pstate(void) |
718 | { | |
719 | u64 value; | |
720 | int nont, ret; | |
721 | ||
722 | rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value); | |
723 | nont = core_get_max_pstate(); | |
724 | ret = (((value) >> 8) & 0xFF); | |
725 | if (ret <= nont) | |
726 | ret = nont; | |
727 | return ret; | |
728 | } | |
729 | ||
016c8150 DB |
730 | static struct cpu_defaults core_params = { |
731 | .pid_policy = { | |
732 | .sample_rate_ms = 10, | |
733 | .deadband = 0, | |
734 | .setpoint = 97, | |
735 | .p_gain_pct = 20, | |
736 | .d_gain_pct = 0, | |
737 | .i_gain_pct = 0, | |
738 | }, | |
739 | .funcs = { | |
740 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 741 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
742 | .get_min = core_get_min_pstate, |
743 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 744 | .get_scaling = core_get_scaling, |
016c8150 | 745 | .set = core_set_pstate, |
157386b6 | 746 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
747 | }, |
748 | }; | |
749 | ||
1421df63 PL |
750 | static struct cpu_defaults silvermont_params = { |
751 | .pid_policy = { | |
752 | .sample_rate_ms = 10, | |
753 | .deadband = 0, | |
754 | .setpoint = 60, | |
755 | .p_gain_pct = 14, | |
756 | .d_gain_pct = 0, | |
757 | .i_gain_pct = 4, | |
758 | }, | |
759 | .funcs = { | |
760 | .get_max = atom_get_max_pstate, | |
761 | .get_max_physical = atom_get_max_pstate, | |
762 | .get_min = atom_get_min_pstate, | |
763 | .get_turbo = atom_get_turbo_pstate, | |
764 | .set = atom_set_pstate, | |
765 | .get_scaling = silvermont_get_scaling, | |
766 | .get_vid = atom_get_vid, | |
e70eed2b | 767 | .get_target_pstate = get_target_pstate_use_cpu_load, |
1421df63 PL |
768 | }, |
769 | }; | |
770 | ||
771 | static struct cpu_defaults airmont_params = { | |
19e77c28 DB |
772 | .pid_policy = { |
773 | .sample_rate_ms = 10, | |
774 | .deadband = 0, | |
6a82ba6d | 775 | .setpoint = 60, |
19e77c28 DB |
776 | .p_gain_pct = 14, |
777 | .d_gain_pct = 0, | |
778 | .i_gain_pct = 4, | |
779 | }, | |
780 | .funcs = { | |
938d21a2 PL |
781 | .get_max = atom_get_max_pstate, |
782 | .get_max_physical = atom_get_max_pstate, | |
783 | .get_min = atom_get_min_pstate, | |
784 | .get_turbo = atom_get_turbo_pstate, | |
785 | .set = atom_set_pstate, | |
1421df63 | 786 | .get_scaling = airmont_get_scaling, |
938d21a2 | 787 | .get_vid = atom_get_vid, |
e70eed2b | 788 | .get_target_pstate = get_target_pstate_use_cpu_load, |
19e77c28 DB |
789 | }, |
790 | }; | |
791 | ||
b34ef932 DC |
792 | static struct cpu_defaults knl_params = { |
793 | .pid_policy = { | |
794 | .sample_rate_ms = 10, | |
795 | .deadband = 0, | |
796 | .setpoint = 97, | |
797 | .p_gain_pct = 20, | |
798 | .d_gain_pct = 0, | |
799 | .i_gain_pct = 0, | |
800 | }, | |
801 | .funcs = { | |
802 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 803 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
804 | .get_min = core_get_min_pstate, |
805 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 806 | .get_scaling = core_get_scaling, |
b34ef932 | 807 | .set = core_set_pstate, |
157386b6 | 808 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
809 | }, |
810 | }; | |
811 | ||
93f0822d DB |
812 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
813 | { | |
814 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 815 | int max_perf_adj; |
93f0822d | 816 | int min_perf; |
845c1cbe | 817 | |
51443fbf | 818 | if (limits->no_turbo || limits->turbo_disabled) |
93f0822d DB |
819 | max_perf = cpu->pstate.max_pstate; |
820 | ||
e0d4c8f8 KCA |
821 | /* |
822 | * performance can be limited by user through sysfs, by cpufreq | |
823 | * policy, or by cpu specific default values determined through | |
824 | * experimentation. | |
825 | */ | |
799281a3 RW |
826 | max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits->max_perf)); |
827 | *max = clamp_t(int, max_perf_adj, | |
828 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 829 | |
799281a3 RW |
830 | min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits->min_perf)); |
831 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); | |
93f0822d DB |
832 | } |
833 | ||
6c1e4591 | 834 | static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate, bool force) |
93f0822d DB |
835 | { |
836 | int max_perf, min_perf; | |
837 | ||
6c1e4591 DS |
838 | if (force) { |
839 | update_turbo_state(); | |
93f0822d | 840 | |
6c1e4591 | 841 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); |
93f0822d | 842 | |
6c1e4591 | 843 | pstate = clamp_t(int, pstate, min_perf, max_perf); |
93f0822d | 844 | |
6c1e4591 DS |
845 | if (pstate == cpu->pstate.current_pstate) |
846 | return; | |
847 | } | |
b27580b0 | 848 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
35363e94 | 849 | |
93f0822d | 850 | cpu->pstate.current_pstate = pstate; |
93f0822d | 851 | |
007bea09 | 852 | pstate_funcs.set(cpu, pstate); |
93f0822d DB |
853 | } |
854 | ||
93f0822d DB |
855 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
856 | { | |
016c8150 DB |
857 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
858 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 859 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 860 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 861 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 862 | |
007bea09 DB |
863 | if (pstate_funcs.get_vid) |
864 | pstate_funcs.get_vid(cpu); | |
6c1e4591 | 865 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
866 | } |
867 | ||
6b17ddb2 | 868 | static inline void intel_pstate_calc_busy(struct cpudata *cpu) |
93f0822d | 869 | { |
6b17ddb2 | 870 | struct sample *sample = &cpu->sample; |
bf810222 | 871 | int64_t core_pct; |
93f0822d | 872 | |
bf810222 | 873 | core_pct = int_tofp(sample->aperf) * int_tofp(100); |
78e27086 | 874 | core_pct = div64_u64(core_pct, int_tofp(sample->mperf)); |
e66c1768 | 875 | |
fcb6a15c | 876 | sample->freq = fp_toint( |
b27580b0 | 877 | mul_fp(int_tofp( |
3bcc6fa9 SP |
878 | cpu->pstate.max_pstate_physical * |
879 | cpu->pstate.scaling / 100), | |
b27580b0 | 880 | core_pct)); |
fcb6a15c | 881 | |
bf810222 | 882 | sample->core_pct_busy = (int32_t)core_pct; |
93f0822d DB |
883 | } |
884 | ||
885 | static inline void intel_pstate_sample(struct cpudata *cpu) | |
886 | { | |
93f0822d | 887 | u64 aperf, mperf; |
4ab60c3f | 888 | unsigned long flags; |
4055fad3 | 889 | u64 tsc; |
93f0822d | 890 | |
4ab60c3f | 891 | local_irq_save(flags); |
93f0822d DB |
892 | rdmsrl(MSR_IA32_APERF, aperf); |
893 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b PL |
894 | tsc = rdtsc(); |
895 | if ((cpu->prev_mperf == mperf) || (cpu->prev_tsc == tsc)) { | |
8e601a9f SP |
896 | local_irq_restore(flags); |
897 | return; | |
898 | } | |
4ab60c3f | 899 | local_irq_restore(flags); |
b69880f9 | 900 | |
c4ee841f DB |
901 | cpu->last_sample_time = cpu->sample.time; |
902 | cpu->sample.time = ktime_get(); | |
d37e2b76 DB |
903 | cpu->sample.aperf = aperf; |
904 | cpu->sample.mperf = mperf; | |
4055fad3 | 905 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
906 | cpu->sample.aperf -= cpu->prev_aperf; |
907 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 908 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 909 | |
6b17ddb2 | 910 | intel_pstate_calc_busy(cpu); |
93f0822d | 911 | |
93f0822d DB |
912 | cpu->prev_aperf = aperf; |
913 | cpu->prev_mperf = mperf; | |
4055fad3 | 914 | cpu->prev_tsc = tsc; |
93f0822d DB |
915 | } |
916 | ||
2f86dc4c DB |
917 | static inline void intel_hwp_set_sample_time(struct cpudata *cpu) |
918 | { | |
919 | int delay; | |
920 | ||
921 | delay = msecs_to_jiffies(50); | |
922 | mod_timer_pinned(&cpu->timer, jiffies + delay); | |
923 | } | |
924 | ||
93f0822d DB |
925 | static inline void intel_pstate_set_sample_time(struct cpudata *cpu) |
926 | { | |
abf013bf | 927 | int delay; |
93f0822d | 928 | |
abf013bf | 929 | delay = msecs_to_jiffies(pid_params.sample_rate_ms); |
93f0822d DB |
930 | mod_timer_pinned(&cpu->timer, jiffies + delay); |
931 | } | |
932 | ||
e70eed2b PL |
933 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
934 | { | |
935 | struct sample *sample = &cpu->sample; | |
936 | int32_t cpu_load; | |
937 | ||
938 | /* | |
939 | * The load can be estimated as the ratio of the mperf counter | |
940 | * running at a constant frequency during active periods | |
941 | * (C0) and the time stamp counter running at the same frequency | |
942 | * also during C-states. | |
943 | */ | |
944 | cpu_load = div64_u64(int_tofp(100) * sample->mperf, sample->tsc); | |
945 | ||
946 | cpu->sample.busy_scaled = cpu_load; | |
947 | ||
948 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, cpu_load); | |
949 | } | |
950 | ||
951 | ||
157386b6 | 952 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 953 | { |
c4ee841f | 954 | int32_t core_busy, max_pstate, current_pstate, sample_ratio; |
7180dddf | 955 | s64 duration_us; |
c4ee841f | 956 | u32 sample_time; |
93f0822d | 957 | |
e0d4c8f8 KCA |
958 | /* |
959 | * core_busy is the ratio of actual performance to max | |
960 | * max_pstate is the max non turbo pstate available | |
961 | * current_pstate was the pstate that was requested during | |
962 | * the last sample period. | |
963 | * | |
964 | * We normalize core_busy, which was our actual percent | |
965 | * performance to what we requested during the last sample | |
966 | * period. The result will be a percentage of busy at a | |
967 | * specified pstate. | |
968 | */ | |
d37e2b76 | 969 | core_busy = cpu->sample.core_pct_busy; |
3bcc6fa9 | 970 | max_pstate = int_tofp(cpu->pstate.max_pstate_physical); |
93f0822d | 971 | current_pstate = int_tofp(cpu->pstate.current_pstate); |
e66c1768 | 972 | core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate)); |
c4ee841f | 973 | |
e0d4c8f8 KCA |
974 | /* |
975 | * Since we have a deferred timer, it will not fire unless | |
976 | * we are in C0. So, determine if the actual elapsed time | |
977 | * is significantly greater (3x) than our sample interval. If it | |
978 | * is, then we were idle for a long enough period of time | |
979 | * to adjust our busyness. | |
980 | */ | |
285cb990 | 981 | sample_time = pid_params.sample_rate_ms * USEC_PER_MSEC; |
7180dddf PB |
982 | duration_us = ktime_us_delta(cpu->sample.time, |
983 | cpu->last_sample_time); | |
c4ee841f DB |
984 | if (duration_us > sample_time * 3) { |
985 | sample_ratio = div_fp(int_tofp(sample_time), | |
c410833a | 986 | int_tofp(duration_us)); |
c4ee841f DB |
987 | core_busy = mul_fp(core_busy, sample_ratio); |
988 | } | |
989 | ||
157386b6 PL |
990 | cpu->sample.busy_scaled = core_busy; |
991 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, core_busy); | |
93f0822d DB |
992 | } |
993 | ||
994 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) | |
995 | { | |
157386b6 | 996 | int from, target_pstate; |
4055fad3 DS |
997 | struct sample *sample; |
998 | ||
999 | from = cpu->pstate.current_pstate; | |
93f0822d | 1000 | |
157386b6 | 1001 | target_pstate = pstate_funcs.get_target_pstate(cpu); |
93f0822d | 1002 | |
157386b6 | 1003 | intel_pstate_set_pstate(cpu, target_pstate, true); |
4055fad3 DS |
1004 | |
1005 | sample = &cpu->sample; | |
1006 | trace_pstate_sample(fp_toint(sample->core_pct_busy), | |
157386b6 | 1007 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1008 | from, |
1009 | cpu->pstate.current_pstate, | |
1010 | sample->mperf, | |
1011 | sample->aperf, | |
1012 | sample->tsc, | |
1013 | sample->freq); | |
93f0822d DB |
1014 | } |
1015 | ||
2f86dc4c DB |
1016 | static void intel_hwp_timer_func(unsigned long __data) |
1017 | { | |
1018 | struct cpudata *cpu = (struct cpudata *) __data; | |
1019 | ||
1020 | intel_pstate_sample(cpu); | |
1021 | intel_hwp_set_sample_time(cpu); | |
1022 | } | |
1023 | ||
93f0822d DB |
1024 | static void intel_pstate_timer_func(unsigned long __data) |
1025 | { | |
1026 | struct cpudata *cpu = (struct cpudata *) __data; | |
1027 | ||
1028 | intel_pstate_sample(cpu); | |
b69880f9 | 1029 | |
ca182aee | 1030 | intel_pstate_adjust_busy_pstate(cpu); |
b69880f9 | 1031 | |
93f0822d DB |
1032 | intel_pstate_set_sample_time(cpu); |
1033 | } | |
1034 | ||
1035 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1036 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1037 | (unsigned long)&policy } | |
93f0822d DB |
1038 | |
1039 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
016c8150 DB |
1040 | ICPU(0x2a, core_params), |
1041 | ICPU(0x2d, core_params), | |
1421df63 | 1042 | ICPU(0x37, silvermont_params), |
016c8150 DB |
1043 | ICPU(0x3a, core_params), |
1044 | ICPU(0x3c, core_params), | |
c7e241df | 1045 | ICPU(0x3d, core_params), |
016c8150 DB |
1046 | ICPU(0x3e, core_params), |
1047 | ICPU(0x3f, core_params), | |
1048 | ICPU(0x45, core_params), | |
1049 | ICPU(0x46, core_params), | |
43f8a966 | 1050 | ICPU(0x47, core_params), |
1421df63 | 1051 | ICPU(0x4c, airmont_params), |
7ab0256e | 1052 | ICPU(0x4e, core_params), |
c7e241df | 1053 | ICPU(0x4f, core_params), |
1c939123 | 1054 | ICPU(0x5e, core_params), |
c7e241df | 1055 | ICPU(0x56, core_params), |
b34ef932 | 1056 | ICPU(0x57, knl_params), |
93f0822d DB |
1057 | {} |
1058 | }; | |
1059 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1060 | ||
2f86dc4c DB |
1061 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] = { |
1062 | ICPU(0x56, core_params), | |
1063 | {} | |
1064 | }; | |
1065 | ||
93f0822d DB |
1066 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1067 | { | |
93f0822d DB |
1068 | struct cpudata *cpu; |
1069 | ||
c0348717 DB |
1070 | if (!all_cpu_data[cpunum]) |
1071 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
1072 | GFP_KERNEL); | |
93f0822d DB |
1073 | if (!all_cpu_data[cpunum]) |
1074 | return -ENOMEM; | |
1075 | ||
1076 | cpu = all_cpu_data[cpunum]; | |
1077 | ||
93f0822d | 1078 | cpu->cpu = cpunum; |
ba88d433 KCA |
1079 | |
1080 | if (hwp_active) | |
1081 | intel_pstate_hwp_enable(cpu); | |
1082 | ||
179e8471 | 1083 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1084 | |
93f0822d | 1085 | init_timer_deferrable(&cpu->timer); |
2d8d1f18 | 1086 | cpu->timer.data = (unsigned long)cpu; |
93f0822d | 1087 | cpu->timer.expires = jiffies + HZ/100; |
2f86dc4c DB |
1088 | |
1089 | if (!hwp_active) | |
1090 | cpu->timer.function = intel_pstate_timer_func; | |
1091 | else | |
1092 | cpu->timer.function = intel_hwp_timer_func; | |
1093 | ||
93f0822d | 1094 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 1095 | intel_pstate_sample(cpu); |
93f0822d DB |
1096 | |
1097 | add_timer_on(&cpu->timer, cpunum); | |
1098 | ||
f16255eb | 1099 | pr_debug("intel_pstate: controlling: cpu %d\n", cpunum); |
93f0822d DB |
1100 | |
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1105 | { | |
1106 | struct sample *sample; | |
1107 | struct cpudata *cpu; | |
1108 | ||
1109 | cpu = all_cpu_data[cpu_num]; | |
1110 | if (!cpu) | |
1111 | return 0; | |
d37e2b76 | 1112 | sample = &cpu->sample; |
93f0822d DB |
1113 | return sample->freq; |
1114 | } | |
1115 | ||
1116 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) | |
1117 | { | |
d3929b83 DB |
1118 | if (!policy->cpuinfo.max_freq) |
1119 | return -ENODEV; | |
1120 | ||
630ec286 SP |
1121 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE && |
1122 | policy->max >= policy->cpuinfo.max_freq) { | |
51443fbf PB |
1123 | pr_debug("intel_pstate: set performance\n"); |
1124 | limits = &performance_limits; | |
584ee3dc AY |
1125 | if (hwp_active) |
1126 | intel_pstate_hwp_set(); | |
d1b68485 | 1127 | return 0; |
93f0822d | 1128 | } |
2f86dc4c | 1129 | |
51443fbf PB |
1130 | pr_debug("intel_pstate: set powersave\n"); |
1131 | limits = &powersave_limits; | |
1132 | limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; | |
1133 | limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); | |
8478f539 PB |
1134 | limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, |
1135 | policy->cpuinfo.max_freq); | |
51443fbf | 1136 | limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); |
43717aad CY |
1137 | |
1138 | /* Normalize user input to [min_policy_pct, max_policy_pct] */ | |
51443fbf PB |
1139 | limits->min_perf_pct = max(limits->min_policy_pct, |
1140 | limits->min_sysfs_pct); | |
1141 | limits->min_perf_pct = min(limits->max_policy_pct, | |
1142 | limits->min_perf_pct); | |
1143 | limits->max_perf_pct = min(limits->max_policy_pct, | |
1144 | limits->max_sysfs_pct); | |
1145 | limits->max_perf_pct = max(limits->min_policy_pct, | |
1146 | limits->max_perf_pct); | |
785ee278 | 1147 | limits->max_perf = round_up(limits->max_perf, 8); |
43717aad CY |
1148 | |
1149 | /* Make sure min_perf_pct <= max_perf_pct */ | |
51443fbf | 1150 | limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); |
43717aad | 1151 | |
51443fbf PB |
1152 | limits->min_perf = div_fp(int_tofp(limits->min_perf_pct), |
1153 | int_tofp(100)); | |
1154 | limits->max_perf = div_fp(int_tofp(limits->max_perf_pct), | |
1155 | int_tofp(100)); | |
93f0822d | 1156 | |
2f86dc4c DB |
1157 | if (hwp_active) |
1158 | intel_pstate_hwp_set(); | |
1159 | ||
93f0822d DB |
1160 | return 0; |
1161 | } | |
1162 | ||
1163 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1164 | { | |
be49e346 | 1165 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1166 | |
285cb990 | 1167 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1168 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1169 | return -EINVAL; |
1170 | ||
1171 | return 0; | |
1172 | } | |
1173 | ||
bb18008f | 1174 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1175 | { |
bb18008f DB |
1176 | int cpu_num = policy->cpu; |
1177 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1178 | |
f16255eb | 1179 | pr_debug("intel_pstate: CPU %d exiting\n", cpu_num); |
bb18008f | 1180 | |
c2294a2f | 1181 | del_timer_sync(&all_cpu_data[cpu_num]->timer); |
2f86dc4c DB |
1182 | if (hwp_active) |
1183 | return; | |
1184 | ||
6c1e4591 | 1185 | intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate, false); |
93f0822d DB |
1186 | } |
1187 | ||
2760984f | 1188 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1189 | { |
93f0822d | 1190 | struct cpudata *cpu; |
52e0a509 | 1191 | int rc; |
93f0822d DB |
1192 | |
1193 | rc = intel_pstate_init_cpu(policy->cpu); | |
1194 | if (rc) | |
1195 | return rc; | |
1196 | ||
1197 | cpu = all_cpu_data[policy->cpu]; | |
1198 | ||
51443fbf | 1199 | if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) |
93f0822d DB |
1200 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1201 | else | |
1202 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1203 | ||
b27580b0 DB |
1204 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1205 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1206 | |
1207 | /* cpuinfo and default policy values */ | |
b27580b0 DB |
1208 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1209 | policy->cpuinfo.max_freq = | |
1210 | cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1211 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1212 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1213 | ||
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | static struct cpufreq_driver intel_pstate_driver = { | |
1218 | .flags = CPUFREQ_CONST_LOOPS, | |
1219 | .verify = intel_pstate_verify_policy, | |
1220 | .setpolicy = intel_pstate_set_policy, | |
1221 | .get = intel_pstate_get, | |
1222 | .init = intel_pstate_cpu_init, | |
bb18008f | 1223 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1224 | .name = "intel_pstate", |
93f0822d DB |
1225 | }; |
1226 | ||
6be26498 | 1227 | static int __initdata no_load; |
2f86dc4c | 1228 | static int __initdata no_hwp; |
d64c3b0b | 1229 | static int __initdata hwp_only; |
aa4ea34d | 1230 | static unsigned int force_load; |
6be26498 | 1231 | |
b563b4e3 DB |
1232 | static int intel_pstate_msrs_not_valid(void) |
1233 | { | |
016c8150 | 1234 | if (!pstate_funcs.get_max() || |
c410833a SK |
1235 | !pstate_funcs.get_min() || |
1236 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1237 | return -ENODEV; |
1238 | ||
b563b4e3 DB |
1239 | return 0; |
1240 | } | |
016c8150 | 1241 | |
e0a261a2 | 1242 | static void copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1243 | { |
1244 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
1245 | pid_params.p_gain_pct = policy->p_gain_pct; | |
1246 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1247 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1248 | pid_params.deadband = policy->deadband; | |
1249 | pid_params.setpoint = policy->setpoint; | |
1250 | } | |
1251 | ||
e0a261a2 | 1252 | static void copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1253 | { |
1254 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 1255 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
1256 | pstate_funcs.get_min = funcs->get_min; |
1257 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1258 | pstate_funcs.get_scaling = funcs->get_scaling; |
016c8150 | 1259 | pstate_funcs.set = funcs->set; |
007bea09 | 1260 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
1261 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
1262 | ||
016c8150 DB |
1263 | } |
1264 | ||
fbbcdc07 | 1265 | #if IS_ENABLED(CONFIG_ACPI) |
6ee11e41 | 1266 | #include <acpi/processor.h> |
fbbcdc07 AH |
1267 | |
1268 | static bool intel_pstate_no_acpi_pss(void) | |
1269 | { | |
1270 | int i; | |
1271 | ||
1272 | for_each_possible_cpu(i) { | |
1273 | acpi_status status; | |
1274 | union acpi_object *pss; | |
1275 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1276 | struct acpi_processor *pr = per_cpu(processors, i); | |
1277 | ||
1278 | if (!pr) | |
1279 | continue; | |
1280 | ||
1281 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1282 | if (ACPI_FAILURE(status)) | |
1283 | continue; | |
1284 | ||
1285 | pss = buffer.pointer; | |
1286 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1287 | kfree(pss); | |
1288 | return false; | |
1289 | } | |
1290 | ||
1291 | kfree(pss); | |
1292 | } | |
1293 | ||
1294 | return true; | |
1295 | } | |
1296 | ||
966916ea | 1297 | static bool intel_pstate_has_acpi_ppc(void) |
1298 | { | |
1299 | int i; | |
1300 | ||
1301 | for_each_possible_cpu(i) { | |
1302 | struct acpi_processor *pr = per_cpu(processors, i); | |
1303 | ||
1304 | if (!pr) | |
1305 | continue; | |
1306 | if (acpi_has_method(pr->handle, "_PPC")) | |
1307 | return true; | |
1308 | } | |
1309 | return false; | |
1310 | } | |
1311 | ||
1312 | enum { | |
1313 | PSS, | |
1314 | PPC, | |
1315 | }; | |
1316 | ||
fbbcdc07 AH |
1317 | struct hw_vendor_info { |
1318 | u16 valid; | |
1319 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1320 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1321 | int oem_pwr_table; |
fbbcdc07 AH |
1322 | }; |
1323 | ||
1324 | /* Hardware vendor-specific info that has its own power management modes */ | |
1325 | static struct hw_vendor_info vendor_info[] = { | |
966916ea | 1326 | {1, "HP ", "ProLiant", PSS}, |
1327 | {1, "ORACLE", "X4-2 ", PPC}, | |
1328 | {1, "ORACLE", "X4-2L ", PPC}, | |
1329 | {1, "ORACLE", "X4-2B ", PPC}, | |
1330 | {1, "ORACLE", "X3-2 ", PPC}, | |
1331 | {1, "ORACLE", "X3-2L ", PPC}, | |
1332 | {1, "ORACLE", "X3-2B ", PPC}, | |
1333 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1334 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1335 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1336 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
1337 | {1, "ORACLE", "X4170 M3", PPC}, |
1338 | {1, "ORACLE", "X4275 M3", PPC}, | |
1339 | {1, "ORACLE", "X6-2 ", PPC}, | |
1340 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
1341 | {0, "", ""}, |
1342 | }; | |
1343 | ||
1344 | static bool intel_pstate_platform_pwr_mgmt_exists(void) | |
1345 | { | |
1346 | struct acpi_table_header hdr; | |
1347 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1348 | const struct x86_cpu_id *id; |
1349 | u64 misc_pwr; | |
1350 | ||
1351 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1352 | if (id) { | |
1353 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1354 | if ( misc_pwr & (1 << 8)) | |
1355 | return true; | |
1356 | } | |
fbbcdc07 | 1357 | |
c410833a SK |
1358 | if (acpi_disabled || |
1359 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1360 | return false; |
1361 | ||
1362 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1363 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1364 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1365 | ACPI_OEM_TABLE_ID_SIZE)) | |
1366 | switch (v_info->oem_pwr_table) { | |
1367 | case PSS: | |
1368 | return intel_pstate_no_acpi_pss(); | |
1369 | case PPC: | |
aa4ea34d EZ |
1370 | return intel_pstate_has_acpi_ppc() && |
1371 | (!force_load); | |
966916ea | 1372 | } |
fbbcdc07 AH |
1373 | } |
1374 | ||
1375 | return false; | |
1376 | } | |
1377 | #else /* CONFIG_ACPI not enabled */ | |
1378 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1379 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1380 | #endif /* CONFIG_ACPI */ |
1381 | ||
93f0822d DB |
1382 | static int __init intel_pstate_init(void) |
1383 | { | |
907cc908 | 1384 | int cpu, rc = 0; |
93f0822d | 1385 | const struct x86_cpu_id *id; |
64df1fdf | 1386 | struct cpu_defaults *cpu_def; |
93f0822d | 1387 | |
6be26498 DB |
1388 | if (no_load) |
1389 | return -ENODEV; | |
1390 | ||
93f0822d DB |
1391 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1392 | if (!id) | |
1393 | return -ENODEV; | |
1394 | ||
fbbcdc07 AH |
1395 | /* |
1396 | * The Intel pstate driver will be ignored if the platform | |
1397 | * firmware has its own power management modes. | |
1398 | */ | |
1399 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1400 | return -ENODEV; | |
1401 | ||
64df1fdf | 1402 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1403 | |
64df1fdf BP |
1404 | copy_pid_params(&cpu_def->pid_policy); |
1405 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1406 | |
b563b4e3 DB |
1407 | if (intel_pstate_msrs_not_valid()) |
1408 | return -ENODEV; | |
1409 | ||
93f0822d DB |
1410 | pr_info("Intel P-state driver initializing.\n"); |
1411 | ||
b57ffac5 | 1412 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1413 | if (!all_cpu_data) |
1414 | return -ENOMEM; | |
93f0822d | 1415 | |
539342f6 PB |
1416 | if (static_cpu_has_safe(X86_FEATURE_HWP) && !no_hwp) { |
1417 | pr_info("intel_pstate: HWP enabled\n"); | |
ba88d433 | 1418 | hwp_active++; |
539342f6 | 1419 | } |
2f86dc4c | 1420 | |
d64c3b0b KCA |
1421 | if (!hwp_active && hwp_only) |
1422 | goto out; | |
1423 | ||
93f0822d DB |
1424 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1425 | if (rc) | |
1426 | goto out; | |
1427 | ||
1428 | intel_pstate_debug_expose_params(); | |
1429 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1430 | |
93f0822d DB |
1431 | return rc; |
1432 | out: | |
907cc908 DB |
1433 | get_online_cpus(); |
1434 | for_each_online_cpu(cpu) { | |
1435 | if (all_cpu_data[cpu]) { | |
1436 | del_timer_sync(&all_cpu_data[cpu]->timer); | |
1437 | kfree(all_cpu_data[cpu]); | |
1438 | } | |
1439 | } | |
1440 | ||
1441 | put_online_cpus(); | |
1442 | vfree(all_cpu_data); | |
93f0822d DB |
1443 | return -ENODEV; |
1444 | } | |
1445 | device_initcall(intel_pstate_init); | |
1446 | ||
6be26498 DB |
1447 | static int __init intel_pstate_setup(char *str) |
1448 | { | |
1449 | if (!str) | |
1450 | return -EINVAL; | |
1451 | ||
1452 | if (!strcmp(str, "disable")) | |
1453 | no_load = 1; | |
539342f6 PB |
1454 | if (!strcmp(str, "no_hwp")) { |
1455 | pr_info("intel_pstate: HWP disabled\n"); | |
2f86dc4c | 1456 | no_hwp = 1; |
539342f6 | 1457 | } |
aa4ea34d EZ |
1458 | if (!strcmp(str, "force")) |
1459 | force_load = 1; | |
d64c3b0b KCA |
1460 | if (!strcmp(str, "hwp_only")) |
1461 | hwp_only = 1; | |
6be26498 DB |
1462 | return 0; |
1463 | } | |
1464 | early_param("intel_pstate", intel_pstate_setup); | |
1465 | ||
93f0822d DB |
1466 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1467 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1468 | MODULE_LICENSE("GPL"); |