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93f0822d | 1 | /* |
d1b68485 | 2 | * intel_pstate.c: Native P state management for Intel processors |
93f0822d DB |
3 | * |
4 | * (C) Copyright 2012 Intel Corporation | |
5 | * Author: Dirk Brandewie <dirk.j.brandewie@intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; version 2 | |
10 | * of the License. | |
11 | */ | |
12 | ||
4836df17 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
93f0822d DB |
15 | #include <linux/kernel.h> |
16 | #include <linux/kernel_stat.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/ktime.h> | |
19 | #include <linux/hrtimer.h> | |
20 | #include <linux/tick.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/cpu.h> | |
25 | #include <linux/cpufreq.h> | |
26 | #include <linux/sysfs.h> | |
27 | #include <linux/types.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/debugfs.h> | |
fbbcdc07 | 30 | #include <linux/acpi.h> |
d6472302 | 31 | #include <linux/vmalloc.h> |
93f0822d DB |
32 | #include <trace/events/power.h> |
33 | ||
34 | #include <asm/div64.h> | |
35 | #include <asm/msr.h> | |
36 | #include <asm/cpu_device_id.h> | |
64df1fdf | 37 | #include <asm/cpufeature.h> |
5b20c944 | 38 | #include <asm/intel-family.h> |
93f0822d | 39 | |
938d21a2 PL |
40 | #define ATOM_RATIOS 0x66a |
41 | #define ATOM_VIDS 0x66b | |
42 | #define ATOM_TURBO_RATIOS 0x66c | |
43 | #define ATOM_TURBO_VIDS 0x66d | |
61d8d2ab | 44 | |
9522a2ff SP |
45 | #ifdef CONFIG_ACPI |
46 | #include <acpi/processor.h> | |
47 | #endif | |
48 | ||
f0fe3cd7 | 49 | #define FRAC_BITS 8 |
93f0822d DB |
50 | #define int_tofp(X) ((int64_t)(X) << FRAC_BITS) |
51 | #define fp_toint(X) ((X) >> FRAC_BITS) | |
f0fe3cd7 | 52 | |
a1c9787d RW |
53 | #define EXT_BITS 6 |
54 | #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS) | |
55 | ||
93f0822d DB |
56 | static inline int32_t mul_fp(int32_t x, int32_t y) |
57 | { | |
58 | return ((int64_t)x * (int64_t)y) >> FRAC_BITS; | |
59 | } | |
60 | ||
7180dddf | 61 | static inline int32_t div_fp(s64 x, s64 y) |
93f0822d | 62 | { |
7180dddf | 63 | return div64_s64((int64_t)x << FRAC_BITS, y); |
93f0822d DB |
64 | } |
65 | ||
d022a65e DB |
66 | static inline int ceiling_fp(int32_t x) |
67 | { | |
68 | int mask, ret; | |
69 | ||
70 | ret = fp_toint(x); | |
71 | mask = (1 << FRAC_BITS) - 1; | |
72 | if (x & mask) | |
73 | ret += 1; | |
74 | return ret; | |
75 | } | |
76 | ||
a1c9787d RW |
77 | static inline u64 mul_ext_fp(u64 x, u64 y) |
78 | { | |
79 | return (x * y) >> EXT_FRAC_BITS; | |
80 | } | |
81 | ||
82 | static inline u64 div_ext_fp(u64 x, u64 y) | |
83 | { | |
84 | return div64_u64(x << EXT_FRAC_BITS, y); | |
85 | } | |
86 | ||
13ad7701 SP |
87 | /** |
88 | * struct sample - Store performance sample | |
a1c9787d | 89 | * @core_avg_perf: Ratio of APERF/MPERF which is the actual average |
13ad7701 SP |
90 | * performance during last sample period |
91 | * @busy_scaled: Scaled busy value which is used to calculate next | |
a1c9787d | 92 | * P state. This can be different than core_avg_perf |
13ad7701 SP |
93 | * to account for cpu idle period |
94 | * @aperf: Difference of actual performance frequency clock count | |
95 | * read from APERF MSR between last and current sample | |
96 | * @mperf: Difference of maximum performance frequency clock count | |
97 | * read from MPERF MSR between last and current sample | |
98 | * @tsc: Difference of time stamp counter between last and | |
99 | * current sample | |
13ad7701 SP |
100 | * @time: Current time from scheduler |
101 | * | |
102 | * This structure is used in the cpudata structure to store performance sample | |
103 | * data for choosing next P State. | |
104 | */ | |
93f0822d | 105 | struct sample { |
a1c9787d | 106 | int32_t core_avg_perf; |
157386b6 | 107 | int32_t busy_scaled; |
93f0822d DB |
108 | u64 aperf; |
109 | u64 mperf; | |
4055fad3 | 110 | u64 tsc; |
a4675fbc | 111 | u64 time; |
93f0822d DB |
112 | }; |
113 | ||
13ad7701 SP |
114 | /** |
115 | * struct pstate_data - Store P state data | |
116 | * @current_pstate: Current requested P state | |
117 | * @min_pstate: Min P state possible for this platform | |
118 | * @max_pstate: Max P state possible for this platform | |
119 | * @max_pstate_physical:This is physical Max P state for a processor | |
120 | * This can be higher than the max_pstate which can | |
121 | * be limited by platform thermal design power limits | |
122 | * @scaling: Scaling factor to convert frequency to cpufreq | |
123 | * frequency units | |
124 | * @turbo_pstate: Max Turbo P state possible for this platform | |
125 | * | |
126 | * Stores the per cpu model P state limits and current P state. | |
127 | */ | |
93f0822d DB |
128 | struct pstate_data { |
129 | int current_pstate; | |
130 | int min_pstate; | |
131 | int max_pstate; | |
3bcc6fa9 | 132 | int max_pstate_physical; |
b27580b0 | 133 | int scaling; |
93f0822d DB |
134 | int turbo_pstate; |
135 | }; | |
136 | ||
13ad7701 SP |
137 | /** |
138 | * struct vid_data - Stores voltage information data | |
139 | * @min: VID data for this platform corresponding to | |
140 | * the lowest P state | |
141 | * @max: VID data corresponding to the highest P State. | |
142 | * @turbo: VID data for turbo P state | |
143 | * @ratio: Ratio of (vid max - vid min) / | |
144 | * (max P state - Min P State) | |
145 | * | |
146 | * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling) | |
147 | * This data is used in Atom platforms, where in addition to target P state, | |
148 | * the voltage data needs to be specified to select next P State. | |
149 | */ | |
007bea09 | 150 | struct vid_data { |
21855ff5 DB |
151 | int min; |
152 | int max; | |
153 | int turbo; | |
007bea09 DB |
154 | int32_t ratio; |
155 | }; | |
156 | ||
13ad7701 SP |
157 | /** |
158 | * struct _pid - Stores PID data | |
159 | * @setpoint: Target set point for busyness or performance | |
160 | * @integral: Storage for accumulated error values | |
161 | * @p_gain: PID proportional gain | |
162 | * @i_gain: PID integral gain | |
163 | * @d_gain: PID derivative gain | |
164 | * @deadband: PID deadband | |
165 | * @last_err: Last error storage for integral part of PID calculation | |
166 | * | |
167 | * Stores PID coefficients and last error for PID controller. | |
168 | */ | |
93f0822d DB |
169 | struct _pid { |
170 | int setpoint; | |
171 | int32_t integral; | |
172 | int32_t p_gain; | |
173 | int32_t i_gain; | |
174 | int32_t d_gain; | |
175 | int deadband; | |
d253d2a5 | 176 | int32_t last_err; |
93f0822d DB |
177 | }; |
178 | ||
13ad7701 SP |
179 | /** |
180 | * struct cpudata - Per CPU instance data storage | |
181 | * @cpu: CPU number for this instance data | |
182 | * @update_util: CPUFreq utility callback information | |
4578ee7e | 183 | * @update_util_set: CPUFreq utility callback is set |
09c448d3 RW |
184 | * @iowait_boost: iowait-related boost fraction |
185 | * @last_update: Time of the last update. | |
13ad7701 SP |
186 | * @pstate: Stores P state limits for this CPU |
187 | * @vid: Stores VID limits for this CPU | |
188 | * @pid: Stores PID parameters for this CPU | |
189 | * @last_sample_time: Last Sample time | |
190 | * @prev_aperf: Last APERF value read from APERF MSR | |
191 | * @prev_mperf: Last MPERF value read from MPERF MSR | |
192 | * @prev_tsc: Last timestamp counter (TSC) value | |
193 | * @prev_cummulative_iowait: IO Wait time difference from last and | |
194 | * current sample | |
195 | * @sample: Storage for storing last Sample data | |
9522a2ff SP |
196 | * @acpi_perf_data: Stores ACPI perf information read from _PSS |
197 | * @valid_pss_table: Set to true for valid ACPI _PSS entries found | |
13ad7701 SP |
198 | * |
199 | * This structure stores per CPU instance data for all CPUs. | |
200 | */ | |
93f0822d DB |
201 | struct cpudata { |
202 | int cpu; | |
203 | ||
a4675fbc | 204 | struct update_util_data update_util; |
4578ee7e | 205 | bool update_util_set; |
93f0822d | 206 | |
93f0822d | 207 | struct pstate_data pstate; |
007bea09 | 208 | struct vid_data vid; |
93f0822d | 209 | struct _pid pid; |
93f0822d | 210 | |
09c448d3 | 211 | u64 last_update; |
a4675fbc | 212 | u64 last_sample_time; |
93f0822d DB |
213 | u64 prev_aperf; |
214 | u64 prev_mperf; | |
4055fad3 | 215 | u64 prev_tsc; |
63d1d656 | 216 | u64 prev_cummulative_iowait; |
d37e2b76 | 217 | struct sample sample; |
9522a2ff SP |
218 | #ifdef CONFIG_ACPI |
219 | struct acpi_processor_performance acpi_perf_data; | |
220 | bool valid_pss_table; | |
221 | #endif | |
09c448d3 | 222 | unsigned int iowait_boost; |
93f0822d DB |
223 | }; |
224 | ||
225 | static struct cpudata **all_cpu_data; | |
13ad7701 SP |
226 | |
227 | /** | |
228 | * struct pid_adjust_policy - Stores static PID configuration data | |
229 | * @sample_rate_ms: PID calculation sample rate in ms | |
230 | * @sample_rate_ns: Sample rate calculation in ns | |
231 | * @deadband: PID deadband | |
232 | * @setpoint: PID Setpoint | |
233 | * @p_gain_pct: PID proportional gain | |
234 | * @i_gain_pct: PID integral gain | |
235 | * @d_gain_pct: PID derivative gain | |
09c448d3 | 236 | * @boost_iowait: Whether or not to use iowait boosting. |
13ad7701 SP |
237 | * |
238 | * Stores per CPU model static PID configuration data. | |
239 | */ | |
93f0822d DB |
240 | struct pstate_adjust_policy { |
241 | int sample_rate_ms; | |
a4675fbc | 242 | s64 sample_rate_ns; |
93f0822d DB |
243 | int deadband; |
244 | int setpoint; | |
245 | int p_gain_pct; | |
246 | int d_gain_pct; | |
247 | int i_gain_pct; | |
09c448d3 | 248 | bool boost_iowait; |
93f0822d DB |
249 | }; |
250 | ||
13ad7701 SP |
251 | /** |
252 | * struct pstate_funcs - Per CPU model specific callbacks | |
253 | * @get_max: Callback to get maximum non turbo effective P state | |
254 | * @get_max_physical: Callback to get maximum non turbo physical P state | |
255 | * @get_min: Callback to get minimum P state | |
256 | * @get_turbo: Callback to get turbo P state | |
257 | * @get_scaling: Callback to get frequency scaling factor | |
258 | * @get_val: Callback to convert P state to actual MSR write value | |
259 | * @get_vid: Callback to get VID data for Atom platforms | |
260 | * @get_target_pstate: Callback to a function to calculate next P state to use | |
261 | * | |
262 | * Core and Atom CPU models have different way to get P State limits. This | |
263 | * structure is used to store those callbacks. | |
264 | */ | |
016c8150 DB |
265 | struct pstate_funcs { |
266 | int (*get_max)(void); | |
3bcc6fa9 | 267 | int (*get_max_physical)(void); |
016c8150 DB |
268 | int (*get_min)(void); |
269 | int (*get_turbo)(void); | |
b27580b0 | 270 | int (*get_scaling)(void); |
fdfdb2b1 | 271 | u64 (*get_val)(struct cpudata*, int pstate); |
007bea09 | 272 | void (*get_vid)(struct cpudata *); |
157386b6 | 273 | int32_t (*get_target_pstate)(struct cpudata *); |
93f0822d DB |
274 | }; |
275 | ||
13ad7701 SP |
276 | /** |
277 | * struct cpu_defaults- Per CPU model default config data | |
278 | * @pid_policy: PID config data | |
279 | * @funcs: Callback function data | |
280 | */ | |
016c8150 DB |
281 | struct cpu_defaults { |
282 | struct pstate_adjust_policy pid_policy; | |
283 | struct pstate_funcs funcs; | |
93f0822d DB |
284 | }; |
285 | ||
157386b6 | 286 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu); |
e70eed2b | 287 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu); |
157386b6 | 288 | |
4a7cb7a9 JZ |
289 | static struct pstate_adjust_policy pid_params __read_mostly; |
290 | static struct pstate_funcs pstate_funcs __read_mostly; | |
291 | static int hwp_active __read_mostly; | |
016c8150 | 292 | |
9522a2ff SP |
293 | #ifdef CONFIG_ACPI |
294 | static bool acpi_ppc; | |
295 | #endif | |
13ad7701 SP |
296 | |
297 | /** | |
298 | * struct perf_limits - Store user and policy limits | |
299 | * @no_turbo: User requested turbo state from intel_pstate sysfs | |
300 | * @turbo_disabled: Platform turbo status either from msr | |
301 | * MSR_IA32_MISC_ENABLE or when maximum available pstate | |
302 | * matches the maximum turbo pstate | |
303 | * @max_perf_pct: Effective maximum performance limit in percentage, this | |
304 | * is minimum of either limits enforced by cpufreq policy | |
305 | * or limits from user set limits via intel_pstate sysfs | |
306 | * @min_perf_pct: Effective minimum performance limit in percentage, this | |
307 | * is maximum of either limits enforced by cpufreq policy | |
308 | * or limits from user set limits via intel_pstate sysfs | |
309 | * @max_perf: This is a scaled value between 0 to 255 for max_perf_pct | |
310 | * This value is used to limit max pstate | |
311 | * @min_perf: This is a scaled value between 0 to 255 for min_perf_pct | |
312 | * This value is used to limit min pstate | |
313 | * @max_policy_pct: The maximum performance in percentage enforced by | |
314 | * cpufreq setpolicy interface | |
315 | * @max_sysfs_pct: The maximum performance in percentage enforced by | |
316 | * intel pstate sysfs interface | |
317 | * @min_policy_pct: The minimum performance in percentage enforced by | |
318 | * cpufreq setpolicy interface | |
319 | * @min_sysfs_pct: The minimum performance in percentage enforced by | |
320 | * intel pstate sysfs interface | |
321 | * | |
322 | * Storage for user and policy defined limits. | |
323 | */ | |
93f0822d DB |
324 | struct perf_limits { |
325 | int no_turbo; | |
dd5fbf70 | 326 | int turbo_disabled; |
93f0822d DB |
327 | int max_perf_pct; |
328 | int min_perf_pct; | |
329 | int32_t max_perf; | |
330 | int32_t min_perf; | |
d8f469e9 DB |
331 | int max_policy_pct; |
332 | int max_sysfs_pct; | |
a0475992 KCA |
333 | int min_policy_pct; |
334 | int min_sysfs_pct; | |
93f0822d DB |
335 | }; |
336 | ||
51443fbf PB |
337 | static struct perf_limits performance_limits = { |
338 | .no_turbo = 0, | |
339 | .turbo_disabled = 0, | |
340 | .max_perf_pct = 100, | |
341 | .max_perf = int_tofp(1), | |
342 | .min_perf_pct = 100, | |
343 | .min_perf = int_tofp(1), | |
344 | .max_policy_pct = 100, | |
345 | .max_sysfs_pct = 100, | |
346 | .min_policy_pct = 0, | |
347 | .min_sysfs_pct = 0, | |
348 | }; | |
349 | ||
350 | static struct perf_limits powersave_limits = { | |
93f0822d | 351 | .no_turbo = 0, |
4521e1a0 | 352 | .turbo_disabled = 0, |
93f0822d DB |
353 | .max_perf_pct = 100, |
354 | .max_perf = int_tofp(1), | |
355 | .min_perf_pct = 0, | |
356 | .min_perf = 0, | |
d8f469e9 DB |
357 | .max_policy_pct = 100, |
358 | .max_sysfs_pct = 100, | |
a0475992 KCA |
359 | .min_policy_pct = 0, |
360 | .min_sysfs_pct = 0, | |
93f0822d DB |
361 | }; |
362 | ||
51443fbf PB |
363 | #ifdef CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE |
364 | static struct perf_limits *limits = &performance_limits; | |
365 | #else | |
366 | static struct perf_limits *limits = &powersave_limits; | |
367 | #endif | |
368 | ||
9522a2ff | 369 | #ifdef CONFIG_ACPI |
2b3ec765 SP |
370 | |
371 | static bool intel_pstate_get_ppc_enable_status(void) | |
372 | { | |
373 | if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER || | |
374 | acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER) | |
375 | return true; | |
376 | ||
377 | return acpi_ppc; | |
378 | } | |
379 | ||
9522a2ff SP |
380 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) |
381 | { | |
382 | struct cpudata *cpu; | |
9522a2ff SP |
383 | int ret; |
384 | int i; | |
385 | ||
e59a8f7f SP |
386 | if (hwp_active) |
387 | return; | |
388 | ||
2b3ec765 | 389 | if (!intel_pstate_get_ppc_enable_status()) |
9522a2ff SP |
390 | return; |
391 | ||
392 | cpu = all_cpu_data[policy->cpu]; | |
393 | ||
394 | ret = acpi_processor_register_performance(&cpu->acpi_perf_data, | |
395 | policy->cpu); | |
396 | if (ret) | |
397 | return; | |
398 | ||
399 | /* | |
400 | * Check if the control value in _PSS is for PERF_CTL MSR, which should | |
401 | * guarantee that the states returned by it map to the states in our | |
402 | * list directly. | |
403 | */ | |
404 | if (cpu->acpi_perf_data.control_register.space_id != | |
405 | ACPI_ADR_SPACE_FIXED_HARDWARE) | |
406 | goto err; | |
407 | ||
408 | /* | |
409 | * If there is only one entry _PSS, simply ignore _PSS and continue as | |
410 | * usual without taking _PSS into account | |
411 | */ | |
412 | if (cpu->acpi_perf_data.state_count < 2) | |
413 | goto err; | |
414 | ||
415 | pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu); | |
416 | for (i = 0; i < cpu->acpi_perf_data.state_count; i++) { | |
417 | pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n", | |
418 | (i == cpu->acpi_perf_data.state ? '*' : ' '), i, | |
419 | (u32) cpu->acpi_perf_data.states[i].core_frequency, | |
420 | (u32) cpu->acpi_perf_data.states[i].power, | |
421 | (u32) cpu->acpi_perf_data.states[i].control); | |
422 | } | |
423 | ||
424 | /* | |
425 | * The _PSS table doesn't contain whole turbo frequency range. | |
426 | * This just contains +1 MHZ above the max non turbo frequency, | |
427 | * with control value corresponding to max turbo ratio. But | |
428 | * when cpufreq set policy is called, it will call with this | |
429 | * max frequency, which will cause a reduced performance as | |
430 | * this driver uses real max turbo frequency as the max | |
431 | * frequency. So correct this frequency in _PSS table to | |
b00345d1 | 432 | * correct max turbo frequency based on the turbo state. |
9522a2ff SP |
433 | * Also need to convert to MHz as _PSS freq is in MHz. |
434 | */ | |
b00345d1 | 435 | if (!limits->turbo_disabled) |
9522a2ff SP |
436 | cpu->acpi_perf_data.states[0].core_frequency = |
437 | policy->cpuinfo.max_freq / 1000; | |
438 | cpu->valid_pss_table = true; | |
6cacd115 | 439 | pr_debug("_PPC limits will be enforced\n"); |
9522a2ff SP |
440 | |
441 | return; | |
442 | ||
443 | err: | |
444 | cpu->valid_pss_table = false; | |
445 | acpi_processor_unregister_performance(policy->cpu); | |
446 | } | |
447 | ||
448 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
449 | { | |
450 | struct cpudata *cpu; | |
451 | ||
452 | cpu = all_cpu_data[policy->cpu]; | |
453 | if (!cpu->valid_pss_table) | |
454 | return; | |
455 | ||
456 | acpi_processor_unregister_performance(policy->cpu); | |
457 | } | |
458 | ||
459 | #else | |
460 | static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy) | |
461 | { | |
462 | } | |
463 | ||
464 | static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy) | |
465 | { | |
466 | } | |
467 | #endif | |
468 | ||
93f0822d | 469 | static inline void pid_reset(struct _pid *pid, int setpoint, int busy, |
c410833a | 470 | int deadband, int integral) { |
b54a0dfd PL |
471 | pid->setpoint = int_tofp(setpoint); |
472 | pid->deadband = int_tofp(deadband); | |
93f0822d | 473 | pid->integral = int_tofp(integral); |
d98d099b | 474 | pid->last_err = int_tofp(setpoint) - int_tofp(busy); |
93f0822d DB |
475 | } |
476 | ||
477 | static inline void pid_p_gain_set(struct _pid *pid, int percent) | |
478 | { | |
22590efb | 479 | pid->p_gain = div_fp(percent, 100); |
93f0822d DB |
480 | } |
481 | ||
482 | static inline void pid_i_gain_set(struct _pid *pid, int percent) | |
483 | { | |
22590efb | 484 | pid->i_gain = div_fp(percent, 100); |
93f0822d DB |
485 | } |
486 | ||
487 | static inline void pid_d_gain_set(struct _pid *pid, int percent) | |
488 | { | |
22590efb | 489 | pid->d_gain = div_fp(percent, 100); |
93f0822d DB |
490 | } |
491 | ||
d253d2a5 | 492 | static signed int pid_calc(struct _pid *pid, int32_t busy) |
93f0822d | 493 | { |
d253d2a5 | 494 | signed int result; |
93f0822d DB |
495 | int32_t pterm, dterm, fp_error; |
496 | int32_t integral_limit; | |
497 | ||
b54a0dfd | 498 | fp_error = pid->setpoint - busy; |
93f0822d | 499 | |
b54a0dfd | 500 | if (abs(fp_error) <= pid->deadband) |
93f0822d DB |
501 | return 0; |
502 | ||
503 | pterm = mul_fp(pid->p_gain, fp_error); | |
504 | ||
505 | pid->integral += fp_error; | |
506 | ||
e0d4c8f8 KCA |
507 | /* |
508 | * We limit the integral here so that it will never | |
509 | * get higher than 30. This prevents it from becoming | |
510 | * too large an input over long periods of time and allows | |
511 | * it to get factored out sooner. | |
512 | * | |
513 | * The value of 30 was chosen through experimentation. | |
514 | */ | |
93f0822d DB |
515 | integral_limit = int_tofp(30); |
516 | if (pid->integral > integral_limit) | |
517 | pid->integral = integral_limit; | |
518 | if (pid->integral < -integral_limit) | |
519 | pid->integral = -integral_limit; | |
520 | ||
d253d2a5 BS |
521 | dterm = mul_fp(pid->d_gain, fp_error - pid->last_err); |
522 | pid->last_err = fp_error; | |
93f0822d DB |
523 | |
524 | result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm; | |
51d211e9 | 525 | result = result + (1 << (FRAC_BITS-1)); |
93f0822d DB |
526 | return (signed int)fp_toint(result); |
527 | } | |
528 | ||
529 | static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu) | |
530 | { | |
016c8150 DB |
531 | pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct); |
532 | pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct); | |
533 | pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct); | |
93f0822d | 534 | |
2d8d1f18 | 535 | pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0); |
93f0822d DB |
536 | } |
537 | ||
93f0822d DB |
538 | static inline void intel_pstate_reset_all_pid(void) |
539 | { | |
540 | unsigned int cpu; | |
845c1cbe | 541 | |
93f0822d DB |
542 | for_each_online_cpu(cpu) { |
543 | if (all_cpu_data[cpu]) | |
544 | intel_pstate_busy_pid_reset(all_cpu_data[cpu]); | |
545 | } | |
546 | } | |
547 | ||
4521e1a0 GM |
548 | static inline void update_turbo_state(void) |
549 | { | |
550 | u64 misc_en; | |
551 | struct cpudata *cpu; | |
552 | ||
553 | cpu = all_cpu_data[0]; | |
554 | rdmsrl(MSR_IA32_MISC_ENABLE, misc_en); | |
51443fbf | 555 | limits->turbo_disabled = |
4521e1a0 GM |
556 | (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE || |
557 | cpu->pstate.max_pstate == cpu->pstate.turbo_pstate); | |
558 | } | |
559 | ||
41cfd64c | 560 | static void intel_pstate_hwp_set(const struct cpumask *cpumask) |
2f86dc4c | 561 | { |
74da56ce KCA |
562 | int min, hw_min, max, hw_max, cpu, range, adj_range; |
563 | u64 value, cap; | |
564 | ||
41cfd64c | 565 | for_each_cpu(cpu, cpumask) { |
f9f4872d SP |
566 | rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap); |
567 | hw_min = HWP_LOWEST_PERF(cap); | |
568 | hw_max = HWP_HIGHEST_PERF(cap); | |
569 | range = hw_max - hw_min; | |
570 | ||
2f86dc4c | 571 | rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value); |
51443fbf | 572 | adj_range = limits->min_perf_pct * range / 100; |
74da56ce | 573 | min = hw_min + adj_range; |
2f86dc4c DB |
574 | value &= ~HWP_MIN_PERF(~0L); |
575 | value |= HWP_MIN_PERF(min); | |
576 | ||
51443fbf | 577 | adj_range = limits->max_perf_pct * range / 100; |
74da56ce | 578 | max = hw_min + adj_range; |
51443fbf | 579 | if (limits->no_turbo) { |
74da56ce KCA |
580 | hw_max = HWP_GUARANTEED_PERF(cap); |
581 | if (hw_max < max) | |
582 | max = hw_max; | |
2f86dc4c DB |
583 | } |
584 | ||
585 | value &= ~HWP_MAX_PERF(~0L); | |
586 | value |= HWP_MAX_PERF(max); | |
587 | wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value); | |
588 | } | |
41cfd64c | 589 | } |
2f86dc4c | 590 | |
ba41e1bc RW |
591 | static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy) |
592 | { | |
593 | if (hwp_active) | |
594 | intel_pstate_hwp_set(policy->cpus); | |
595 | ||
596 | return 0; | |
597 | } | |
598 | ||
41cfd64c VK |
599 | static void intel_pstate_hwp_set_online_cpus(void) |
600 | { | |
601 | get_online_cpus(); | |
602 | intel_pstate_hwp_set(cpu_online_mask); | |
2f86dc4c DB |
603 | put_online_cpus(); |
604 | } | |
605 | ||
93f0822d DB |
606 | /************************** debugfs begin ************************/ |
607 | static int pid_param_set(void *data, u64 val) | |
608 | { | |
609 | *(u32 *)data = val; | |
610 | intel_pstate_reset_all_pid(); | |
611 | return 0; | |
612 | } | |
845c1cbe | 613 | |
93f0822d DB |
614 | static int pid_param_get(void *data, u64 *val) |
615 | { | |
616 | *val = *(u32 *)data; | |
617 | return 0; | |
618 | } | |
2d8d1f18 | 619 | DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n"); |
93f0822d DB |
620 | |
621 | struct pid_param { | |
622 | char *name; | |
623 | void *value; | |
624 | }; | |
625 | ||
626 | static struct pid_param pid_files[] = { | |
016c8150 DB |
627 | {"sample_rate_ms", &pid_params.sample_rate_ms}, |
628 | {"d_gain_pct", &pid_params.d_gain_pct}, | |
629 | {"i_gain_pct", &pid_params.i_gain_pct}, | |
630 | {"deadband", &pid_params.deadband}, | |
631 | {"setpoint", &pid_params.setpoint}, | |
632 | {"p_gain_pct", &pid_params.p_gain_pct}, | |
93f0822d DB |
633 | {NULL, NULL} |
634 | }; | |
635 | ||
317dd50e | 636 | static void __init intel_pstate_debug_expose_params(void) |
93f0822d | 637 | { |
317dd50e | 638 | struct dentry *debugfs_parent; |
93f0822d DB |
639 | int i = 0; |
640 | ||
2f86dc4c DB |
641 | if (hwp_active) |
642 | return; | |
93f0822d DB |
643 | debugfs_parent = debugfs_create_dir("pstate_snb", NULL); |
644 | if (IS_ERR_OR_NULL(debugfs_parent)) | |
645 | return; | |
646 | while (pid_files[i].name) { | |
647 | debugfs_create_file(pid_files[i].name, 0660, | |
c410833a SK |
648 | debugfs_parent, pid_files[i].value, |
649 | &fops_pid_param); | |
93f0822d DB |
650 | i++; |
651 | } | |
652 | } | |
653 | ||
654 | /************************** debugfs end ************************/ | |
655 | ||
656 | /************************** sysfs begin ************************/ | |
657 | #define show_one(file_name, object) \ | |
658 | static ssize_t show_##file_name \ | |
659 | (struct kobject *kobj, struct attribute *attr, char *buf) \ | |
660 | { \ | |
51443fbf | 661 | return sprintf(buf, "%u\n", limits->object); \ |
93f0822d DB |
662 | } |
663 | ||
d01b1f48 KCA |
664 | static ssize_t show_turbo_pct(struct kobject *kobj, |
665 | struct attribute *attr, char *buf) | |
666 | { | |
667 | struct cpudata *cpu; | |
668 | int total, no_turbo, turbo_pct; | |
669 | uint32_t turbo_fp; | |
670 | ||
671 | cpu = all_cpu_data[0]; | |
672 | ||
673 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
674 | no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1; | |
22590efb | 675 | turbo_fp = div_fp(no_turbo, total); |
d01b1f48 KCA |
676 | turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100))); |
677 | return sprintf(buf, "%u\n", turbo_pct); | |
678 | } | |
679 | ||
0522424e KCA |
680 | static ssize_t show_num_pstates(struct kobject *kobj, |
681 | struct attribute *attr, char *buf) | |
682 | { | |
683 | struct cpudata *cpu; | |
684 | int total; | |
685 | ||
686 | cpu = all_cpu_data[0]; | |
687 | total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1; | |
688 | return sprintf(buf, "%u\n", total); | |
689 | } | |
690 | ||
4521e1a0 GM |
691 | static ssize_t show_no_turbo(struct kobject *kobj, |
692 | struct attribute *attr, char *buf) | |
693 | { | |
694 | ssize_t ret; | |
695 | ||
696 | update_turbo_state(); | |
51443fbf PB |
697 | if (limits->turbo_disabled) |
698 | ret = sprintf(buf, "%u\n", limits->turbo_disabled); | |
4521e1a0 | 699 | else |
51443fbf | 700 | ret = sprintf(buf, "%u\n", limits->no_turbo); |
4521e1a0 GM |
701 | |
702 | return ret; | |
703 | } | |
704 | ||
93f0822d | 705 | static ssize_t store_no_turbo(struct kobject *a, struct attribute *b, |
c410833a | 706 | const char *buf, size_t count) |
93f0822d DB |
707 | { |
708 | unsigned int input; | |
709 | int ret; | |
845c1cbe | 710 | |
93f0822d DB |
711 | ret = sscanf(buf, "%u", &input); |
712 | if (ret != 1) | |
713 | return -EINVAL; | |
4521e1a0 GM |
714 | |
715 | update_turbo_state(); | |
51443fbf | 716 | if (limits->turbo_disabled) { |
4836df17 | 717 | pr_warn("Turbo disabled by BIOS or unavailable on processor\n"); |
4521e1a0 | 718 | return -EPERM; |
dd5fbf70 | 719 | } |
2f86dc4c | 720 | |
51443fbf | 721 | limits->no_turbo = clamp_t(int, input, 0, 1); |
4521e1a0 | 722 | |
2f86dc4c | 723 | if (hwp_active) |
41cfd64c | 724 | intel_pstate_hwp_set_online_cpus(); |
2f86dc4c | 725 | |
93f0822d DB |
726 | return count; |
727 | } | |
728 | ||
729 | static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 730 | const char *buf, size_t count) |
93f0822d DB |
731 | { |
732 | unsigned int input; | |
733 | int ret; | |
845c1cbe | 734 | |
93f0822d DB |
735 | ret = sscanf(buf, "%u", &input); |
736 | if (ret != 1) | |
737 | return -EINVAL; | |
738 | ||
51443fbf PB |
739 | limits->max_sysfs_pct = clamp_t(int, input, 0 , 100); |
740 | limits->max_perf_pct = min(limits->max_policy_pct, | |
741 | limits->max_sysfs_pct); | |
742 | limits->max_perf_pct = max(limits->min_policy_pct, | |
743 | limits->max_perf_pct); | |
744 | limits->max_perf_pct = max(limits->min_perf_pct, | |
745 | limits->max_perf_pct); | |
22590efb | 746 | limits->max_perf = div_fp(limits->max_perf_pct, 100); |
845c1cbe | 747 | |
2f86dc4c | 748 | if (hwp_active) |
41cfd64c | 749 | intel_pstate_hwp_set_online_cpus(); |
93f0822d DB |
750 | return count; |
751 | } | |
752 | ||
753 | static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b, | |
c410833a | 754 | const char *buf, size_t count) |
93f0822d DB |
755 | { |
756 | unsigned int input; | |
757 | int ret; | |
845c1cbe | 758 | |
93f0822d DB |
759 | ret = sscanf(buf, "%u", &input); |
760 | if (ret != 1) | |
761 | return -EINVAL; | |
a0475992 | 762 | |
51443fbf PB |
763 | limits->min_sysfs_pct = clamp_t(int, input, 0 , 100); |
764 | limits->min_perf_pct = max(limits->min_policy_pct, | |
765 | limits->min_sysfs_pct); | |
766 | limits->min_perf_pct = min(limits->max_policy_pct, | |
767 | limits->min_perf_pct); | |
768 | limits->min_perf_pct = min(limits->max_perf_pct, | |
769 | limits->min_perf_pct); | |
22590efb | 770 | limits->min_perf = div_fp(limits->min_perf_pct, 100); |
93f0822d | 771 | |
2f86dc4c | 772 | if (hwp_active) |
41cfd64c | 773 | intel_pstate_hwp_set_online_cpus(); |
93f0822d DB |
774 | return count; |
775 | } | |
776 | ||
93f0822d DB |
777 | show_one(max_perf_pct, max_perf_pct); |
778 | show_one(min_perf_pct, min_perf_pct); | |
779 | ||
780 | define_one_global_rw(no_turbo); | |
781 | define_one_global_rw(max_perf_pct); | |
782 | define_one_global_rw(min_perf_pct); | |
d01b1f48 | 783 | define_one_global_ro(turbo_pct); |
0522424e | 784 | define_one_global_ro(num_pstates); |
93f0822d DB |
785 | |
786 | static struct attribute *intel_pstate_attributes[] = { | |
787 | &no_turbo.attr, | |
788 | &max_perf_pct.attr, | |
789 | &min_perf_pct.attr, | |
d01b1f48 | 790 | &turbo_pct.attr, |
0522424e | 791 | &num_pstates.attr, |
93f0822d DB |
792 | NULL |
793 | }; | |
794 | ||
795 | static struct attribute_group intel_pstate_attr_group = { | |
796 | .attrs = intel_pstate_attributes, | |
797 | }; | |
93f0822d | 798 | |
317dd50e | 799 | static void __init intel_pstate_sysfs_expose_params(void) |
93f0822d | 800 | { |
317dd50e | 801 | struct kobject *intel_pstate_kobject; |
93f0822d DB |
802 | int rc; |
803 | ||
804 | intel_pstate_kobject = kobject_create_and_add("intel_pstate", | |
805 | &cpu_subsys.dev_root->kobj); | |
806 | BUG_ON(!intel_pstate_kobject); | |
2d8d1f18 | 807 | rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group); |
93f0822d DB |
808 | BUG_ON(rc); |
809 | } | |
93f0822d | 810 | /************************** sysfs end ************************/ |
2f86dc4c | 811 | |
ba88d433 | 812 | static void intel_pstate_hwp_enable(struct cpudata *cpudata) |
2f86dc4c | 813 | { |
f05c9665 | 814 | /* First disable HWP notification interrupt as we don't process them */ |
da7de91c SP |
815 | if (static_cpu_has(X86_FEATURE_HWP_NOTIFY)) |
816 | wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00); | |
f05c9665 | 817 | |
ba88d433 | 818 | wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1); |
2f86dc4c DB |
819 | } |
820 | ||
938d21a2 | 821 | static int atom_get_min_pstate(void) |
19e77c28 DB |
822 | { |
823 | u64 value; | |
845c1cbe | 824 | |
938d21a2 | 825 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 826 | return (value >> 8) & 0x7F; |
19e77c28 DB |
827 | } |
828 | ||
938d21a2 | 829 | static int atom_get_max_pstate(void) |
19e77c28 DB |
830 | { |
831 | u64 value; | |
845c1cbe | 832 | |
938d21a2 | 833 | rdmsrl(ATOM_RATIOS, value); |
c16ed060 | 834 | return (value >> 16) & 0x7F; |
19e77c28 | 835 | } |
93f0822d | 836 | |
938d21a2 | 837 | static int atom_get_turbo_pstate(void) |
61d8d2ab DB |
838 | { |
839 | u64 value; | |
845c1cbe | 840 | |
938d21a2 | 841 | rdmsrl(ATOM_TURBO_RATIOS, value); |
c16ed060 | 842 | return value & 0x7F; |
61d8d2ab DB |
843 | } |
844 | ||
fdfdb2b1 | 845 | static u64 atom_get_val(struct cpudata *cpudata, int pstate) |
007bea09 DB |
846 | { |
847 | u64 val; | |
848 | int32_t vid_fp; | |
849 | u32 vid; | |
850 | ||
144c8e17 | 851 | val = (u64)pstate << 8; |
51443fbf | 852 | if (limits->no_turbo && !limits->turbo_disabled) |
007bea09 DB |
853 | val |= (u64)1 << 32; |
854 | ||
855 | vid_fp = cpudata->vid.min + mul_fp( | |
856 | int_tofp(pstate - cpudata->pstate.min_pstate), | |
857 | cpudata->vid.ratio); | |
858 | ||
859 | vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max); | |
d022a65e | 860 | vid = ceiling_fp(vid_fp); |
007bea09 | 861 | |
21855ff5 DB |
862 | if (pstate > cpudata->pstate.max_pstate) |
863 | vid = cpudata->vid.turbo; | |
864 | ||
fdfdb2b1 | 865 | return val | vid; |
007bea09 DB |
866 | } |
867 | ||
1421df63 | 868 | static int silvermont_get_scaling(void) |
b27580b0 DB |
869 | { |
870 | u64 value; | |
871 | int i; | |
1421df63 PL |
872 | /* Defined in Table 35-6 from SDM (Sept 2015) */ |
873 | static int silvermont_freq_table[] = { | |
874 | 83300, 100000, 133300, 116700, 80000}; | |
b27580b0 DB |
875 | |
876 | rdmsrl(MSR_FSB_FREQ, value); | |
1421df63 PL |
877 | i = value & 0x7; |
878 | WARN_ON(i > 4); | |
b27580b0 | 879 | |
1421df63 PL |
880 | return silvermont_freq_table[i]; |
881 | } | |
b27580b0 | 882 | |
1421df63 PL |
883 | static int airmont_get_scaling(void) |
884 | { | |
885 | u64 value; | |
886 | int i; | |
887 | /* Defined in Table 35-10 from SDM (Sept 2015) */ | |
888 | static int airmont_freq_table[] = { | |
889 | 83300, 100000, 133300, 116700, 80000, | |
890 | 93300, 90000, 88900, 87500}; | |
891 | ||
892 | rdmsrl(MSR_FSB_FREQ, value); | |
893 | i = value & 0xF; | |
894 | WARN_ON(i > 8); | |
895 | ||
896 | return airmont_freq_table[i]; | |
b27580b0 DB |
897 | } |
898 | ||
938d21a2 | 899 | static void atom_get_vid(struct cpudata *cpudata) |
007bea09 DB |
900 | { |
901 | u64 value; | |
902 | ||
938d21a2 | 903 | rdmsrl(ATOM_VIDS, value); |
c16ed060 DB |
904 | cpudata->vid.min = int_tofp((value >> 8) & 0x7f); |
905 | cpudata->vid.max = int_tofp((value >> 16) & 0x7f); | |
007bea09 DB |
906 | cpudata->vid.ratio = div_fp( |
907 | cpudata->vid.max - cpudata->vid.min, | |
908 | int_tofp(cpudata->pstate.max_pstate - | |
909 | cpudata->pstate.min_pstate)); | |
21855ff5 | 910 | |
938d21a2 | 911 | rdmsrl(ATOM_TURBO_VIDS, value); |
21855ff5 | 912 | cpudata->vid.turbo = value & 0x7f; |
007bea09 DB |
913 | } |
914 | ||
016c8150 | 915 | static int core_get_min_pstate(void) |
93f0822d DB |
916 | { |
917 | u64 value; | |
845c1cbe | 918 | |
05e99c8c | 919 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
920 | return (value >> 40) & 0xFF; |
921 | } | |
922 | ||
3bcc6fa9 | 923 | static int core_get_max_pstate_physical(void) |
93f0822d DB |
924 | { |
925 | u64 value; | |
845c1cbe | 926 | |
05e99c8c | 927 | rdmsrl(MSR_PLATFORM_INFO, value); |
93f0822d DB |
928 | return (value >> 8) & 0xFF; |
929 | } | |
930 | ||
016c8150 | 931 | static int core_get_max_pstate(void) |
93f0822d | 932 | { |
6a35fc2d SP |
933 | u64 tar; |
934 | u64 plat_info; | |
935 | int max_pstate; | |
936 | int err; | |
937 | ||
938 | rdmsrl(MSR_PLATFORM_INFO, plat_info); | |
939 | max_pstate = (plat_info >> 8) & 0xFF; | |
940 | ||
941 | err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar); | |
942 | if (!err) { | |
943 | /* Do some sanity checking for safety */ | |
944 | if (plat_info & 0x600000000) { | |
945 | u64 tdp_ctrl; | |
946 | u64 tdp_ratio; | |
947 | int tdp_msr; | |
948 | ||
949 | err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl); | |
950 | if (err) | |
951 | goto skip_tar; | |
952 | ||
5fc8f707 | 953 | tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x3); |
6a35fc2d SP |
954 | err = rdmsrl_safe(tdp_msr, &tdp_ratio); |
955 | if (err) | |
956 | goto skip_tar; | |
957 | ||
1becf035 SP |
958 | /* For level 1 and 2, bits[23:16] contain the ratio */ |
959 | if (tdp_ctrl) | |
960 | tdp_ratio >>= 16; | |
961 | ||
962 | tdp_ratio &= 0xff; /* ratios are only 8 bits long */ | |
6a35fc2d SP |
963 | if (tdp_ratio - 1 == tar) { |
964 | max_pstate = tar; | |
965 | pr_debug("max_pstate=TAC %x\n", max_pstate); | |
966 | } else { | |
967 | goto skip_tar; | |
968 | } | |
969 | } | |
970 | } | |
845c1cbe | 971 | |
6a35fc2d SP |
972 | skip_tar: |
973 | return max_pstate; | |
93f0822d DB |
974 | } |
975 | ||
016c8150 | 976 | static int core_get_turbo_pstate(void) |
93f0822d DB |
977 | { |
978 | u64 value; | |
979 | int nont, ret; | |
845c1cbe | 980 | |
100cf6f2 | 981 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
016c8150 | 982 | nont = core_get_max_pstate(); |
285cb990 | 983 | ret = (value) & 255; |
93f0822d DB |
984 | if (ret <= nont) |
985 | ret = nont; | |
986 | return ret; | |
987 | } | |
988 | ||
b27580b0 DB |
989 | static inline int core_get_scaling(void) |
990 | { | |
991 | return 100000; | |
992 | } | |
993 | ||
fdfdb2b1 | 994 | static u64 core_get_val(struct cpudata *cpudata, int pstate) |
016c8150 DB |
995 | { |
996 | u64 val; | |
997 | ||
144c8e17 | 998 | val = (u64)pstate << 8; |
51443fbf | 999 | if (limits->no_turbo && !limits->turbo_disabled) |
016c8150 DB |
1000 | val |= (u64)1 << 32; |
1001 | ||
fdfdb2b1 | 1002 | return val; |
016c8150 DB |
1003 | } |
1004 | ||
b34ef932 DC |
1005 | static int knl_get_turbo_pstate(void) |
1006 | { | |
1007 | u64 value; | |
1008 | int nont, ret; | |
1009 | ||
100cf6f2 | 1010 | rdmsrl(MSR_TURBO_RATIO_LIMIT, value); |
b34ef932 DC |
1011 | nont = core_get_max_pstate(); |
1012 | ret = (((value) >> 8) & 0xFF); | |
1013 | if (ret <= nont) | |
1014 | ret = nont; | |
1015 | return ret; | |
1016 | } | |
1017 | ||
016c8150 DB |
1018 | static struct cpu_defaults core_params = { |
1019 | .pid_policy = { | |
1020 | .sample_rate_ms = 10, | |
1021 | .deadband = 0, | |
1022 | .setpoint = 97, | |
1023 | .p_gain_pct = 20, | |
1024 | .d_gain_pct = 0, | |
1025 | .i_gain_pct = 0, | |
1026 | }, | |
1027 | .funcs = { | |
1028 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1029 | .get_max_physical = core_get_max_pstate_physical, |
016c8150 DB |
1030 | .get_min = core_get_min_pstate, |
1031 | .get_turbo = core_get_turbo_pstate, | |
b27580b0 | 1032 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1033 | .get_val = core_get_val, |
157386b6 | 1034 | .get_target_pstate = get_target_pstate_use_performance, |
016c8150 DB |
1035 | }, |
1036 | }; | |
1037 | ||
42ce8921 | 1038 | static const struct cpu_defaults silvermont_params = { |
1421df63 PL |
1039 | .pid_policy = { |
1040 | .sample_rate_ms = 10, | |
1041 | .deadband = 0, | |
1042 | .setpoint = 60, | |
1043 | .p_gain_pct = 14, | |
1044 | .d_gain_pct = 0, | |
1045 | .i_gain_pct = 4, | |
09c448d3 | 1046 | .boost_iowait = true, |
1421df63 PL |
1047 | }, |
1048 | .funcs = { | |
1049 | .get_max = atom_get_max_pstate, | |
1050 | .get_max_physical = atom_get_max_pstate, | |
1051 | .get_min = atom_get_min_pstate, | |
1052 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1053 | .get_val = atom_get_val, |
1421df63 PL |
1054 | .get_scaling = silvermont_get_scaling, |
1055 | .get_vid = atom_get_vid, | |
e70eed2b | 1056 | .get_target_pstate = get_target_pstate_use_cpu_load, |
1421df63 PL |
1057 | }, |
1058 | }; | |
1059 | ||
42ce8921 | 1060 | static const struct cpu_defaults airmont_params = { |
19e77c28 DB |
1061 | .pid_policy = { |
1062 | .sample_rate_ms = 10, | |
1063 | .deadband = 0, | |
6a82ba6d | 1064 | .setpoint = 60, |
19e77c28 DB |
1065 | .p_gain_pct = 14, |
1066 | .d_gain_pct = 0, | |
1067 | .i_gain_pct = 4, | |
09c448d3 | 1068 | .boost_iowait = true, |
19e77c28 DB |
1069 | }, |
1070 | .funcs = { | |
938d21a2 PL |
1071 | .get_max = atom_get_max_pstate, |
1072 | .get_max_physical = atom_get_max_pstate, | |
1073 | .get_min = atom_get_min_pstate, | |
1074 | .get_turbo = atom_get_turbo_pstate, | |
fdfdb2b1 | 1075 | .get_val = atom_get_val, |
1421df63 | 1076 | .get_scaling = airmont_get_scaling, |
938d21a2 | 1077 | .get_vid = atom_get_vid, |
e70eed2b | 1078 | .get_target_pstate = get_target_pstate_use_cpu_load, |
19e77c28 DB |
1079 | }, |
1080 | }; | |
1081 | ||
42ce8921 | 1082 | static const struct cpu_defaults knl_params = { |
b34ef932 DC |
1083 | .pid_policy = { |
1084 | .sample_rate_ms = 10, | |
1085 | .deadband = 0, | |
1086 | .setpoint = 97, | |
1087 | .p_gain_pct = 20, | |
1088 | .d_gain_pct = 0, | |
1089 | .i_gain_pct = 0, | |
1090 | }, | |
1091 | .funcs = { | |
1092 | .get_max = core_get_max_pstate, | |
3bcc6fa9 | 1093 | .get_max_physical = core_get_max_pstate_physical, |
b34ef932 DC |
1094 | .get_min = core_get_min_pstate, |
1095 | .get_turbo = knl_get_turbo_pstate, | |
69cefc27 | 1096 | .get_scaling = core_get_scaling, |
fdfdb2b1 | 1097 | .get_val = core_get_val, |
157386b6 | 1098 | .get_target_pstate = get_target_pstate_use_performance, |
b34ef932 DC |
1099 | }, |
1100 | }; | |
1101 | ||
42ce8921 | 1102 | static const struct cpu_defaults bxt_params = { |
41bad47f SP |
1103 | .pid_policy = { |
1104 | .sample_rate_ms = 10, | |
1105 | .deadband = 0, | |
1106 | .setpoint = 60, | |
1107 | .p_gain_pct = 14, | |
1108 | .d_gain_pct = 0, | |
1109 | .i_gain_pct = 4, | |
09c448d3 | 1110 | .boost_iowait = true, |
41bad47f SP |
1111 | }, |
1112 | .funcs = { | |
1113 | .get_max = core_get_max_pstate, | |
1114 | .get_max_physical = core_get_max_pstate_physical, | |
1115 | .get_min = core_get_min_pstate, | |
1116 | .get_turbo = core_get_turbo_pstate, | |
1117 | .get_scaling = core_get_scaling, | |
1118 | .get_val = core_get_val, | |
1119 | .get_target_pstate = get_target_pstate_use_cpu_load, | |
1120 | }, | |
1121 | }; | |
1122 | ||
93f0822d DB |
1123 | static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max) |
1124 | { | |
1125 | int max_perf = cpu->pstate.turbo_pstate; | |
7244cb62 | 1126 | int max_perf_adj; |
93f0822d | 1127 | int min_perf; |
845c1cbe | 1128 | |
51443fbf | 1129 | if (limits->no_turbo || limits->turbo_disabled) |
93f0822d DB |
1130 | max_perf = cpu->pstate.max_pstate; |
1131 | ||
e0d4c8f8 KCA |
1132 | /* |
1133 | * performance can be limited by user through sysfs, by cpufreq | |
1134 | * policy, or by cpu specific default values determined through | |
1135 | * experimentation. | |
1136 | */ | |
a158bed5 | 1137 | max_perf_adj = fp_toint(max_perf * limits->max_perf); |
799281a3 RW |
1138 | *max = clamp_t(int, max_perf_adj, |
1139 | cpu->pstate.min_pstate, cpu->pstate.turbo_pstate); | |
93f0822d | 1140 | |
a158bed5 | 1141 | min_perf = fp_toint(max_perf * limits->min_perf); |
799281a3 | 1142 | *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf); |
93f0822d DB |
1143 | } |
1144 | ||
fdfdb2b1 RW |
1145 | static void intel_pstate_set_min_pstate(struct cpudata *cpu) |
1146 | { | |
1147 | int pstate = cpu->pstate.min_pstate; | |
1148 | ||
bc95a454 RW |
1149 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
1150 | cpu->pstate.current_pstate = pstate; | |
fdfdb2b1 RW |
1151 | /* |
1152 | * Generally, there is no guarantee that this code will always run on | |
1153 | * the CPU being updated, so force the register update to run on the | |
1154 | * right CPU. | |
1155 | */ | |
1156 | wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL, | |
1157 | pstate_funcs.get_val(cpu, pstate)); | |
93f0822d DB |
1158 | } |
1159 | ||
93f0822d DB |
1160 | static void intel_pstate_get_cpu_pstates(struct cpudata *cpu) |
1161 | { | |
016c8150 DB |
1162 | cpu->pstate.min_pstate = pstate_funcs.get_min(); |
1163 | cpu->pstate.max_pstate = pstate_funcs.get_max(); | |
3bcc6fa9 | 1164 | cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical(); |
016c8150 | 1165 | cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(); |
b27580b0 | 1166 | cpu->pstate.scaling = pstate_funcs.get_scaling(); |
93f0822d | 1167 | |
007bea09 DB |
1168 | if (pstate_funcs.get_vid) |
1169 | pstate_funcs.get_vid(cpu); | |
fdfdb2b1 RW |
1170 | |
1171 | intel_pstate_set_min_pstate(cpu); | |
93f0822d DB |
1172 | } |
1173 | ||
a1c9787d | 1174 | static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu) |
93f0822d | 1175 | { |
6b17ddb2 | 1176 | struct sample *sample = &cpu->sample; |
e66c1768 | 1177 | |
a1c9787d | 1178 | sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf); |
93f0822d DB |
1179 | } |
1180 | ||
4fec7ad5 | 1181 | static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time) |
93f0822d | 1182 | { |
93f0822d | 1183 | u64 aperf, mperf; |
4ab60c3f | 1184 | unsigned long flags; |
4055fad3 | 1185 | u64 tsc; |
93f0822d | 1186 | |
4ab60c3f | 1187 | local_irq_save(flags); |
93f0822d DB |
1188 | rdmsrl(MSR_IA32_APERF, aperf); |
1189 | rdmsrl(MSR_IA32_MPERF, mperf); | |
e70eed2b | 1190 | tsc = rdtsc(); |
4fec7ad5 | 1191 | if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) { |
8e601a9f | 1192 | local_irq_restore(flags); |
4fec7ad5 | 1193 | return false; |
8e601a9f | 1194 | } |
4ab60c3f | 1195 | local_irq_restore(flags); |
b69880f9 | 1196 | |
c4ee841f | 1197 | cpu->last_sample_time = cpu->sample.time; |
a4675fbc | 1198 | cpu->sample.time = time; |
d37e2b76 DB |
1199 | cpu->sample.aperf = aperf; |
1200 | cpu->sample.mperf = mperf; | |
4055fad3 | 1201 | cpu->sample.tsc = tsc; |
d37e2b76 DB |
1202 | cpu->sample.aperf -= cpu->prev_aperf; |
1203 | cpu->sample.mperf -= cpu->prev_mperf; | |
4055fad3 | 1204 | cpu->sample.tsc -= cpu->prev_tsc; |
1abc4b20 | 1205 | |
93f0822d DB |
1206 | cpu->prev_aperf = aperf; |
1207 | cpu->prev_mperf = mperf; | |
4055fad3 | 1208 | cpu->prev_tsc = tsc; |
febce40f RW |
1209 | /* |
1210 | * First time this function is invoked in a given cycle, all of the | |
1211 | * previous sample data fields are equal to zero or stale and they must | |
1212 | * be populated with meaningful numbers for things to work, so assume | |
1213 | * that sample.time will always be reset before setting the utilization | |
1214 | * update hook and make the caller skip the sample then. | |
1215 | */ | |
1216 | return !!cpu->last_sample_time; | |
93f0822d DB |
1217 | } |
1218 | ||
8fa520af PL |
1219 | static inline int32_t get_avg_frequency(struct cpudata *cpu) |
1220 | { | |
a1c9787d RW |
1221 | return mul_ext_fp(cpu->sample.core_avg_perf, |
1222 | cpu->pstate.max_pstate_physical * cpu->pstate.scaling); | |
8fa520af PL |
1223 | } |
1224 | ||
bdcaa23f PL |
1225 | static inline int32_t get_avg_pstate(struct cpudata *cpu) |
1226 | { | |
8edb0a6e RW |
1227 | return mul_ext_fp(cpu->pstate.max_pstate_physical, |
1228 | cpu->sample.core_avg_perf); | |
bdcaa23f PL |
1229 | } |
1230 | ||
e70eed2b PL |
1231 | static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu) |
1232 | { | |
1233 | struct sample *sample = &cpu->sample; | |
09c448d3 | 1234 | int32_t busy_frac, boost; |
e70eed2b | 1235 | |
09c448d3 | 1236 | busy_frac = div_fp(sample->mperf, sample->tsc); |
63d1d656 | 1237 | |
09c448d3 RW |
1238 | boost = cpu->iowait_boost; |
1239 | cpu->iowait_boost >>= 1; | |
63d1d656 | 1240 | |
09c448d3 RW |
1241 | if (busy_frac < boost) |
1242 | busy_frac = boost; | |
63d1d656 | 1243 | |
09c448d3 RW |
1244 | sample->busy_scaled = busy_frac * 100; |
1245 | return get_avg_pstate(cpu) - pid_calc(&cpu->pid, sample->busy_scaled); | |
e70eed2b PL |
1246 | } |
1247 | ||
157386b6 | 1248 | static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu) |
93f0822d | 1249 | { |
1aa7a6e2 | 1250 | int32_t perf_scaled, max_pstate, current_pstate, sample_ratio; |
a4675fbc | 1251 | u64 duration_ns; |
93f0822d | 1252 | |
e0d4c8f8 | 1253 | /* |
f00593a4 RW |
1254 | * perf_scaled is the ratio of the average P-state during the last |
1255 | * sampling period to the P-state requested last time (in percent). | |
1256 | * | |
1257 | * That measures the system's response to the previous P-state | |
1258 | * selection. | |
e0d4c8f8 | 1259 | */ |
22590efb RW |
1260 | max_pstate = cpu->pstate.max_pstate_physical; |
1261 | current_pstate = cpu->pstate.current_pstate; | |
1aa7a6e2 | 1262 | perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf, |
a1c9787d | 1263 | div_fp(100 * max_pstate, current_pstate)); |
c4ee841f | 1264 | |
e0d4c8f8 | 1265 | /* |
a4675fbc RW |
1266 | * Since our utilization update callback will not run unless we are |
1267 | * in C0, check if the actual elapsed time is significantly greater (3x) | |
1268 | * than our sample interval. If it is, then we were idle for a long | |
1aa7a6e2 | 1269 | * enough period of time to adjust our performance metric. |
e0d4c8f8 | 1270 | */ |
a4675fbc | 1271 | duration_ns = cpu->sample.time - cpu->last_sample_time; |
febce40f | 1272 | if ((s64)duration_ns > pid_params.sample_rate_ns * 3) { |
22590efb | 1273 | sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns); |
1aa7a6e2 | 1274 | perf_scaled = mul_fp(perf_scaled, sample_ratio); |
ffb81056 RW |
1275 | } else { |
1276 | sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc); | |
1277 | if (sample_ratio < int_tofp(1)) | |
1aa7a6e2 | 1278 | perf_scaled = 0; |
c4ee841f DB |
1279 | } |
1280 | ||
1aa7a6e2 RW |
1281 | cpu->sample.busy_scaled = perf_scaled; |
1282 | return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled); | |
93f0822d DB |
1283 | } |
1284 | ||
fdfdb2b1 RW |
1285 | static inline void intel_pstate_update_pstate(struct cpudata *cpu, int pstate) |
1286 | { | |
1287 | int max_perf, min_perf; | |
1288 | ||
1289 | update_turbo_state(); | |
1290 | ||
1291 | intel_pstate_get_min_max(cpu, &min_perf, &max_perf); | |
1292 | pstate = clamp_t(int, pstate, min_perf, max_perf); | |
bc95a454 | 1293 | trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu); |
fdfdb2b1 RW |
1294 | if (pstate == cpu->pstate.current_pstate) |
1295 | return; | |
1296 | ||
bc95a454 | 1297 | cpu->pstate.current_pstate = pstate; |
fdfdb2b1 RW |
1298 | wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate)); |
1299 | } | |
1300 | ||
93f0822d DB |
1301 | static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu) |
1302 | { | |
157386b6 | 1303 | int from, target_pstate; |
4055fad3 DS |
1304 | struct sample *sample; |
1305 | ||
1306 | from = cpu->pstate.current_pstate; | |
93f0822d | 1307 | |
157386b6 | 1308 | target_pstate = pstate_funcs.get_target_pstate(cpu); |
93f0822d | 1309 | |
fdfdb2b1 | 1310 | intel_pstate_update_pstate(cpu, target_pstate); |
4055fad3 DS |
1311 | |
1312 | sample = &cpu->sample; | |
a1c9787d | 1313 | trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf), |
157386b6 | 1314 | fp_toint(sample->busy_scaled), |
4055fad3 DS |
1315 | from, |
1316 | cpu->pstate.current_pstate, | |
1317 | sample->mperf, | |
1318 | sample->aperf, | |
1319 | sample->tsc, | |
3ba7bcaa SP |
1320 | get_avg_frequency(cpu), |
1321 | fp_toint(cpu->iowait_boost * 100)); | |
93f0822d DB |
1322 | } |
1323 | ||
a4675fbc | 1324 | static void intel_pstate_update_util(struct update_util_data *data, u64 time, |
58919e83 | 1325 | unsigned int flags) |
93f0822d | 1326 | { |
a4675fbc | 1327 | struct cpudata *cpu = container_of(data, struct cpudata, update_util); |
09c448d3 RW |
1328 | u64 delta_ns; |
1329 | ||
1330 | if (pid_params.boost_iowait) { | |
1331 | if (flags & SCHED_CPUFREQ_IOWAIT) { | |
1332 | cpu->iowait_boost = int_tofp(1); | |
1333 | } else if (cpu->iowait_boost) { | |
1334 | /* Clear iowait_boost if the CPU may have been idle. */ | |
1335 | delta_ns = time - cpu->last_update; | |
1336 | if (delta_ns > TICK_NSEC) | |
1337 | cpu->iowait_boost = 0; | |
1338 | } | |
1339 | cpu->last_update = time; | |
1340 | } | |
b69880f9 | 1341 | |
09c448d3 | 1342 | delta_ns = time - cpu->sample.time; |
a4675fbc | 1343 | if ((s64)delta_ns >= pid_params.sample_rate_ns) { |
4fec7ad5 RW |
1344 | bool sample_taken = intel_pstate_sample(cpu, time); |
1345 | ||
6d45b719 | 1346 | if (sample_taken) { |
a1c9787d | 1347 | intel_pstate_calc_avg_perf(cpu); |
6d45b719 RW |
1348 | if (!hwp_active) |
1349 | intel_pstate_adjust_busy_pstate(cpu); | |
1350 | } | |
a4675fbc | 1351 | } |
93f0822d DB |
1352 | } |
1353 | ||
1354 | #define ICPU(model, policy) \ | |
6cbd7ee1 DB |
1355 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\ |
1356 | (unsigned long)&policy } | |
93f0822d DB |
1357 | |
1358 | static const struct x86_cpu_id intel_pstate_cpu_ids[] = { | |
5b20c944 DH |
1359 | ICPU(INTEL_FAM6_SANDYBRIDGE, core_params), |
1360 | ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_params), | |
1361 | ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_params), | |
1362 | ICPU(INTEL_FAM6_IVYBRIDGE, core_params), | |
1363 | ICPU(INTEL_FAM6_HASWELL_CORE, core_params), | |
1364 | ICPU(INTEL_FAM6_BROADWELL_CORE, core_params), | |
1365 | ICPU(INTEL_FAM6_IVYBRIDGE_X, core_params), | |
1366 | ICPU(INTEL_FAM6_HASWELL_X, core_params), | |
1367 | ICPU(INTEL_FAM6_HASWELL_ULT, core_params), | |
1368 | ICPU(INTEL_FAM6_HASWELL_GT3E, core_params), | |
1369 | ICPU(INTEL_FAM6_BROADWELL_GT3E, core_params), | |
1370 | ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_params), | |
1371 | ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_params), | |
1372 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), | |
1373 | ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_params), | |
1374 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), | |
1375 | ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_params), | |
41bad47f | 1376 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, bxt_params), |
93f0822d DB |
1377 | {} |
1378 | }; | |
1379 | MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids); | |
1380 | ||
29327c84 | 1381 | static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = { |
5b20c944 | 1382 | ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params), |
65c1262f SP |
1383 | ICPU(INTEL_FAM6_BROADWELL_X, core_params), |
1384 | ICPU(INTEL_FAM6_SKYLAKE_X, core_params), | |
2f86dc4c DB |
1385 | {} |
1386 | }; | |
1387 | ||
93f0822d DB |
1388 | static int intel_pstate_init_cpu(unsigned int cpunum) |
1389 | { | |
93f0822d DB |
1390 | struct cpudata *cpu; |
1391 | ||
c0348717 DB |
1392 | if (!all_cpu_data[cpunum]) |
1393 | all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), | |
1394 | GFP_KERNEL); | |
93f0822d DB |
1395 | if (!all_cpu_data[cpunum]) |
1396 | return -ENOMEM; | |
1397 | ||
1398 | cpu = all_cpu_data[cpunum]; | |
1399 | ||
93f0822d | 1400 | cpu->cpu = cpunum; |
ba88d433 | 1401 | |
a4675fbc | 1402 | if (hwp_active) { |
ba88d433 | 1403 | intel_pstate_hwp_enable(cpu); |
a4675fbc RW |
1404 | pid_params.sample_rate_ms = 50; |
1405 | pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC; | |
1406 | } | |
ba88d433 | 1407 | |
179e8471 | 1408 | intel_pstate_get_cpu_pstates(cpu); |
016c8150 | 1409 | |
93f0822d | 1410 | intel_pstate_busy_pid_reset(cpu); |
93f0822d | 1411 | |
4836df17 | 1412 | pr_debug("controlling: cpu %d\n", cpunum); |
93f0822d DB |
1413 | |
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static unsigned int intel_pstate_get(unsigned int cpu_num) | |
1418 | { | |
f96fd0c8 | 1419 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
93f0822d | 1420 | |
f96fd0c8 | 1421 | return cpu ? get_avg_frequency(cpu) : 0; |
93f0822d DB |
1422 | } |
1423 | ||
febce40f | 1424 | static void intel_pstate_set_update_util_hook(unsigned int cpu_num) |
bb6ab52f | 1425 | { |
febce40f RW |
1426 | struct cpudata *cpu = all_cpu_data[cpu_num]; |
1427 | ||
5ab666e0 RW |
1428 | if (cpu->update_util_set) |
1429 | return; | |
1430 | ||
febce40f RW |
1431 | /* Prevent intel_pstate_update_util() from using stale data. */ |
1432 | cpu->sample.time = 0; | |
0bed612b RW |
1433 | cpufreq_add_update_util_hook(cpu_num, &cpu->update_util, |
1434 | intel_pstate_update_util); | |
4578ee7e | 1435 | cpu->update_util_set = true; |
bb6ab52f RW |
1436 | } |
1437 | ||
1438 | static void intel_pstate_clear_update_util_hook(unsigned int cpu) | |
1439 | { | |
4578ee7e CY |
1440 | struct cpudata *cpu_data = all_cpu_data[cpu]; |
1441 | ||
1442 | if (!cpu_data->update_util_set) | |
1443 | return; | |
1444 | ||
0bed612b | 1445 | cpufreq_remove_update_util_hook(cpu); |
4578ee7e | 1446 | cpu_data->update_util_set = false; |
bb6ab52f RW |
1447 | synchronize_sched(); |
1448 | } | |
1449 | ||
30a39153 SP |
1450 | static void intel_pstate_set_performance_limits(struct perf_limits *limits) |
1451 | { | |
1452 | limits->no_turbo = 0; | |
1453 | limits->turbo_disabled = 0; | |
1454 | limits->max_perf_pct = 100; | |
1455 | limits->max_perf = int_tofp(1); | |
1456 | limits->min_perf_pct = 100; | |
1457 | limits->min_perf = int_tofp(1); | |
1458 | limits->max_policy_pct = 100; | |
1459 | limits->max_sysfs_pct = 100; | |
1460 | limits->min_policy_pct = 0; | |
1461 | limits->min_sysfs_pct = 0; | |
1462 | } | |
1463 | ||
93f0822d DB |
1464 | static int intel_pstate_set_policy(struct cpufreq_policy *policy) |
1465 | { | |
3be9200d SP |
1466 | struct cpudata *cpu; |
1467 | ||
d3929b83 DB |
1468 | if (!policy->cpuinfo.max_freq) |
1469 | return -ENODEV; | |
1470 | ||
2c2c1af4 SP |
1471 | pr_debug("set_policy cpuinfo.max %u policy->max %u\n", |
1472 | policy->cpuinfo.max_freq, policy->max); | |
1473 | ||
3be9200d | 1474 | cpu = all_cpu_data[0]; |
c749c64f RW |
1475 | if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate && |
1476 | policy->max < policy->cpuinfo.max_freq && | |
1477 | policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) { | |
1478 | pr_debug("policy->max > max non turbo frequency\n"); | |
1479 | policy->max = policy->cpuinfo.max_freq; | |
3be9200d SP |
1480 | } |
1481 | ||
30a39153 | 1482 | if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { |
51443fbf | 1483 | limits = &performance_limits; |
30a39153 | 1484 | if (policy->max >= policy->cpuinfo.max_freq) { |
4836df17 | 1485 | pr_debug("set performance\n"); |
30a39153 SP |
1486 | intel_pstate_set_performance_limits(limits); |
1487 | goto out; | |
1488 | } | |
1489 | } else { | |
4836df17 | 1490 | pr_debug("set powersave\n"); |
30a39153 | 1491 | limits = &powersave_limits; |
93f0822d | 1492 | } |
2f86dc4c | 1493 | |
51443fbf PB |
1494 | limits->min_policy_pct = (policy->min * 100) / policy->cpuinfo.max_freq; |
1495 | limits->min_policy_pct = clamp_t(int, limits->min_policy_pct, 0 , 100); | |
8478f539 PB |
1496 | limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100, |
1497 | policy->cpuinfo.max_freq); | |
51443fbf | 1498 | limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0 , 100); |
43717aad CY |
1499 | |
1500 | /* Normalize user input to [min_policy_pct, max_policy_pct] */ | |
51443fbf PB |
1501 | limits->min_perf_pct = max(limits->min_policy_pct, |
1502 | limits->min_sysfs_pct); | |
1503 | limits->min_perf_pct = min(limits->max_policy_pct, | |
1504 | limits->min_perf_pct); | |
1505 | limits->max_perf_pct = min(limits->max_policy_pct, | |
1506 | limits->max_sysfs_pct); | |
1507 | limits->max_perf_pct = max(limits->min_policy_pct, | |
1508 | limits->max_perf_pct); | |
43717aad CY |
1509 | |
1510 | /* Make sure min_perf_pct <= max_perf_pct */ | |
51443fbf | 1511 | limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct); |
43717aad | 1512 | |
22590efb RW |
1513 | limits->min_perf = div_fp(limits->min_perf_pct, 100); |
1514 | limits->max_perf = div_fp(limits->max_perf_pct, 100); | |
2c2c1af4 | 1515 | limits->max_perf = round_up(limits->max_perf, FRAC_BITS); |
93f0822d | 1516 | |
bb6ab52f RW |
1517 | out: |
1518 | intel_pstate_set_update_util_hook(policy->cpu); | |
1519 | ||
ba41e1bc | 1520 | intel_pstate_hwp_set_policy(policy); |
2f86dc4c | 1521 | |
93f0822d DB |
1522 | return 0; |
1523 | } | |
1524 | ||
1525 | static int intel_pstate_verify_policy(struct cpufreq_policy *policy) | |
1526 | { | |
be49e346 | 1527 | cpufreq_verify_within_cpu_limits(policy); |
93f0822d | 1528 | |
285cb990 | 1529 | if (policy->policy != CPUFREQ_POLICY_POWERSAVE && |
c410833a | 1530 | policy->policy != CPUFREQ_POLICY_PERFORMANCE) |
93f0822d DB |
1531 | return -EINVAL; |
1532 | ||
1533 | return 0; | |
1534 | } | |
1535 | ||
bb18008f | 1536 | static void intel_pstate_stop_cpu(struct cpufreq_policy *policy) |
93f0822d | 1537 | { |
bb18008f DB |
1538 | int cpu_num = policy->cpu; |
1539 | struct cpudata *cpu = all_cpu_data[cpu_num]; | |
93f0822d | 1540 | |
4836df17 | 1541 | pr_debug("CPU %d exiting\n", cpu_num); |
bb18008f | 1542 | |
bb6ab52f | 1543 | intel_pstate_clear_update_util_hook(cpu_num); |
a4675fbc | 1544 | |
2f86dc4c DB |
1545 | if (hwp_active) |
1546 | return; | |
1547 | ||
fdfdb2b1 | 1548 | intel_pstate_set_min_pstate(cpu); |
93f0822d DB |
1549 | } |
1550 | ||
2760984f | 1551 | static int intel_pstate_cpu_init(struct cpufreq_policy *policy) |
93f0822d | 1552 | { |
93f0822d | 1553 | struct cpudata *cpu; |
52e0a509 | 1554 | int rc; |
93f0822d DB |
1555 | |
1556 | rc = intel_pstate_init_cpu(policy->cpu); | |
1557 | if (rc) | |
1558 | return rc; | |
1559 | ||
1560 | cpu = all_cpu_data[policy->cpu]; | |
1561 | ||
51443fbf | 1562 | if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100) |
93f0822d DB |
1563 | policy->policy = CPUFREQ_POLICY_PERFORMANCE; |
1564 | else | |
1565 | policy->policy = CPUFREQ_POLICY_POWERSAVE; | |
1566 | ||
b27580b0 DB |
1567 | policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling; |
1568 | policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling; | |
93f0822d DB |
1569 | |
1570 | /* cpuinfo and default policy values */ | |
b27580b0 | 1571 | policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling; |
983e600e SP |
1572 | update_turbo_state(); |
1573 | policy->cpuinfo.max_freq = limits->turbo_disabled ? | |
1574 | cpu->pstate.max_pstate : cpu->pstate.turbo_pstate; | |
1575 | policy->cpuinfo.max_freq *= cpu->pstate.scaling; | |
1576 | ||
9522a2ff | 1577 | intel_pstate_init_acpi_perf_limits(policy); |
93f0822d DB |
1578 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; |
1579 | cpumask_set_cpu(policy->cpu, policy->cpus); | |
1580 | ||
1581 | return 0; | |
1582 | } | |
1583 | ||
9522a2ff SP |
1584 | static int intel_pstate_cpu_exit(struct cpufreq_policy *policy) |
1585 | { | |
1586 | intel_pstate_exit_perf_limits(policy); | |
1587 | ||
1588 | return 0; | |
1589 | } | |
1590 | ||
93f0822d DB |
1591 | static struct cpufreq_driver intel_pstate_driver = { |
1592 | .flags = CPUFREQ_CONST_LOOPS, | |
1593 | .verify = intel_pstate_verify_policy, | |
1594 | .setpolicy = intel_pstate_set_policy, | |
ba41e1bc | 1595 | .resume = intel_pstate_hwp_set_policy, |
93f0822d DB |
1596 | .get = intel_pstate_get, |
1597 | .init = intel_pstate_cpu_init, | |
9522a2ff | 1598 | .exit = intel_pstate_cpu_exit, |
bb18008f | 1599 | .stop_cpu = intel_pstate_stop_cpu, |
93f0822d | 1600 | .name = "intel_pstate", |
93f0822d DB |
1601 | }; |
1602 | ||
eed43609 JZ |
1603 | static int no_load __initdata; |
1604 | static int no_hwp __initdata; | |
1605 | static int hwp_only __initdata; | |
29327c84 | 1606 | static unsigned int force_load __initdata; |
6be26498 | 1607 | |
29327c84 | 1608 | static int __init intel_pstate_msrs_not_valid(void) |
b563b4e3 | 1609 | { |
016c8150 | 1610 | if (!pstate_funcs.get_max() || |
c410833a SK |
1611 | !pstate_funcs.get_min() || |
1612 | !pstate_funcs.get_turbo()) | |
b563b4e3 DB |
1613 | return -ENODEV; |
1614 | ||
b563b4e3 DB |
1615 | return 0; |
1616 | } | |
016c8150 | 1617 | |
29327c84 | 1618 | static void __init copy_pid_params(struct pstate_adjust_policy *policy) |
016c8150 DB |
1619 | { |
1620 | pid_params.sample_rate_ms = policy->sample_rate_ms; | |
a4675fbc | 1621 | pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC; |
016c8150 DB |
1622 | pid_params.p_gain_pct = policy->p_gain_pct; |
1623 | pid_params.i_gain_pct = policy->i_gain_pct; | |
1624 | pid_params.d_gain_pct = policy->d_gain_pct; | |
1625 | pid_params.deadband = policy->deadband; | |
1626 | pid_params.setpoint = policy->setpoint; | |
1627 | } | |
1628 | ||
29327c84 | 1629 | static void __init copy_cpu_funcs(struct pstate_funcs *funcs) |
016c8150 DB |
1630 | { |
1631 | pstate_funcs.get_max = funcs->get_max; | |
3bcc6fa9 | 1632 | pstate_funcs.get_max_physical = funcs->get_max_physical; |
016c8150 DB |
1633 | pstate_funcs.get_min = funcs->get_min; |
1634 | pstate_funcs.get_turbo = funcs->get_turbo; | |
b27580b0 | 1635 | pstate_funcs.get_scaling = funcs->get_scaling; |
fdfdb2b1 | 1636 | pstate_funcs.get_val = funcs->get_val; |
007bea09 | 1637 | pstate_funcs.get_vid = funcs->get_vid; |
157386b6 PL |
1638 | pstate_funcs.get_target_pstate = funcs->get_target_pstate; |
1639 | ||
016c8150 DB |
1640 | } |
1641 | ||
9522a2ff | 1642 | #ifdef CONFIG_ACPI |
fbbcdc07 | 1643 | |
29327c84 | 1644 | static bool __init intel_pstate_no_acpi_pss(void) |
fbbcdc07 AH |
1645 | { |
1646 | int i; | |
1647 | ||
1648 | for_each_possible_cpu(i) { | |
1649 | acpi_status status; | |
1650 | union acpi_object *pss; | |
1651 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1652 | struct acpi_processor *pr = per_cpu(processors, i); | |
1653 | ||
1654 | if (!pr) | |
1655 | continue; | |
1656 | ||
1657 | status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer); | |
1658 | if (ACPI_FAILURE(status)) | |
1659 | continue; | |
1660 | ||
1661 | pss = buffer.pointer; | |
1662 | if (pss && pss->type == ACPI_TYPE_PACKAGE) { | |
1663 | kfree(pss); | |
1664 | return false; | |
1665 | } | |
1666 | ||
1667 | kfree(pss); | |
1668 | } | |
1669 | ||
1670 | return true; | |
1671 | } | |
1672 | ||
29327c84 | 1673 | static bool __init intel_pstate_has_acpi_ppc(void) |
966916ea | 1674 | { |
1675 | int i; | |
1676 | ||
1677 | for_each_possible_cpu(i) { | |
1678 | struct acpi_processor *pr = per_cpu(processors, i); | |
1679 | ||
1680 | if (!pr) | |
1681 | continue; | |
1682 | if (acpi_has_method(pr->handle, "_PPC")) | |
1683 | return true; | |
1684 | } | |
1685 | return false; | |
1686 | } | |
1687 | ||
1688 | enum { | |
1689 | PSS, | |
1690 | PPC, | |
1691 | }; | |
1692 | ||
fbbcdc07 AH |
1693 | struct hw_vendor_info { |
1694 | u16 valid; | |
1695 | char oem_id[ACPI_OEM_ID_SIZE]; | |
1696 | char oem_table_id[ACPI_OEM_TABLE_ID_SIZE]; | |
966916ea | 1697 | int oem_pwr_table; |
fbbcdc07 AH |
1698 | }; |
1699 | ||
1700 | /* Hardware vendor-specific info that has its own power management modes */ | |
29327c84 | 1701 | static struct hw_vendor_info vendor_info[] __initdata = { |
966916ea | 1702 | {1, "HP ", "ProLiant", PSS}, |
1703 | {1, "ORACLE", "X4-2 ", PPC}, | |
1704 | {1, "ORACLE", "X4-2L ", PPC}, | |
1705 | {1, "ORACLE", "X4-2B ", PPC}, | |
1706 | {1, "ORACLE", "X3-2 ", PPC}, | |
1707 | {1, "ORACLE", "X3-2L ", PPC}, | |
1708 | {1, "ORACLE", "X3-2B ", PPC}, | |
1709 | {1, "ORACLE", "X4470M2 ", PPC}, | |
1710 | {1, "ORACLE", "X4270M3 ", PPC}, | |
1711 | {1, "ORACLE", "X4270M2 ", PPC}, | |
1712 | {1, "ORACLE", "X4170M2 ", PPC}, | |
5aecc3c8 EZ |
1713 | {1, "ORACLE", "X4170 M3", PPC}, |
1714 | {1, "ORACLE", "X4275 M3", PPC}, | |
1715 | {1, "ORACLE", "X6-2 ", PPC}, | |
1716 | {1, "ORACLE", "Sudbury ", PPC}, | |
fbbcdc07 AH |
1717 | {0, "", ""}, |
1718 | }; | |
1719 | ||
29327c84 | 1720 | static bool __init intel_pstate_platform_pwr_mgmt_exists(void) |
fbbcdc07 AH |
1721 | { |
1722 | struct acpi_table_header hdr; | |
1723 | struct hw_vendor_info *v_info; | |
2f86dc4c DB |
1724 | const struct x86_cpu_id *id; |
1725 | u64 misc_pwr; | |
1726 | ||
1727 | id = x86_match_cpu(intel_pstate_cpu_oob_ids); | |
1728 | if (id) { | |
1729 | rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr); | |
1730 | if ( misc_pwr & (1 << 8)) | |
1731 | return true; | |
1732 | } | |
fbbcdc07 | 1733 | |
c410833a SK |
1734 | if (acpi_disabled || |
1735 | ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr))) | |
fbbcdc07 AH |
1736 | return false; |
1737 | ||
1738 | for (v_info = vendor_info; v_info->valid; v_info++) { | |
c410833a | 1739 | if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) && |
966916ea | 1740 | !strncmp(hdr.oem_table_id, v_info->oem_table_id, |
1741 | ACPI_OEM_TABLE_ID_SIZE)) | |
1742 | switch (v_info->oem_pwr_table) { | |
1743 | case PSS: | |
1744 | return intel_pstate_no_acpi_pss(); | |
1745 | case PPC: | |
aa4ea34d EZ |
1746 | return intel_pstate_has_acpi_ppc() && |
1747 | (!force_load); | |
966916ea | 1748 | } |
fbbcdc07 AH |
1749 | } |
1750 | ||
1751 | return false; | |
1752 | } | |
1753 | #else /* CONFIG_ACPI not enabled */ | |
1754 | static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; } | |
966916ea | 1755 | static inline bool intel_pstate_has_acpi_ppc(void) { return false; } |
fbbcdc07 AH |
1756 | #endif /* CONFIG_ACPI */ |
1757 | ||
7791e4aa SP |
1758 | static const struct x86_cpu_id hwp_support_ids[] __initconst = { |
1759 | { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP }, | |
1760 | {} | |
1761 | }; | |
1762 | ||
93f0822d DB |
1763 | static int __init intel_pstate_init(void) |
1764 | { | |
907cc908 | 1765 | int cpu, rc = 0; |
93f0822d | 1766 | const struct x86_cpu_id *id; |
64df1fdf | 1767 | struct cpu_defaults *cpu_def; |
93f0822d | 1768 | |
6be26498 DB |
1769 | if (no_load) |
1770 | return -ENODEV; | |
1771 | ||
7791e4aa SP |
1772 | if (x86_match_cpu(hwp_support_ids) && !no_hwp) { |
1773 | copy_cpu_funcs(&core_params.funcs); | |
1774 | hwp_active++; | |
1775 | goto hwp_cpu_matched; | |
1776 | } | |
1777 | ||
93f0822d DB |
1778 | id = x86_match_cpu(intel_pstate_cpu_ids); |
1779 | if (!id) | |
1780 | return -ENODEV; | |
1781 | ||
64df1fdf | 1782 | cpu_def = (struct cpu_defaults *)id->driver_data; |
016c8150 | 1783 | |
64df1fdf BP |
1784 | copy_pid_params(&cpu_def->pid_policy); |
1785 | copy_cpu_funcs(&cpu_def->funcs); | |
016c8150 | 1786 | |
b563b4e3 DB |
1787 | if (intel_pstate_msrs_not_valid()) |
1788 | return -ENODEV; | |
1789 | ||
7791e4aa SP |
1790 | hwp_cpu_matched: |
1791 | /* | |
1792 | * The Intel pstate driver will be ignored if the platform | |
1793 | * firmware has its own power management modes. | |
1794 | */ | |
1795 | if (intel_pstate_platform_pwr_mgmt_exists()) | |
1796 | return -ENODEV; | |
1797 | ||
4836df17 | 1798 | pr_info("Intel P-state driver initializing\n"); |
93f0822d | 1799 | |
b57ffac5 | 1800 | all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus()); |
93f0822d DB |
1801 | if (!all_cpu_data) |
1802 | return -ENOMEM; | |
93f0822d | 1803 | |
d64c3b0b KCA |
1804 | if (!hwp_active && hwp_only) |
1805 | goto out; | |
1806 | ||
93f0822d DB |
1807 | rc = cpufreq_register_driver(&intel_pstate_driver); |
1808 | if (rc) | |
1809 | goto out; | |
1810 | ||
1811 | intel_pstate_debug_expose_params(); | |
1812 | intel_pstate_sysfs_expose_params(); | |
b69880f9 | 1813 | |
7791e4aa | 1814 | if (hwp_active) |
4836df17 | 1815 | pr_info("HWP enabled\n"); |
7791e4aa | 1816 | |
93f0822d DB |
1817 | return rc; |
1818 | out: | |
907cc908 DB |
1819 | get_online_cpus(); |
1820 | for_each_online_cpu(cpu) { | |
1821 | if (all_cpu_data[cpu]) { | |
bb6ab52f | 1822 | intel_pstate_clear_update_util_hook(cpu); |
907cc908 DB |
1823 | kfree(all_cpu_data[cpu]); |
1824 | } | |
1825 | } | |
1826 | ||
1827 | put_online_cpus(); | |
1828 | vfree(all_cpu_data); | |
93f0822d DB |
1829 | return -ENODEV; |
1830 | } | |
1831 | device_initcall(intel_pstate_init); | |
1832 | ||
6be26498 DB |
1833 | static int __init intel_pstate_setup(char *str) |
1834 | { | |
1835 | if (!str) | |
1836 | return -EINVAL; | |
1837 | ||
1838 | if (!strcmp(str, "disable")) | |
1839 | no_load = 1; | |
539342f6 | 1840 | if (!strcmp(str, "no_hwp")) { |
4836df17 | 1841 | pr_info("HWP disabled\n"); |
2f86dc4c | 1842 | no_hwp = 1; |
539342f6 | 1843 | } |
aa4ea34d EZ |
1844 | if (!strcmp(str, "force")) |
1845 | force_load = 1; | |
d64c3b0b KCA |
1846 | if (!strcmp(str, "hwp_only")) |
1847 | hwp_only = 1; | |
9522a2ff SP |
1848 | |
1849 | #ifdef CONFIG_ACPI | |
1850 | if (!strcmp(str, "support_acpi_ppc")) | |
1851 | acpi_ppc = true; | |
1852 | #endif | |
1853 | ||
6be26498 DB |
1854 | return 0; |
1855 | } | |
1856 | early_param("intel_pstate", intel_pstate_setup); | |
1857 | ||
93f0822d DB |
1858 | MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>"); |
1859 | MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors"); | |
1860 | MODULE_LICENSE("GPL"); |