[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / maple-cpufreq.c

/*
 *  Copyright (C) 2011 Dmitry Eremin-Solenikov
 *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
 * that is iMac G5 and latest single CPU desktop.
 */

#undef DEBUG

#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/init.h>
#include <linux/completion.h>
#include <linux/mutex.h>
#include <linux/time.h>
#include <linux/of_device.h>

#define DBG(fmt...) pr_debug(fmt)

/* see 970FX user manual */

#define SCOM_PCR 0x0aa001			/* PCR scom addr */

#define PCR_HILO_SELECT		0x80000000U	/* 1 = PCR, 0 = PCRH */
#define PCR_SPEED_FULL		0x00000000U	/* 1:1 speed value */
#define PCR_SPEED_HALF		0x00020000U	/* 1:2 speed value */
#define PCR_SPEED_QUARTER	0x00040000U	/* 1:4 speed value */
#define PCR_SPEED_MASK		0x000e0000U	/* speed mask */
#define PCR_SPEED_SHIFT		17
#define PCR_FREQ_REQ_VALID	0x00010000U	/* freq request valid */
#define PCR_VOLT_REQ_VALID	0x00008000U	/* volt request valid */
#define PCR_TARGET_TIME_MASK	0x00006000U	/* target time */
#define PCR_STATLAT_MASK	0x00001f00U	/* STATLAT value */
#define PCR_SNOOPLAT_MASK	0x000000f0U	/* SNOOPLAT value */
#define PCR_SNOOPACC_MASK	0x0000000fU	/* SNOOPACC value */

#define SCOM_PSR 0x408001			/* PSR scom addr */
/* warning: PSR is a 64 bits register */
#define PSR_CMD_RECEIVED	0x2000000000000000U   /* command received */
#define PSR_CMD_COMPLETED	0x1000000000000000U   /* command completed */
#define PSR_CUR_SPEED_MASK	0x0300000000000000U   /* current speed */
#define PSR_CUR_SPEED_SHIFT	(56)

/*
 * The G5 only supports two frequencies (Quarter speed is not supported)
 */
#define CPUFREQ_HIGH                  0
#define CPUFREQ_LOW                   1

static struct cpufreq_frequency_table maple_cpu_freqs[] = {
	{CPUFREQ_HIGH,		0},
	{CPUFREQ_LOW,		0},
	{0,			CPUFREQ_TABLE_END},
};

static struct freq_attr *maple_cpu_freqs_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	NULL,
};

/* Power mode data is an array of the 32 bits PCR values to use for
 * the various frequencies, retrieved from the device-tree
 */
static int maple_pmode_cur;

static DEFINE_MUTEX(maple_switch_mutex);

static const u32 *maple_pmode_data;
static int maple_pmode_max;

/*
 * SCOM based frequency switching for 970FX rev3
 */
static int maple_scom_switch_freq(int speed_mode)
{
	unsigned long flags;
	int to;

	local_irq_save(flags);

	/* Clear PCR high */
	scom970_write(SCOM_PCR, 0);
	/* Clear PCR low */
	scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
	/* Set PCR low */
	scom970_write(SCOM_PCR, PCR_HILO_SELECT |
		      maple_pmode_data[speed_mode]);

	/* Wait for completion */
	for (to = 0; to < 10; to++) {
		unsigned long psr = scom970_read(SCOM_PSR);

		if ((psr & PSR_CMD_RECEIVED) == 0 &&
		    (((psr >> PSR_CUR_SPEED_SHIFT) ^
		      (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
		    == 0)
			break;
		if (psr & PSR_CMD_COMPLETED)
			break;
		udelay(100);
	}

	local_irq_restore(flags);

	maple_pmode_cur = speed_mode;
	ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;

	return 0;
}

static int maple_scom_query_freq(void)
{
	unsigned long psr = scom970_read(SCOM_PSR);
	int i;

	for (i = 0; i <= maple_pmode_max; i++)
		if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
		      (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
			break;
	return i;
}

/*
 * Common interface to the cpufreq core
 */

static int maple_cpufreq_verify(struct cpufreq_policy *policy)
{
	return cpufreq_frequency_table_verify(policy, maple_cpu_freqs);
}

static int maple_cpufreq_target(struct cpufreq_policy *policy,
	unsigned int target_freq, unsigned int relation)
{
	unsigned int newstate = 0;
	struct cpufreq_freqs freqs;
	int rc;

	if (cpufreq_frequency_table_target(policy, maple_cpu_freqs,
			target_freq, relation, &newstate))
		return -EINVAL;

	if (maple_pmode_cur == newstate)
		return 0;

	mutex_lock(&maple_switch_mutex);

	freqs.old = maple_cpu_freqs[maple_pmode_cur].frequency;
	freqs.new = maple_cpu_freqs[newstate].frequency;

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
	rc = maple_scom_switch_freq(newstate);
	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	mutex_unlock(&maple_switch_mutex);

	return rc;
}

static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
{
	return maple_cpu_freqs[maple_pmode_cur].frequency;
}

static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	policy->cpuinfo.transition_latency = 12000;
	policy->cur = maple_cpu_freqs[maple_scom_query_freq()].frequency;
	/* secondary CPUs are tied to the primary one by the
	 * cpufreq core if in the secondary policy we tell it that
	 * it actually must be one policy together with all others. */
	cpumask_setall(policy->cpus);

	return cpufreq_table_validate_and_show(policy, maple_cpu_freqs);
}


static struct cpufreq_driver maple_cpufreq_driver = {
	.name		= "maple",
	.flags		= CPUFREQ_CONST_LOOPS,
	.init		= maple_cpufreq_cpu_init,
	.verify		= maple_cpufreq_verify,
	.target		= maple_cpufreq_target,
	.get		= maple_cpufreq_get_speed,
	.attr		= maple_cpu_freqs_attr,
};

static int __init maple_cpufreq_init(void)
{
	struct device_node *cpunode;
	unsigned int psize;
	unsigned long max_freq;
	const u32 *valp;
	u32 pvr_hi;
	int rc = -ENODEV;

	/*
	 * Behave here like powermac driver which checks machine compatibility
	 * to ease merging of two drivers in future.
	 */
	if (!of_machine_is_compatible("Momentum,Maple") &&
	    !of_machine_is_compatible("Momentum,Apache"))
		return 0;

	/* Get first CPU node */
	cpunode = of_cpu_device_node_get(0);
	if (cpunode == NULL) {
		printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
		goto bail_noprops;
	}

	/* Check 970FX for now */
	/* we actually don't care on which CPU to access PVR */
	pvr_hi = PVR_VER(mfspr(SPRN_PVR));
	if (pvr_hi != 0x3c && pvr_hi != 0x44) {
		printk(KERN_ERR "cpufreq: Unsupported CPU version (%x)\n",
				pvr_hi);
		goto bail_noprops;
	}

	/* Look for the powertune data in the device-tree */
	/*
	 * On Maple this property is provided by PIBS in dual-processor config,
	 * not provided by PIBS in CPU0 config and also not provided by SLOF,
	 * so YMMV
	 */
	maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
	if (!maple_pmode_data) {
		DBG("No power-mode-data !\n");
		goto bail_noprops;
	}
	maple_pmode_max = psize / sizeof(u32) - 1;

	/*
	 * From what I see, clock-frequency is always the maximal frequency.
	 * The current driver can not slew sysclk yet, so we really only deal
	 * with powertune steps for now. We also only implement full freq and
	 * half freq in this version. So far, I haven't yet seen a machine
	 * supporting anything else.
	 */
	valp = of_get_property(cpunode, "clock-frequency", NULL);
	if (!valp)
		return -ENODEV;
	max_freq = (*valp)/1000;
	maple_cpu_freqs[0].frequency = max_freq;
	maple_cpu_freqs[1].frequency = max_freq/2;

	/* Force apply current frequency to make sure everything is in
	 * sync (voltage is right for example). Firmware may leave us with
	 * a strange setting ...
	 */
	msleep(10);
	maple_pmode_cur = -1;
	maple_scom_switch_freq(maple_scom_query_freq());

	printk(KERN_INFO "Registering Maple CPU frequency driver\n");
	printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
		maple_cpu_freqs[1].frequency/1000,
		maple_cpu_freqs[0].frequency/1000,
		maple_cpu_freqs[maple_pmode_cur].frequency/1000);

	rc = cpufreq_register_driver(&maple_cpufreq_driver);

	of_node_put(cpunode);

	return rc;

bail_noprops:
	of_node_put(cpunode);

	return rc;
}

module_init(maple_cpufreq_init);


MODULE_LICENSE("GPL");
Commit	Line	Data
5d8c6658 DES	1	/*
	2	* Copyright (C) 2011 Dmitry Eremin-Solenikov
	3	* Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	4	* and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
	11	* that is iMac G5 and latest single CPU desktop.
	12	*/
	13
	14	#undef DEBUG
	15
	16	#include <linux/module.h>
	17	#include <linux/types.h>
	18	#include <linux/errno.h>
	19	#include <linux/kernel.h>
	20	#include <linux/delay.h>
	21	#include <linux/sched.h>
	22	#include <linux/cpufreq.h>
	23	#include <linux/init.h>
	24	#include <linux/completion.h>
	25	#include <linux/mutex.h>
	26	#include <linux/time.h>
2421d4c3	27	#include <linux/of_device.h>
5d8c6658 DES	28
	29	#define DBG(fmt...) pr_debug(fmt)
	30
	31	/* see 970FX user manual */
	32
	33	#define SCOM_PCR 0x0aa001 /* PCR scom addr */
	34
	35	#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
	36	#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
	37	#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
	38	#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
	39	#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
	40	#define PCR_SPEED_SHIFT 17
	41	#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
	42	#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
	43	#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
	44	#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
	45	#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
	46	#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
	47
	48	#define SCOM_PSR 0x408001 /* PSR scom addr */
	49	/* warning: PSR is a 64 bits register */
	50	#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
	51	#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
	52	#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
	53	#define PSR_CUR_SPEED_SHIFT (56)
	54
	55	/*
	56	* The G5 only supports two frequencies (Quarter speed is not supported)
	57	*/
	58	#define CPUFREQ_HIGH 0
	59	#define CPUFREQ_LOW 1
	60
	61	static struct cpufreq_frequency_table maple_cpu_freqs[] = {
	62	{CPUFREQ_HIGH, 0},
	63	{CPUFREQ_LOW, 0},
	64	{0, CPUFREQ_TABLE_END},
	65	};
	66
	67	static struct freq_attr *maple_cpu_freqs_attr[] = {
	68	&cpufreq_freq_attr_scaling_available_freqs,
	69	NULL,
	70	};
	71
	72	/* Power mode data is an array of the 32 bits PCR values to use for
	73	* the various frequencies, retrieved from the device-tree
	74	*/
	75	static int maple_pmode_cur;
	76
	77	static DEFINE_MUTEX(maple_switch_mutex);
	78
	79	static const u32 *maple_pmode_data;
	80	static int maple_pmode_max;
	81
	82	/*
	83	* SCOM based frequency switching for 970FX rev3
	84	*/
	85	static int maple_scom_switch_freq(int speed_mode)
	86	{
	87	unsigned long flags;
	88	int to;
	89
	90	local_irq_save(flags);
	91
92	/* Clear PCR high */
93	scom970_write(SCOM_PCR, 0);
94	/* Clear PCR low */
95	scom970_write(SCOM_PCR, PCR_HILO_SELECT \| 0);
96	/* Set PCR low */
97	scom970_write(SCOM_PCR, PCR_HILO_SELECT \|
98	maple_pmode_data[speed_mode]);
99
100	/* Wait for completion */
101	for (to = 0; to < 10; to++) {
102	unsigned long psr = scom970_read(SCOM_PSR);
103
104	if ((psr & PSR_CMD_RECEIVED) == 0 &&
105	(((psr >> PSR_CUR_SPEED_SHIFT) ^
106	(maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
107	== 0)
108	break;
109	if (psr & PSR_CMD_COMPLETED)
110	break;
111	udelay(100);
112	}
113
114	local_irq_restore(flags);
115
116	maple_pmode_cur = speed_mode;
117	ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
118
119	return 0;
120	}
121
122	static int maple_scom_query_freq(void)
123	{
124	unsigned long psr = scom970_read(SCOM_PSR);
125	int i;
126
127	for (i = 0; i <= maple_pmode_max; i++)
128	if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
129	(maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
130	break;
131	return i;
132	}
133
134	/*
135	* Common interface to the cpufreq core
136	*/
137
138	static int maple_cpufreq_verify(struct cpufreq_policy *policy)
139	{
140	return cpufreq_frequency_table_verify(policy, maple_cpu_freqs);
141	}
142
143	static int maple_cpufreq_target(struct cpufreq_policy *policy,
144	unsigned int target_freq, unsigned int relation)
145	{
146	unsigned int newstate = 0;
147	struct cpufreq_freqs freqs;
148	int rc;
149
150	if (cpufreq_frequency_table_target(policy, maple_cpu_freqs,
151	target_freq, relation, &newstate))
152	return -EINVAL;
153
154	if (maple_pmode_cur == newstate)
155	return 0;
156
157	mutex_lock(&maple_switch_mutex);
158
159	freqs.old = maple_cpu_freqs[maple_pmode_cur].frequency;
160	freqs.new = maple_cpu_freqs[newstate].frequency;
5d8c6658	161
b43a7ffb	162	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
5d8c6658	163	rc = maple_scom_switch_freq(newstate);
b43a7ffb	164	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
5d8c6658 DES	165
	166	mutex_unlock(&maple_switch_mutex);
	167
	168	return rc;
	169	}
	170
	171	static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
	172	{
	173	return maple_cpu_freqs[maple_pmode_cur].frequency;
	174	}
	175
	176	static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
	177	{
	178	policy->cpuinfo.transition_latency = 12000;
	179	policy->cur = maple_cpu_freqs[maple_scom_query_freq()].frequency;
	180	/* secondary CPUs are tied to the primary one by the
	181	* cpufreq core if in the secondary policy we tell it that
	182	* it actually must be one policy together with all others. */
4c738d00	183	cpumask_setall(policy->cpus);
5d8c6658	184
05b1621c	185	return cpufreq_table_validate_and_show(policy, maple_cpu_freqs);
5d8c6658 DES	186	}
	187
	188
	189	static struct cpufreq_driver maple_cpufreq_driver = {
	190	.name = "maple",
5d8c6658 DES	191	.flags = CPUFREQ_CONST_LOOPS,
	192	.init = maple_cpufreq_cpu_init,
	193	.verify = maple_cpufreq_verify,
	194	.target = maple_cpufreq_target,
	195	.get = maple_cpufreq_get_speed,
	196	.attr = maple_cpu_freqs_attr,
	197	};
	198
	199	static int __init maple_cpufreq_init(void)
	200	{
5d8c6658 DES	201	struct device_node *cpunode;
	202	unsigned int psize;
	203	unsigned long max_freq;
	204	const u32 *valp;
	205	u32 pvr_hi;
	206	int rc = -ENODEV;
	207
	208	/*
	209	* Behave here like powermac driver which checks machine compatibility
	210	* to ease merging of two drivers in future.
	211	*/
	212	if (!of_machine_is_compatible("Momentum,Maple") &&
	213	!of_machine_is_compatible("Momentum,Apache"))
	214	return 0;
	215
5d8c6658	216	/* Get first CPU node */
2421d4c3	217	cpunode = of_cpu_device_node_get(0);
5d8c6658 DES	218	if (cpunode == NULL) {
5d8c6658 DES	219	printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
2421d4c3	220	goto bail_noprops;
5d8c6658 DES	221	}
	222
	223	/* Check 970FX for now */
	224	/* we actually don't care on which CPU to access PVR */
	225	pvr_hi = PVR_VER(mfspr(SPRN_PVR));
	226	if (pvr_hi != 0x3c && pvr_hi != 0x44) {
	227	printk(KERN_ERR "cpufreq: Unsupported CPU version (%x)\n",
	228	pvr_hi);
	229	goto bail_noprops;
	230	}
	231
	232	/* Look for the powertune data in the device-tree */
	233	/*
	234	* On Maple this property is provided by PIBS in dual-processor config,
	235	* not provided by PIBS in CPU0 config and also not provided by SLOF,
	236	* so YMMV
	237	*/
	238	maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
	239	if (!maple_pmode_data) {
	240	DBG("No power-mode-data !\n");
	241	goto bail_noprops;
	242	}
	243	maple_pmode_max = psize / sizeof(u32) - 1;
	244
	245	/*
	246	* From what I see, clock-frequency is always the maximal frequency.
	247	* The current driver can not slew sysclk yet, so we really only deal
	248	* with powertune steps for now. We also only implement full freq and
	249	* half freq in this version. So far, I haven't yet seen a machine
	250	* supporting anything else.
	251	*/
	252	valp = of_get_property(cpunode, "clock-frequency", NULL);
	253	if (!valp)
	254	return -ENODEV;
	255	max_freq = (*valp)/1000;
	256	maple_cpu_freqs[0].frequency = max_freq;
	257	maple_cpu_freqs[1].frequency = max_freq/2;
	258
	259	/* Force apply current frequency to make sure everything is in
	260	* sync (voltage is right for example). Firmware may leave us with
	261	* a strange setting ...
	262	*/
	263	msleep(10);
	264	maple_pmode_cur = -1;
	265	maple_scom_switch_freq(maple_scom_query_freq());
	266
	267	printk(KERN_INFO "Registering Maple CPU frequency driver\n");
	268	printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
	269	maple_cpu_freqs[1].frequency/1000,
	270	maple_cpu_freqs[0].frequency/1000,
	271	maple_cpu_freqs[maple_pmode_cur].frequency/1000);
	272
	273	rc = cpufreq_register_driver(&maple_cpufreq_driver);
	274
	275	of_node_put(cpunode);
5d8c6658 DES	276
	277	return rc;
	278
	279	bail_noprops:
	280	of_node_put(cpunode);
5d8c6658 DES	281
	282	return rc;
	283	}
	284
	285	module_init(maple_cpufreq_init);
	286
	287
	288	MODULE_LICENSE("GPL");