]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/cpufreq/omap-cpufreq.c
Merge branch 'for-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / omap-cpufreq.c
CommitLineData
ec6bced6 1/*
ffe4f0f1 2 * CPU frequency scaling for OMAP using OPP information
ec6bced6
TL
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Written by Tony Lindgren <tony@atomide.com>
6 *
7 * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
8 *
731e0cc6
SS
9 * Copyright (C) 2007-2011 Texas Instruments, Inc.
10 * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
11 *
ec6bced6
TL
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16#include <linux/types.h>
17#include <linux/kernel.h>
18#include <linux/sched.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/init.h>
22#include <linux/err.h>
f8ce2547 23#include <linux/clk.h>
fced80c7 24#include <linux/io.h>
e4db1c74 25#include <linux/pm_opp.h>
46c12216 26#include <linux/cpu.h>
c1b547bc 27#include <linux/module.h>
49ded525 28#include <linux/platform_device.h>
53dfe8a8 29#include <linux/regulator/consumer.h>
ec6bced6 30
731e0cc6 31#include <asm/smp_plat.h>
46c12216 32#include <asm/cpu.h>
ec6bced6 33
42daffd2
AM
34/* OPP tolerance in percentage */
35#define OPP_TOLERANCE 4
36
731e0cc6 37static struct cpufreq_frequency_table *freq_table;
1c78217f 38static atomic_t freq_table_users = ATOMIC_INIT(0);
b8488fbe 39static struct clk *mpu_clk;
a820ffa8 40static struct device *mpu_dev;
53dfe8a8 41static struct regulator *mpu_reg;
b8488fbe 42
b0a330dc 43static unsigned int omap_getspeed(unsigned int cpu)
ec6bced6 44{
ec6bced6
TL
45 unsigned long rate;
46
46c12216 47 if (cpu >= NR_CPUS)
ec6bced6
TL
48 return 0;
49
ec6bced6 50 rate = clk_get_rate(mpu_clk) / 1000;
ec6bced6
TL
51 return rate;
52}
53
9c0ebcf7 54static int omap_target(struct cpufreq_policy *policy, unsigned int index)
ec6bced6 55{
696d0b2c 56 int r, ret;
47d43ba7 57 struct dev_pm_opp *opp;
42daffd2 58 unsigned long freq, volt = 0, volt_old = 0, tol = 0;
d4019f0a 59 unsigned int old_freq, new_freq;
ec6bced6 60
d4019f0a
VK
61 old_freq = omap_getspeed(policy->cpu);
62 new_freq = freq_table[index].frequency;
aeec2990 63
d4019f0a 64 freq = new_freq * 1000;
8df0a663
KH
65 ret = clk_round_rate(mpu_clk, freq);
66 if (IS_ERR_VALUE(ret)) {
67 dev_warn(mpu_dev,
68 "CPUfreq: Cannot find matching frequency for %lu\n",
69 freq);
70 return ret;
71 }
72 freq = ret;
53dfe8a8
KH
73
74 if (mpu_reg) {
f44d188a 75 rcu_read_lock();
5d4879cd 76 opp = dev_pm_opp_find_freq_ceil(mpu_dev, &freq);
53dfe8a8 77 if (IS_ERR(opp)) {
f44d188a 78 rcu_read_unlock();
53dfe8a8 79 dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
d4019f0a 80 __func__, new_freq);
53dfe8a8
KH
81 return -EINVAL;
82 }
5d4879cd 83 volt = dev_pm_opp_get_voltage(opp);
f44d188a 84 rcu_read_unlock();
42daffd2 85 tol = volt * OPP_TOLERANCE / 100;
53dfe8a8
KH
86 volt_old = regulator_get_voltage(mpu_reg);
87 }
88
89 dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n",
d4019f0a
VK
90 old_freq / 1000, volt_old ? volt_old / 1000 : -1,
91 new_freq / 1000, volt ? volt / 1000 : -1);
44a49a23 92
53dfe8a8 93 /* scaling up? scale voltage before frequency */
d4019f0a 94 if (mpu_reg && (new_freq > old_freq)) {
42daffd2 95 r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8
KH
96 if (r < 0) {
97 dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
98 __func__);
d4019f0a 99 return r;
53dfe8a8
KH
100 }
101 }
731e0cc6 102
d4019f0a 103 ret = clk_set_rate(mpu_clk, new_freq * 1000);
46c12216 104
53dfe8a8 105 /* scaling down? scale voltage after frequency */
d4019f0a 106 if (mpu_reg && (new_freq < old_freq)) {
42daffd2 107 r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8
KH
108 if (r < 0) {
109 dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
110 __func__);
d4019f0a
VK
111 clk_set_rate(mpu_clk, old_freq * 1000);
112 return r;
53dfe8a8
KH
113 }
114 }
115
ec6bced6
TL
116 return ret;
117}
118
1c78217f
NM
119static inline void freq_table_free(void)
120{
121 if (atomic_dec_and_test(&freq_table_users))
5d4879cd 122 dev_pm_opp_free_cpufreq_table(mpu_dev, &freq_table);
1c78217f
NM
123}
124
2760984f 125static int omap_cpu_init(struct cpufreq_policy *policy)
ec6bced6 126{
982bce11 127 int result;
731e0cc6 128
e2ee1b4d 129 mpu_clk = clk_get(NULL, "cpufreq_ck");
ec6bced6
TL
130 if (IS_ERR(mpu_clk))
131 return PTR_ERR(mpu_clk);
132
982bce11 133 if (!freq_table) {
5d4879cd 134 result = dev_pm_opp_init_cpufreq_table(mpu_dev, &freq_table);
982bce11
VK
135 if (result) {
136 dev_err(mpu_dev,
137 "%s: cpu%d: failed creating freq table[%d]\n",
bf2a359d 138 __func__, policy->cpu, result);
982bce11
VK
139 goto fail;
140 }
aeec2990
KH
141 }
142
1b865214
RN
143 atomic_inc_return(&freq_table_users);
144
aeec2990 145 /* FIXME: what's the actual transition time? */
982bce11
VK
146 result = cpufreq_generic_init(policy, freq_table, 300 * 1000);
147 if (!result)
148 return 0;
11e04fdd 149
1c78217f 150 freq_table_free();
982bce11 151fail:
11e04fdd
NM
152 clk_put(mpu_clk);
153 return result;
ec6bced6
TL
154}
155
b8488fbe
HD
156static int omap_cpu_exit(struct cpufreq_policy *policy)
157{
42a4df00 158 cpufreq_frequency_table_put_attr(policy->cpu);
1c78217f 159 freq_table_free();
b8488fbe
HD
160 clk_put(mpu_clk);
161 return 0;
162}
163
ec6bced6
TL
164static struct cpufreq_driver omap_driver = {
165 .flags = CPUFREQ_STICKY,
d5ca1649 166 .verify = cpufreq_generic_frequency_table_verify,
9c0ebcf7 167 .target_index = omap_target,
ec6bced6
TL
168 .get = omap_getspeed,
169 .init = omap_cpu_init,
b8488fbe 170 .exit = omap_cpu_exit,
ec6bced6 171 .name = "omap",
d5ca1649 172 .attr = cpufreq_generic_attr,
ec6bced6
TL
173};
174
49ded525 175static int omap_cpufreq_probe(struct platform_device *pdev)
ec6bced6 176{
747a7f64
KH
177 mpu_dev = get_cpu_device(0);
178 if (!mpu_dev) {
a820ffa8 179 pr_warning("%s: unable to get the mpu device\n", __func__);
747a7f64 180 return -EINVAL;
a820ffa8
NM
181 }
182
53dfe8a8
KH
183 mpu_reg = regulator_get(mpu_dev, "vcc");
184 if (IS_ERR(mpu_reg)) {
185 pr_warning("%s: unable to get MPU regulator\n", __func__);
186 mpu_reg = NULL;
187 } else {
188 /*
189 * Ensure physical regulator is present.
190 * (e.g. could be dummy regulator.)
191 */
192 if (regulator_get_voltage(mpu_reg) < 0) {
193 pr_warn("%s: physical regulator not present for MPU\n",
194 __func__);
195 regulator_put(mpu_reg);
196 mpu_reg = NULL;
197 }
198 }
199
ec6bced6
TL
200 return cpufreq_register_driver(&omap_driver);
201}
202
49ded525 203static int omap_cpufreq_remove(struct platform_device *pdev)
731e0cc6 204{
49ded525 205 return cpufreq_unregister_driver(&omap_driver);
731e0cc6 206}
aeec2990 207
49ded525
NM
208static struct platform_driver omap_cpufreq_platdrv = {
209 .driver = {
210 .name = "omap-cpufreq",
211 .owner = THIS_MODULE,
212 },
213 .probe = omap_cpufreq_probe,
214 .remove = omap_cpufreq_remove,
215};
216module_platform_driver(omap_cpufreq_platdrv);
217
731e0cc6
SS
218MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
219MODULE_LICENSE("GPL");