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Commit | Line | Data |
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ec6bced6 | 1 | /* |
ffe4f0f1 | 2 | * CPU frequency scaling for OMAP using OPP information |
ec6bced6 TL |
3 | * |
4 | * Copyright (C) 2005 Nokia Corporation | |
5 | * Written by Tony Lindgren <tony@atomide.com> | |
6 | * | |
7 | * Based on cpu-sa1110.c, Copyright (C) 2001 Russell King | |
8 | * | |
731e0cc6 SS |
9 | * Copyright (C) 2007-2011 Texas Instruments, Inc. |
10 | * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar | |
11 | * | |
ec6bced6 TL |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | #include <linux/types.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/sched.h> | |
19 | #include <linux/cpufreq.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/err.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
731e0cc6 | 25 | #include <linux/opp.h> |
46c12216 | 26 | #include <linux/cpu.h> |
c1b547bc | 27 | #include <linux/module.h> |
53dfe8a8 | 28 | #include <linux/regulator/consumer.h> |
ec6bced6 | 29 | |
731e0cc6 | 30 | #include <asm/smp_plat.h> |
46c12216 | 31 | #include <asm/cpu.h> |
ec6bced6 | 32 | |
731e0cc6 SS |
33 | #include <plat/clock.h> |
34 | #include <plat/omap-pm.h> | |
35 | #include <plat/common.h> | |
c1b547bc | 36 | #include <plat/omap_device.h> |
a7ca9d2b | 37 | |
731e0cc6 | 38 | #include <mach/hardware.h> |
aeec2990 | 39 | |
42daffd2 AM |
40 | /* OPP tolerance in percentage */ |
41 | #define OPP_TOLERANCE 4 | |
42 | ||
731e0cc6 | 43 | static struct cpufreq_frequency_table *freq_table; |
1c78217f | 44 | static atomic_t freq_table_users = ATOMIC_INIT(0); |
b8488fbe | 45 | static struct clk *mpu_clk; |
08ca3e3b | 46 | static char *mpu_clk_name; |
a820ffa8 | 47 | static struct device *mpu_dev; |
53dfe8a8 | 48 | static struct regulator *mpu_reg; |
b8488fbe | 49 | |
b0a330dc | 50 | static int omap_verify_speed(struct cpufreq_policy *policy) |
ec6bced6 | 51 | { |
bf2a359d | 52 | if (!freq_table) |
ec6bced6 | 53 | return -EINVAL; |
bf2a359d | 54 | return cpufreq_frequency_table_verify(policy, freq_table); |
ec6bced6 TL |
55 | } |
56 | ||
b0a330dc | 57 | static unsigned int omap_getspeed(unsigned int cpu) |
ec6bced6 | 58 | { |
ec6bced6 TL |
59 | unsigned long rate; |
60 | ||
46c12216 | 61 | if (cpu >= NR_CPUS) |
ec6bced6 TL |
62 | return 0; |
63 | ||
ec6bced6 | 64 | rate = clk_get_rate(mpu_clk) / 1000; |
ec6bced6 TL |
65 | return rate; |
66 | } | |
67 | ||
68 | static int omap_target(struct cpufreq_policy *policy, | |
69 | unsigned int target_freq, | |
70 | unsigned int relation) | |
71 | { | |
bf2a359d | 72 | unsigned int i; |
53dfe8a8 | 73 | int r, ret = 0; |
731e0cc6 | 74 | struct cpufreq_freqs freqs; |
53dfe8a8 | 75 | struct opp *opp; |
42daffd2 | 76 | unsigned long freq, volt = 0, volt_old = 0, tol = 0; |
ec6bced6 | 77 | |
bf2a359d NM |
78 | if (!freq_table) { |
79 | dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__, | |
80 | policy->cpu); | |
81 | return -EINVAL; | |
82 | } | |
83 | ||
84 | ret = cpufreq_frequency_table_target(policy, freq_table, target_freq, | |
85 | relation, &i); | |
86 | if (ret) { | |
87 | dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n", | |
88 | __func__, policy->cpu, target_freq, ret); | |
89 | return ret; | |
90 | } | |
91 | freqs.new = freq_table[i].frequency; | |
92 | if (!freqs.new) { | |
93 | dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__, | |
94 | policy->cpu, target_freq); | |
95 | return -EINVAL; | |
96 | } | |
aeec2990 | 97 | |
46c12216 | 98 | freqs.old = omap_getspeed(policy->cpu); |
46c12216 | 99 | freqs.cpu = policy->cpu; |
ec6bced6 | 100 | |
022ac03b | 101 | if (freqs.old == freqs.new && policy->cur == freqs.new) |
aeec2990 KH |
102 | return ret; |
103 | ||
46c12216 RK |
104 | /* notifiers */ |
105 | for_each_cpu(i, policy->cpus) { | |
106 | freqs.cpu = i; | |
107 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
108 | } | |
731e0cc6 | 109 | |
53dfe8a8 KH |
110 | freq = freqs.new * 1000; |
111 | ||
112 | if (mpu_reg) { | |
113 | opp = opp_find_freq_ceil(mpu_dev, &freq); | |
114 | if (IS_ERR(opp)) { | |
115 | dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n", | |
116 | __func__, freqs.new); | |
117 | return -EINVAL; | |
118 | } | |
119 | volt = opp_get_voltage(opp); | |
42daffd2 | 120 | tol = volt * OPP_TOLERANCE / 100; |
53dfe8a8 KH |
121 | volt_old = regulator_get_voltage(mpu_reg); |
122 | } | |
123 | ||
124 | dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", | |
125 | freqs.old / 1000, volt_old ? volt_old / 1000 : -1, | |
126 | freqs.new / 1000, volt ? volt / 1000 : -1); | |
127 | ||
128 | /* scaling up? scale voltage before frequency */ | |
129 | if (mpu_reg && (freqs.new > freqs.old)) { | |
42daffd2 | 130 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
131 | if (r < 0) { |
132 | dev_warn(mpu_dev, "%s: unable to scale voltage up.\n", | |
133 | __func__); | |
134 | freqs.new = freqs.old; | |
135 | goto done; | |
136 | } | |
137 | } | |
731e0cc6 | 138 | |
aeec2990 | 139 | ret = clk_set_rate(mpu_clk, freqs.new * 1000); |
46c12216 | 140 | |
53dfe8a8 KH |
141 | /* scaling down? scale voltage after frequency */ |
142 | if (mpu_reg && (freqs.new < freqs.old)) { | |
42daffd2 | 143 | r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol); |
53dfe8a8 KH |
144 | if (r < 0) { |
145 | dev_warn(mpu_dev, "%s: unable to scale voltage down.\n", | |
146 | __func__); | |
147 | ret = clk_set_rate(mpu_clk, freqs.old * 1000); | |
148 | freqs.new = freqs.old; | |
149 | goto done; | |
150 | } | |
151 | } | |
152 | ||
153 | freqs.new = omap_getspeed(policy->cpu); | |
46c12216 | 154 | |
53dfe8a8 | 155 | done: |
46c12216 RK |
156 | /* notifiers */ |
157 | for_each_cpu(i, policy->cpus) { | |
158 | freqs.cpu = i; | |
159 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
160 | } | |
ec6bced6 TL |
161 | |
162 | return ret; | |
163 | } | |
164 | ||
1c78217f NM |
165 | static inline void freq_table_free(void) |
166 | { | |
167 | if (atomic_dec_and_test(&freq_table_users)) | |
168 | opp_free_cpufreq_table(mpu_dev, &freq_table); | |
169 | } | |
170 | ||
790ab7e9 | 171 | static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy) |
ec6bced6 | 172 | { |
aeec2990 | 173 | int result = 0; |
731e0cc6 | 174 | |
08ca3e3b | 175 | mpu_clk = clk_get(NULL, mpu_clk_name); |
ec6bced6 TL |
176 | if (IS_ERR(mpu_clk)) |
177 | return PTR_ERR(mpu_clk); | |
178 | ||
11e04fdd NM |
179 | if (policy->cpu >= NR_CPUS) { |
180 | result = -EINVAL; | |
181 | goto fail_ck; | |
182 | } | |
aeec2990 | 183 | |
46c12216 | 184 | policy->cur = policy->min = policy->max = omap_getspeed(policy->cpu); |
1c78217f | 185 | |
1b865214 | 186 | if (!freq_table) |
1c78217f | 187 | result = opp_init_cpufreq_table(mpu_dev, &freq_table); |
bf2a359d NM |
188 | |
189 | if (result) { | |
190 | dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n", | |
191 | __func__, policy->cpu, result); | |
11e04fdd | 192 | goto fail_ck; |
aeec2990 KH |
193 | } |
194 | ||
1b865214 RN |
195 | atomic_inc_return(&freq_table_users); |
196 | ||
bf2a359d | 197 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); |
1c78217f NM |
198 | if (result) |
199 | goto fail_table; | |
200 | ||
201 | cpufreq_frequency_table_get_attr(freq_table, policy->cpu); | |
bf2a359d | 202 | |
731e0cc6 SS |
203 | policy->min = policy->cpuinfo.min_freq; |
204 | policy->max = policy->cpuinfo.max_freq; | |
46c12216 RK |
205 | policy->cur = omap_getspeed(policy->cpu); |
206 | ||
207 | /* | |
208 | * On OMAP SMP configuartion, both processors share the voltage | |
209 | * and clock. So both CPUs needs to be scaled together and hence | |
210 | * needs software co-ordination. Use cpufreq affected_cpus | |
211 | * interface to handle this scenario. Additional is_smp() check | |
212 | * is to keep SMP_ON_UP build working. | |
213 | */ | |
214 | if (is_smp()) { | |
215 | policy->shared_type = CPUFREQ_SHARED_TYPE_ANY; | |
ed8ce00c | 216 | cpumask_setall(policy->cpus); |
46c12216 | 217 | } |
731e0cc6 | 218 | |
aeec2990 | 219 | /* FIXME: what's the actual transition time? */ |
b029839c | 220 | policy->cpuinfo.transition_latency = 300 * 1000; |
ec6bced6 TL |
221 | |
222 | return 0; | |
11e04fdd | 223 | |
1c78217f NM |
224 | fail_table: |
225 | freq_table_free(); | |
11e04fdd NM |
226 | fail_ck: |
227 | clk_put(mpu_clk); | |
228 | return result; | |
ec6bced6 TL |
229 | } |
230 | ||
b8488fbe HD |
231 | static int omap_cpu_exit(struct cpufreq_policy *policy) |
232 | { | |
1c78217f | 233 | freq_table_free(); |
b8488fbe HD |
234 | clk_put(mpu_clk); |
235 | return 0; | |
236 | } | |
237 | ||
aeec2990 KH |
238 | static struct freq_attr *omap_cpufreq_attr[] = { |
239 | &cpufreq_freq_attr_scaling_available_freqs, | |
240 | NULL, | |
241 | }; | |
242 | ||
ec6bced6 TL |
243 | static struct cpufreq_driver omap_driver = { |
244 | .flags = CPUFREQ_STICKY, | |
245 | .verify = omap_verify_speed, | |
246 | .target = omap_target, | |
247 | .get = omap_getspeed, | |
248 | .init = omap_cpu_init, | |
b8488fbe | 249 | .exit = omap_cpu_exit, |
ec6bced6 | 250 | .name = "omap", |
aeec2990 | 251 | .attr = omap_cpufreq_attr, |
ec6bced6 TL |
252 | }; |
253 | ||
254 | static int __init omap_cpufreq_init(void) | |
255 | { | |
08ca3e3b NM |
256 | if (cpu_is_omap24xx()) |
257 | mpu_clk_name = "virt_prcm_set"; | |
258 | else if (cpu_is_omap34xx()) | |
259 | mpu_clk_name = "dpll1_ck"; | |
260 | else if (cpu_is_omap44xx()) | |
261 | mpu_clk_name = "dpll_mpu_ck"; | |
262 | ||
263 | if (!mpu_clk_name) { | |
264 | pr_err("%s: unsupported Silicon?\n", __func__); | |
265 | return -EINVAL; | |
266 | } | |
a820ffa8 | 267 | |
c1b547bc | 268 | mpu_dev = omap_device_get_by_hwmod_name("mpu"); |
1bae9958 | 269 | if (IS_ERR(mpu_dev)) { |
a820ffa8 | 270 | pr_warning("%s: unable to get the mpu device\n", __func__); |
1bae9958 | 271 | return PTR_ERR(mpu_dev); |
a820ffa8 NM |
272 | } |
273 | ||
53dfe8a8 KH |
274 | mpu_reg = regulator_get(mpu_dev, "vcc"); |
275 | if (IS_ERR(mpu_reg)) { | |
276 | pr_warning("%s: unable to get MPU regulator\n", __func__); | |
277 | mpu_reg = NULL; | |
278 | } else { | |
279 | /* | |
280 | * Ensure physical regulator is present. | |
281 | * (e.g. could be dummy regulator.) | |
282 | */ | |
283 | if (regulator_get_voltage(mpu_reg) < 0) { | |
284 | pr_warn("%s: physical regulator not present for MPU\n", | |
285 | __func__); | |
286 | regulator_put(mpu_reg); | |
287 | mpu_reg = NULL; | |
288 | } | |
289 | } | |
290 | ||
ec6bced6 TL |
291 | return cpufreq_register_driver(&omap_driver); |
292 | } | |
293 | ||
731e0cc6 SS |
294 | static void __exit omap_cpufreq_exit(void) |
295 | { | |
296 | cpufreq_unregister_driver(&omap_driver); | |
297 | } | |
aeec2990 | 298 | |
731e0cc6 SS |
299 | MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs"); |
300 | MODULE_LICENSE("GPL"); | |
301 | module_init(omap_cpufreq_init); | |
302 | module_exit(omap_cpufreq_exit); |