[mirror_ubuntu-bionic-kernel.git] / drivers / cpufreq / omap-cpufreq.c

/*
 *  CPU frequency scaling for OMAP using OPP information
 *
 *  Copyright (C) 2005 Nokia Corporation
 *  Written by Tony Lindgren <tony@atomide.com>
 *
 *  Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
 *
 * Copyright (C) 2007-2011 Texas Instruments, Inc.
 * - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/cpufreq.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/opp.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>

#include <asm/smp_plat.h>
#include <asm/cpu.h>

/* OPP tolerance in percentage */
#define	OPP_TOLERANCE	4

static struct cpufreq_frequency_table *freq_table;
static atomic_t freq_table_users = ATOMIC_INIT(0);
static struct clk *mpu_clk;
static struct device *mpu_dev;
static struct regulator *mpu_reg;

static unsigned int omap_getspeed(unsigned int cpu)
{
	unsigned long rate;

	if (cpu >= NR_CPUS)
		return 0;

	rate = clk_get_rate(mpu_clk) / 1000;
	return rate;
}

static int omap_target(struct cpufreq_policy *policy,
		       unsigned int target_freq,
		       unsigned int relation)
{
	unsigned int i;
	int r, ret = 0;
	struct cpufreq_freqs freqs;
	struct opp *opp;
	unsigned long freq, volt = 0, volt_old = 0, tol = 0;

	if (!freq_table) {
		dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
				policy->cpu);
		return -EINVAL;
	}

	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
			relation, &i);
	if (ret) {
		dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
			__func__, policy->cpu, target_freq, ret);
		return ret;
	}
	freqs.new = freq_table[i].frequency;
	if (!freqs.new) {
		dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
			policy->cpu, target_freq);
		return -EINVAL;
	}

	freqs.old = omap_getspeed(policy->cpu);

	if (freqs.old == freqs.new && policy->cur == freqs.new)
		return ret;

	freq = freqs.new * 1000;
	ret = clk_round_rate(mpu_clk, freq);
	if (IS_ERR_VALUE(ret)) {
		dev_warn(mpu_dev,
			 "CPUfreq: Cannot find matching frequency for %lu\n",
			 freq);
		return ret;
	}
	freq = ret;

	if (mpu_reg) {
		rcu_read_lock();
		opp = opp_find_freq_ceil(mpu_dev, &freq);
		if (IS_ERR(opp)) {
			rcu_read_unlock();
			dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
				__func__, freqs.new);
			return -EINVAL;
		}
		volt = opp_get_voltage(opp);
		rcu_read_unlock();
		tol = volt * OPP_TOLERANCE / 100;
		volt_old = regulator_get_voltage(mpu_reg);
	}

	dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n", 
		freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
		freqs.new / 1000, volt ? volt / 1000 : -1);

	/* notifiers */
	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	/* scaling up?  scale voltage before frequency */
	if (mpu_reg && (freqs.new > freqs.old)) {
		r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
		if (r < 0) {
			dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
				 __func__);
			freqs.new = freqs.old;
			goto done;
		}
	}

	ret = clk_set_rate(mpu_clk, freqs.new * 1000);

	/* scaling down?  scale voltage after frequency */
	if (mpu_reg && (freqs.new < freqs.old)) {
		r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
		if (r < 0) {
			dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
				 __func__);
			ret = clk_set_rate(mpu_clk, freqs.old * 1000);
			freqs.new = freqs.old;
			goto done;
		}
	}

	freqs.new = omap_getspeed(policy->cpu);

done:
	/* notifiers */
	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return ret;
}

static inline void freq_table_free(void)
{
	if (atomic_dec_and_test(&freq_table_users))
		opp_free_cpufreq_table(mpu_dev, &freq_table);
}

static int omap_cpu_init(struct cpufreq_policy *policy)
{
	int result = 0;

	mpu_clk = clk_get(NULL, "cpufreq_ck");
	if (IS_ERR(mpu_clk))
		return PTR_ERR(mpu_clk);

	if (policy->cpu >= NR_CPUS) {
		result = -EINVAL;
		goto fail_ck;
	}

	if (!freq_table)
		result = opp_init_cpufreq_table(mpu_dev, &freq_table);

	if (result) {
		dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
				__func__, policy->cpu, result);
		goto fail_ck;
	}

	atomic_inc_return(&freq_table_users);

	result = cpufreq_table_validate_and_show(policy, freq_table);
	if (result)
		goto fail_table;

	/*
	 * On OMAP SMP configuartion, both processors share the voltage
	 * and clock. So both CPUs needs to be scaled together and hence
	 * needs software co-ordination. Use cpufreq affected_cpus
	 * interface to handle this scenario. Additional is_smp() check
	 * is to keep SMP_ON_UP build working.
	 */
	if (is_smp())
		cpumask_setall(policy->cpus);

	/* FIXME: what's the actual transition time? */
	policy->cpuinfo.transition_latency = 300 * 1000;

	return 0;

fail_table:
	freq_table_free();
fail_ck:
	clk_put(mpu_clk);
	return result;
}

static int omap_cpu_exit(struct cpufreq_policy *policy)
{
	cpufreq_frequency_table_put_attr(policy->cpu);
	freq_table_free();
	clk_put(mpu_clk);
	return 0;
}

static struct cpufreq_driver omap_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target		= omap_target,
	.get		= omap_getspeed,
	.init		= omap_cpu_init,
	.exit		= omap_cpu_exit,
	.name		= "omap",
	.attr		= cpufreq_generic_attr,
};

static int omap_cpufreq_probe(struct platform_device *pdev)
{
	mpu_dev = get_cpu_device(0);
	if (!mpu_dev) {
		pr_warning("%s: unable to get the mpu device\n", __func__);
		return -EINVAL;
	}

	mpu_reg = regulator_get(mpu_dev, "vcc");
	if (IS_ERR(mpu_reg)) {
		pr_warning("%s: unable to get MPU regulator\n", __func__);
		mpu_reg = NULL;
	} else {
		/* 
		 * Ensure physical regulator is present.
		 * (e.g. could be dummy regulator.)
		 */
		if (regulator_get_voltage(mpu_reg) < 0) {
			pr_warn("%s: physical regulator not present for MPU\n",
				__func__);
			regulator_put(mpu_reg);
			mpu_reg = NULL;
		}
	}

	return cpufreq_register_driver(&omap_driver);
}

static int omap_cpufreq_remove(struct platform_device *pdev)
{
	return cpufreq_unregister_driver(&omap_driver);
}

static struct platform_driver omap_cpufreq_platdrv = {
	.driver = {
		.name	= "omap-cpufreq",
		.owner	= THIS_MODULE,
	},
	.probe		= omap_cpufreq_probe,
	.remove		= omap_cpufreq_remove,
};
module_platform_driver(omap_cpufreq_platdrv);

MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
MODULE_LICENSE("GPL");
Commit	Line	Data
ec6bced6	1	/*
ffe4f0f1	2	* CPU frequency scaling for OMAP using OPP information
ec6bced6 TL	3	*
	4	* Copyright (C) 2005 Nokia Corporation
	5	* Written by Tony Lindgren <tony@atomide.com>
	6	*
	7	* Based on cpu-sa1110.c, Copyright (C) 2001 Russell King
	8	*
731e0cc6 SS	9	* Copyright (C) 2007-2011 Texas Instruments, Inc.
	10	* - OMAP3/4 support by Rajendra Nayak, Santosh Shilimkar
	11	*
ec6bced6 TL	12	* This program is free software; you can redistribute it and/or modify
	13	* it under the terms of the GNU General Public License version 2 as
	14	* published by the Free Software Foundation.
	15	*/
	16	#include <linux/types.h>
	17	#include <linux/kernel.h>
	18	#include <linux/sched.h>
	19	#include <linux/cpufreq.h>
	20	#include <linux/delay.h>
	21	#include <linux/init.h>
	22	#include <linux/err.h>
f8ce2547	23	#include <linux/clk.h>
fced80c7	24	#include <linux/io.h>
731e0cc6	25	#include <linux/opp.h>
46c12216	26	#include <linux/cpu.h>
c1b547bc	27	#include <linux/module.h>
49ded525	28	#include <linux/platform_device.h>
53dfe8a8	29	#include <linux/regulator/consumer.h>
ec6bced6	30
731e0cc6	31	#include <asm/smp_plat.h>
46c12216	32	#include <asm/cpu.h>
ec6bced6	33
42daffd2 AM	34	/* OPP tolerance in percentage */
	35	#define OPP_TOLERANCE 4
	36
731e0cc6	37	static struct cpufreq_frequency_table *freq_table;
1c78217f	38	static atomic_t freq_table_users = ATOMIC_INIT(0);
b8488fbe	39	static struct clk *mpu_clk;
a820ffa8	40	static struct device *mpu_dev;
53dfe8a8	41	static struct regulator *mpu_reg;
b8488fbe	42
b0a330dc	43	static unsigned int omap_getspeed(unsigned int cpu)
ec6bced6	44	{
ec6bced6 TL	45	unsigned long rate;
ec6bced6 TL	46
46c12216	47	if (cpu >= NR_CPUS)
ec6bced6 TL	48	return 0;
ec6bced6 TL	49
ec6bced6	50	rate = clk_get_rate(mpu_clk) / 1000;
ec6bced6 TL	51	return rate;
	52	}
	53
	54	static int omap_target(struct cpufreq_policy *policy,
	55	unsigned int target_freq,
	56	unsigned int relation)
	57	{
bf2a359d	58	unsigned int i;
53dfe8a8	59	int r, ret = 0;
731e0cc6	60	struct cpufreq_freqs freqs;
53dfe8a8	61	struct opp *opp;
42daffd2	62	unsigned long freq, volt = 0, volt_old = 0, tol = 0;
ec6bced6	63
bf2a359d NM	64	if (!freq_table) {
	65	dev_err(mpu_dev, "%s: cpu%d: no freq table!\n", __func__,
	66	policy->cpu);
	67	return -EINVAL;
	68	}
	69
	70	ret = cpufreq_frequency_table_target(policy, freq_table, target_freq,
	71	relation, &i);
	72	if (ret) {
	73	dev_dbg(mpu_dev, "%s: cpu%d: no freq match for %d(ret=%d)\n",
	74	__func__, policy->cpu, target_freq, ret);
	75	return ret;
	76	}
	77	freqs.new = freq_table[i].frequency;
	78	if (!freqs.new) {
	79	dev_err(mpu_dev, "%s: cpu%d: no match for freq %d\n", __func__,
	80	policy->cpu, target_freq);
	81	return -EINVAL;
	82	}
aeec2990	83
46c12216	84	freqs.old = omap_getspeed(policy->cpu);
ec6bced6	85
022ac03b	86	if (freqs.old == freqs.new && policy->cur == freqs.new)
aeec2990 KH	87	return ret;
aeec2990 KH	88
53dfe8a8	89	freq = freqs.new * 1000;
8df0a663 KH	90	ret = clk_round_rate(mpu_clk, freq);
	91	if (IS_ERR_VALUE(ret)) {
	92	dev_warn(mpu_dev,
	93	"CPUfreq: Cannot find matching frequency for %lu\n",
	94	freq);
	95	return ret;
	96	}
	97	freq = ret;
53dfe8a8 KH	98
53dfe8a8 KH	99	if (mpu_reg) {
f44d188a	100	rcu_read_lock();
53dfe8a8 KH	101	opp = opp_find_freq_ceil(mpu_dev, &freq);
53dfe8a8 KH	102	if (IS_ERR(opp)) {
f44d188a	103	rcu_read_unlock();
53dfe8a8 KH	104	dev_err(mpu_dev, "%s: unable to find MPU OPP for %d\n",
	105	__func__, freqs.new);
	106	return -EINVAL;
	107	}
	108	volt = opp_get_voltage(opp);
f44d188a	109	rcu_read_unlock();
42daffd2	110	tol = volt * OPP_TOLERANCE / 100;
53dfe8a8 KH	111	volt_old = regulator_get_voltage(mpu_reg);
	112	}
	113
	114	dev_dbg(mpu_dev, "cpufreq-omap: %u MHz, %ld mV --> %u MHz, %ld mV\n",
	115	freqs.old / 1000, volt_old ? volt_old / 1000 : -1,
	116	freqs.new / 1000, volt ? volt / 1000 : -1);
	117
44a49a23 VK	118	/* notifiers */
	119	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
	120
53dfe8a8 KH	121	/* scaling up? scale voltage before frequency */
53dfe8a8 KH	122	if (mpu_reg && (freqs.new > freqs.old)) {
42daffd2	123	r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8 KH	124	if (r < 0) {
	125	dev_warn(mpu_dev, "%s: unable to scale voltage up.\n",
	126	__func__);
	127	freqs.new = freqs.old;
	128	goto done;
	129	}
	130	}
731e0cc6	131
aeec2990	132	ret = clk_set_rate(mpu_clk, freqs.new * 1000);
46c12216	133
53dfe8a8 KH	134	/* scaling down? scale voltage after frequency */
53dfe8a8 KH	135	if (mpu_reg && (freqs.new < freqs.old)) {
42daffd2	136	r = regulator_set_voltage(mpu_reg, volt - tol, volt + tol);
53dfe8a8 KH	137	if (r < 0) {
	138	dev_warn(mpu_dev, "%s: unable to scale voltage down.\n",
	139	__func__);
	140	ret = clk_set_rate(mpu_clk, freqs.old * 1000);
	141	freqs.new = freqs.old;
	142	goto done;
	143	}
	144	}
	145
	146	freqs.new = omap_getspeed(policy->cpu);
46c12216	147
53dfe8a8	148	done:
46c12216	149	/* notifiers */
b43a7ffb	150	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
ec6bced6 TL	151
	152	return ret;
	153	}
	154
1c78217f NM	155	static inline void freq_table_free(void)
	156	{
	157	if (atomic_dec_and_test(&freq_table_users))
	158	opp_free_cpufreq_table(mpu_dev, &freq_table);
	159	}
	160
2760984f	161	static int omap_cpu_init(struct cpufreq_policy *policy)
ec6bced6	162	{
aeec2990	163	int result = 0;
731e0cc6	164
e2ee1b4d	165	mpu_clk = clk_get(NULL, "cpufreq_ck");
ec6bced6 TL	166	if (IS_ERR(mpu_clk))
	167	return PTR_ERR(mpu_clk);
	168
11e04fdd NM	169	if (policy->cpu >= NR_CPUS) {
	170	result = -EINVAL;
	171	goto fail_ck;
	172	}
aeec2990	173
1b865214	174	if (!freq_table)
1c78217f	175	result = opp_init_cpufreq_table(mpu_dev, &freq_table);
bf2a359d NM	176
	177	if (result) {
	178	dev_err(mpu_dev, "%s: cpu%d: failed creating freq table[%d]\n",
	179	__func__, policy->cpu, result);
11e04fdd	180	goto fail_ck;
aeec2990 KH	181	}
aeec2990 KH	182
1b865214 RN	183	atomic_inc_return(&freq_table_users);
1b865214 RN	184
aca71cf0	185	result = cpufreq_table_validate_and_show(policy, freq_table);
1c78217f NM	186	if (result)
	187	goto fail_table;
	188
46c12216 RK	189	/*
	190	* On OMAP SMP configuartion, both processors share the voltage
	191	* and clock. So both CPUs needs to be scaled together and hence
	192	* needs software co-ordination. Use cpufreq affected_cpus
	193	* interface to handle this scenario. Additional is_smp() check
	194	* is to keep SMP_ON_UP build working.
	195	*/
62b36cc1	196	if (is_smp())
ed8ce00c	197	cpumask_setall(policy->cpus);
731e0cc6	198
aeec2990	199	/* FIXME: what's the actual transition time? */
b029839c	200	policy->cpuinfo.transition_latency = 300 * 1000;
ec6bced6 TL	201
ec6bced6 TL	202	return 0;
11e04fdd	203
1c78217f NM	204	fail_table:
1c78217f NM	205	freq_table_free();
11e04fdd NM	206	fail_ck:
	207	clk_put(mpu_clk);
	208	return result;
ec6bced6 TL	209	}
ec6bced6 TL	210
b8488fbe HD	211	static int omap_cpu_exit(struct cpufreq_policy *policy)
b8488fbe HD	212	{
42a4df00	213	cpufreq_frequency_table_put_attr(policy->cpu);
1c78217f	214	freq_table_free();
b8488fbe HD	215	clk_put(mpu_clk);
	216	return 0;
	217	}
	218
ec6bced6 TL	219	static struct cpufreq_driver omap_driver = {
ec6bced6 TL	220	.flags = CPUFREQ_STICKY,
d5ca1649	221	.verify = cpufreq_generic_frequency_table_verify,
ec6bced6 TL	222	.target = omap_target,
	223	.get = omap_getspeed,
	224	.init = omap_cpu_init,
b8488fbe	225	.exit = omap_cpu_exit,
ec6bced6	226	.name = "omap",
d5ca1649	227	.attr = cpufreq_generic_attr,
ec6bced6 TL	228	};
ec6bced6 TL	229
49ded525	230	static int omap_cpufreq_probe(struct platform_device *pdev)
ec6bced6	231	{
747a7f64 KH	232	mpu_dev = get_cpu_device(0);
747a7f64 KH	233	if (!mpu_dev) {
a820ffa8	234	pr_warning("%s: unable to get the mpu device\n", __func__);
747a7f64	235	return -EINVAL;
a820ffa8 NM	236	}
a820ffa8 NM	237
53dfe8a8 KH	238	mpu_reg = regulator_get(mpu_dev, "vcc");
	239	if (IS_ERR(mpu_reg)) {
	240	pr_warning("%s: unable to get MPU regulator\n", __func__);
	241	mpu_reg = NULL;
	242	} else {
	243	/*
	244	* Ensure physical regulator is present.
	245	* (e.g. could be dummy regulator.)
	246	*/
	247	if (regulator_get_voltage(mpu_reg) < 0) {
	248	pr_warn("%s: physical regulator not present for MPU\n",
	249	__func__);
	250	regulator_put(mpu_reg);
	251	mpu_reg = NULL;
	252	}
	253	}
	254
ec6bced6 TL	255	return cpufreq_register_driver(&omap_driver);
	256	}
	257
49ded525	258	static int omap_cpufreq_remove(struct platform_device *pdev)
731e0cc6	259	{
49ded525	260	return cpufreq_unregister_driver(&omap_driver);
731e0cc6	261	}
aeec2990	262
49ded525 NM	263	static struct platform_driver omap_cpufreq_platdrv = {
	264	.driver = {
	265	.name = "omap-cpufreq",
	266	.owner = THIS_MODULE,
	267	},
	268	.probe = omap_cpufreq_probe,
	269	.remove = omap_cpufreq_remove,
	270	};
	271	module_platform_driver(omap_cpufreq_platdrv);
	272
731e0cc6 SS	273	MODULE_DESCRIPTION("cpufreq driver for OMAP SoCs");
731e0cc6 SS	274	MODULE_LICENSE("GPL");