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Commit | Line | Data |
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1da177e4 | 1 | /* |
73860c6b | 2 | * (c) 2003-2010 Advanced Micro Devices, Inc. |
1da177e4 LT |
3 | * Your use of this code is subject to the terms and conditions of the |
4 | * GNU general public license version 2. See "COPYING" or | |
5 | * http://www.gnu.org/licenses/gpl.html | |
6 | * | |
065b807c | 7 | * Support : mark.langsdorf@amd.com |
1da177e4 LT |
8 | * |
9 | * Based on the powernow-k7.c module written by Dave Jones. | |
f4432c5c | 10 | * (C) 2003 Dave Jones on behalf of SuSE Labs |
1da177e4 | 11 | * (C) 2004 Dominik Brodowski <linux@brodo.de> |
a2531293 | 12 | * (C) 2004 Pavel Machek <pavel@ucw.cz> |
1da177e4 LT |
13 | * Licensed under the terms of the GNU GPL License version 2. |
14 | * Based upon datasheets & sample CPUs kindly provided by AMD. | |
15 | * | |
16 | * Valuable input gratefully received from Dave Jones, Pavel Machek, | |
1f729e06 | 17 | * Dominik Brodowski, Jacob Shin, and others. |
065b807c | 18 | * Originally developed by Paul Devriendt. |
1da177e4 LT |
19 | * Processor information obtained from Chapter 9 (Power and Thermal Management) |
20 | * of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD | |
21 | * Opteron Processors" available for download from www.amd.com | |
22 | * | |
2e3f8faa | 23 | * Tables for specific CPUs can be inferred from |
065b807c | 24 | * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/30430.pdf |
1da177e4 LT |
25 | */ |
26 | ||
27 | #include <linux/kernel.h> | |
28 | #include <linux/smp.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/init.h> | |
31 | #include <linux/cpufreq.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/string.h> | |
065b807c | 34 | #include <linux/cpumask.h> |
4e57b681 | 35 | #include <linux/sched.h> /* for current / set_cpus_allowed() */ |
0e64a0c9 DJ |
36 | #include <linux/io.h> |
37 | #include <linux/delay.h> | |
1da177e4 LT |
38 | |
39 | #include <asm/msr.h> | |
1da177e4 | 40 | |
1da177e4 | 41 | #include <linux/acpi.h> |
14cc3e2b | 42 | #include <linux/mutex.h> |
1da177e4 | 43 | #include <acpi/processor.h> |
1da177e4 LT |
44 | |
45 | #define PFX "powernow-k8: " | |
c5829cd0 | 46 | #define VERSION "version 2.20.00" |
1da177e4 | 47 | #include "powernow-k8.h" |
a2fed573 | 48 | #include "mperf.h" |
1da177e4 LT |
49 | |
50 | /* serialize freq changes */ | |
14cc3e2b | 51 | static DEFINE_MUTEX(fidvid_mutex); |
1da177e4 | 52 | |
2c6b8c03 | 53 | static DEFINE_PER_CPU(struct powernow_k8_data *, powernow_data); |
1da177e4 | 54 | |
1f729e06 DJ |
55 | static int cpu_family = CPU_OPTERON; |
56 | ||
a8eb2848 AH |
57 | /* array to map SW pstate number to acpi state */ |
58 | static u32 ps_to_as[8]; | |
59 | ||
73860c6b BP |
60 | /* core performance boost */ |
61 | static bool cpb_capable, cpb_enabled; | |
62 | static struct msr __percpu *msrs; | |
63 | ||
a2fed573 ML |
64 | static struct cpufreq_driver cpufreq_amd64_driver; |
65 | ||
065b807c | 66 | #ifndef CONFIG_SMP |
7ad728f9 RR |
67 | static inline const struct cpumask *cpu_core_mask(int cpu) |
68 | { | |
69 | return cpumask_of(0); | |
70 | } | |
065b807c DJ |
71 | #endif |
72 | ||
1da177e4 LT |
73 | /* Return a frequency in MHz, given an input fid */ |
74 | static u32 find_freq_from_fid(u32 fid) | |
75 | { | |
76 | return 800 + (fid * 100); | |
77 | } | |
78 | ||
79 | /* Return a frequency in KHz, given an input fid */ | |
80 | static u32 find_khz_freq_from_fid(u32 fid) | |
81 | { | |
82 | return 1000 * find_freq_from_fid(fid); | |
83 | } | |
84 | ||
0e64a0c9 | 85 | static u32 find_khz_freq_from_pstate(struct cpufreq_frequency_table *data, |
a8eb2848 | 86 | u32 pstate) |
1f729e06 | 87 | { |
a8eb2848 | 88 | return data[ps_to_as[pstate]].frequency; |
1f729e06 DJ |
89 | } |
90 | ||
1da177e4 LT |
91 | /* Return the vco fid for an input fid |
92 | * | |
93 | * Each "low" fid has corresponding "high" fid, and you can get to "low" fids | |
94 | * only from corresponding high fids. This returns "high" fid corresponding to | |
95 | * "low" one. | |
96 | */ | |
97 | static u32 convert_fid_to_vco_fid(u32 fid) | |
98 | { | |
32ee8c3e | 99 | if (fid < HI_FID_TABLE_BOTTOM) |
1da177e4 | 100 | return 8 + (2 * fid); |
32ee8c3e | 101 | else |
1da177e4 | 102 | return fid; |
1da177e4 LT |
103 | } |
104 | ||
105 | /* | |
106 | * Return 1 if the pending bit is set. Unless we just instructed the processor | |
107 | * to transition to a new state, seeing this bit set is really bad news. | |
108 | */ | |
109 | static int pending_bit_stuck(void) | |
110 | { | |
111 | u32 lo, hi; | |
112 | ||
e7bdd7a5 | 113 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
114 | return 0; |
115 | ||
1da177e4 LT |
116 | rdmsr(MSR_FIDVID_STATUS, lo, hi); |
117 | return lo & MSR_S_LO_CHANGE_PENDING ? 1 : 0; | |
118 | } | |
119 | ||
120 | /* | |
121 | * Update the global current fid / vid values from the status msr. | |
122 | * Returns 1 on error. | |
123 | */ | |
124 | static int query_current_values_with_pending_wait(struct powernow_k8_data *data) | |
125 | { | |
126 | u32 lo, hi; | |
127 | u32 i = 0; | |
128 | ||
e7bdd7a5 | 129 | if (cpu_family == CPU_HW_PSTATE) { |
532cfee6 NC |
130 | rdmsr(MSR_PSTATE_STATUS, lo, hi); |
131 | i = lo & HW_PSTATE_MASK; | |
132 | data->currpstate = i; | |
133 | ||
134 | /* | |
135 | * a workaround for family 11h erratum 311 might cause | |
136 | * an "out-of-range Pstate if the core is in Pstate-0 | |
137 | */ | |
138 | if ((boot_cpu_data.x86 == 0x11) && (i >= data->numps)) | |
139 | data->currpstate = HW_PSTATE_0; | |
140 | ||
1f729e06 DJ |
141 | return 0; |
142 | } | |
7153d961 | 143 | do { |
0213df74 | 144 | if (i++ > 10000) { |
2d06d8c4 | 145 | pr_debug("detected change pending stuck\n"); |
1da177e4 LT |
146 | return 1; |
147 | } | |
148 | rdmsr(MSR_FIDVID_STATUS, lo, hi); | |
7153d961 | 149 | } while (lo & MSR_S_LO_CHANGE_PENDING); |
1da177e4 LT |
150 | |
151 | data->currvid = hi & MSR_S_HI_CURRENT_VID; | |
152 | data->currfid = lo & MSR_S_LO_CURRENT_FID; | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
157 | /* the isochronous relief time */ | |
158 | static void count_off_irt(struct powernow_k8_data *data) | |
159 | { | |
160 | udelay((1 << data->irt) * 10); | |
161 | return; | |
162 | } | |
163 | ||
27b46d76 | 164 | /* the voltage stabilization time */ |
1da177e4 LT |
165 | static void count_off_vst(struct powernow_k8_data *data) |
166 | { | |
167 | udelay(data->vstable * VST_UNITS_20US); | |
168 | return; | |
169 | } | |
170 | ||
171 | /* need to init the control msr to a safe value (for each cpu) */ | |
172 | static void fidvid_msr_init(void) | |
173 | { | |
174 | u32 lo, hi; | |
175 | u8 fid, vid; | |
176 | ||
177 | rdmsr(MSR_FIDVID_STATUS, lo, hi); | |
178 | vid = hi & MSR_S_HI_CURRENT_VID; | |
179 | fid = lo & MSR_S_LO_CURRENT_FID; | |
180 | lo = fid | (vid << MSR_C_LO_VID_SHIFT); | |
181 | hi = MSR_C_HI_STP_GNT_BENIGN; | |
2d06d8c4 | 182 | pr_debug("cpu%d, init lo 0x%x, hi 0x%x\n", smp_processor_id(), lo, hi); |
1da177e4 LT |
183 | wrmsr(MSR_FIDVID_CTL, lo, hi); |
184 | } | |
185 | ||
1da177e4 LT |
186 | /* write the new fid value along with the other control fields to the msr */ |
187 | static int write_new_fid(struct powernow_k8_data *data, u32 fid) | |
188 | { | |
189 | u32 lo; | |
190 | u32 savevid = data->currvid; | |
0213df74 | 191 | u32 i = 0; |
1da177e4 LT |
192 | |
193 | if ((fid & INVALID_FID_MASK) || (data->currvid & INVALID_VID_MASK)) { | |
194 | printk(KERN_ERR PFX "internal error - overflow on fid write\n"); | |
195 | return 1; | |
196 | } | |
197 | ||
0e64a0c9 DJ |
198 | lo = fid; |
199 | lo |= (data->currvid << MSR_C_LO_VID_SHIFT); | |
200 | lo |= MSR_C_LO_INIT_FID_VID; | |
1da177e4 | 201 | |
2d06d8c4 | 202 | pr_debug("writing fid 0x%x, lo 0x%x, hi 0x%x\n", |
1da177e4 LT |
203 | fid, lo, data->plllock * PLL_LOCK_CONVERSION); |
204 | ||
0213df74 DJ |
205 | do { |
206 | wrmsr(MSR_FIDVID_CTL, lo, data->plllock * PLL_LOCK_CONVERSION); | |
207 | if (i++ > 100) { | |
0e64a0c9 DJ |
208 | printk(KERN_ERR PFX |
209 | "Hardware error - pending bit very stuck - " | |
210 | "no further pstate changes possible\n"); | |
63172cb3 | 211 | return 1; |
32ee8c3e | 212 | } |
0213df74 | 213 | } while (query_current_values_with_pending_wait(data)); |
1da177e4 LT |
214 | |
215 | count_off_irt(data); | |
216 | ||
217 | if (savevid != data->currvid) { | |
0e64a0c9 DJ |
218 | printk(KERN_ERR PFX |
219 | "vid change on fid trans, old 0x%x, new 0x%x\n", | |
220 | savevid, data->currvid); | |
1da177e4 LT |
221 | return 1; |
222 | } | |
223 | ||
224 | if (fid != data->currfid) { | |
0e64a0c9 DJ |
225 | printk(KERN_ERR PFX |
226 | "fid trans failed, fid 0x%x, curr 0x%x\n", fid, | |
227 | data->currfid); | |
1da177e4 LT |
228 | return 1; |
229 | } | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | /* Write a new vid to the hardware */ | |
235 | static int write_new_vid(struct powernow_k8_data *data, u32 vid) | |
236 | { | |
237 | u32 lo; | |
238 | u32 savefid = data->currfid; | |
0213df74 | 239 | int i = 0; |
1da177e4 LT |
240 | |
241 | if ((data->currfid & INVALID_FID_MASK) || (vid & INVALID_VID_MASK)) { | |
242 | printk(KERN_ERR PFX "internal error - overflow on vid write\n"); | |
243 | return 1; | |
244 | } | |
245 | ||
0e64a0c9 DJ |
246 | lo = data->currfid; |
247 | lo |= (vid << MSR_C_LO_VID_SHIFT); | |
248 | lo |= MSR_C_LO_INIT_FID_VID; | |
1da177e4 | 249 | |
2d06d8c4 | 250 | pr_debug("writing vid 0x%x, lo 0x%x, hi 0x%x\n", |
1da177e4 LT |
251 | vid, lo, STOP_GRANT_5NS); |
252 | ||
0213df74 DJ |
253 | do { |
254 | wrmsr(MSR_FIDVID_CTL, lo, STOP_GRANT_5NS); | |
6df89006 | 255 | if (i++ > 100) { |
0e64a0c9 DJ |
256 | printk(KERN_ERR PFX "internal error - pending bit " |
257 | "very stuck - no further pstate " | |
258 | "changes possible\n"); | |
6df89006 DJ |
259 | return 1; |
260 | } | |
0213df74 | 261 | } while (query_current_values_with_pending_wait(data)); |
1da177e4 LT |
262 | |
263 | if (savefid != data->currfid) { | |
0e64a0c9 DJ |
264 | printk(KERN_ERR PFX "fid changed on vid trans, old " |
265 | "0x%x new 0x%x\n", | |
1da177e4 LT |
266 | savefid, data->currfid); |
267 | return 1; | |
268 | } | |
269 | ||
270 | if (vid != data->currvid) { | |
0e64a0c9 DJ |
271 | printk(KERN_ERR PFX "vid trans failed, vid 0x%x, " |
272 | "curr 0x%x\n", | |
273 | vid, data->currvid); | |
1da177e4 LT |
274 | return 1; |
275 | } | |
276 | ||
277 | return 0; | |
278 | } | |
279 | ||
280 | /* | |
281 | * Reduce the vid by the max of step or reqvid. | |
282 | * Decreasing vid codes represent increasing voltages: | |
841e40b3 | 283 | * vid of 0 is 1.550V, vid of 0x1e is 0.800V, vid of VID_OFF is off. |
1da177e4 | 284 | */ |
0e64a0c9 DJ |
285 | static int decrease_vid_code_by_step(struct powernow_k8_data *data, |
286 | u32 reqvid, u32 step) | |
1da177e4 LT |
287 | { |
288 | if ((data->currvid - reqvid) > step) | |
289 | reqvid = data->currvid - step; | |
290 | ||
291 | if (write_new_vid(data, reqvid)) | |
292 | return 1; | |
293 | ||
294 | count_off_vst(data); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
1f729e06 DJ |
299 | /* Change hardware pstate by single MSR write */ |
300 | static int transition_pstate(struct powernow_k8_data *data, u32 pstate) | |
301 | { | |
302 | wrmsr(MSR_PSTATE_CTRL, pstate, 0); | |
c5829cd0 | 303 | data->currpstate = pstate; |
1f729e06 DJ |
304 | return 0; |
305 | } | |
306 | ||
307 | /* Change Opteron/Athlon64 fid and vid, by the 3 phases. */ | |
0e64a0c9 DJ |
308 | static int transition_fid_vid(struct powernow_k8_data *data, |
309 | u32 reqfid, u32 reqvid) | |
1da177e4 | 310 | { |
a2e1b4c3 | 311 | if (core_voltage_pre_transition(data, reqvid, reqfid)) |
1da177e4 LT |
312 | return 1; |
313 | ||
314 | if (core_frequency_transition(data, reqfid)) | |
315 | return 1; | |
316 | ||
317 | if (core_voltage_post_transition(data, reqvid)) | |
318 | return 1; | |
319 | ||
320 | if (query_current_values_with_pending_wait(data)) | |
321 | return 1; | |
322 | ||
323 | if ((reqfid != data->currfid) || (reqvid != data->currvid)) { | |
0e64a0c9 DJ |
324 | printk(KERN_ERR PFX "failed (cpu%d): req 0x%x 0x%x, " |
325 | "curr 0x%x 0x%x\n", | |
1da177e4 LT |
326 | smp_processor_id(), |
327 | reqfid, reqvid, data->currfid, data->currvid); | |
328 | return 1; | |
329 | } | |
330 | ||
2d06d8c4 | 331 | pr_debug("transitioned (cpu%d): new fid 0x%x, vid 0x%x\n", |
1da177e4 LT |
332 | smp_processor_id(), data->currfid, data->currvid); |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | /* Phase 1 - core voltage transition ... setup voltage */ | |
0e64a0c9 | 338 | static int core_voltage_pre_transition(struct powernow_k8_data *data, |
a2e1b4c3 | 339 | u32 reqvid, u32 reqfid) |
1da177e4 LT |
340 | { |
341 | u32 rvosteps = data->rvo; | |
342 | u32 savefid = data->currfid; | |
a2e1b4c3 | 343 | u32 maxvid, lo, rvomult = 1; |
1da177e4 | 344 | |
2d06d8c4 | 345 | pr_debug("ph1 (cpu%d): start, currfid 0x%x, currvid 0x%x, " |
0e64a0c9 | 346 | "reqvid 0x%x, rvo 0x%x\n", |
1da177e4 LT |
347 | smp_processor_id(), |
348 | data->currfid, data->currvid, reqvid, data->rvo); | |
349 | ||
a2e1b4c3 ML |
350 | if ((savefid < LO_FID_TABLE_TOP) && (reqfid < LO_FID_TABLE_TOP)) |
351 | rvomult = 2; | |
352 | rvosteps *= rvomult; | |
065b807c DJ |
353 | rdmsr(MSR_FIDVID_STATUS, lo, maxvid); |
354 | maxvid = 0x1f & (maxvid >> 16); | |
2d06d8c4 | 355 | pr_debug("ph1 maxvid=0x%x\n", maxvid); |
065b807c DJ |
356 | if (reqvid < maxvid) /* lower numbers are higher voltages */ |
357 | reqvid = maxvid; | |
358 | ||
1da177e4 | 359 | while (data->currvid > reqvid) { |
2d06d8c4 | 360 | pr_debug("ph1: curr 0x%x, req vid 0x%x\n", |
1da177e4 LT |
361 | data->currvid, reqvid); |
362 | if (decrease_vid_code_by_step(data, reqvid, data->vidmvs)) | |
363 | return 1; | |
364 | } | |
365 | ||
a2e1b4c3 ML |
366 | while ((rvosteps > 0) && |
367 | ((rvomult * data->rvo + data->currvid) > reqvid)) { | |
065b807c | 368 | if (data->currvid == maxvid) { |
1da177e4 LT |
369 | rvosteps = 0; |
370 | } else { | |
2d06d8c4 | 371 | pr_debug("ph1: changing vid for rvo, req 0x%x\n", |
1da177e4 | 372 | data->currvid - 1); |
0e64a0c9 | 373 | if (decrease_vid_code_by_step(data, data->currvid-1, 1)) |
1da177e4 LT |
374 | return 1; |
375 | rvosteps--; | |
376 | } | |
377 | } | |
378 | ||
379 | if (query_current_values_with_pending_wait(data)) | |
380 | return 1; | |
381 | ||
382 | if (savefid != data->currfid) { | |
0e64a0c9 DJ |
383 | printk(KERN_ERR PFX "ph1 err, currfid changed 0x%x\n", |
384 | data->currfid); | |
1da177e4 LT |
385 | return 1; |
386 | } | |
387 | ||
2d06d8c4 | 388 | pr_debug("ph1 complete, currfid 0x%x, currvid 0x%x\n", |
1da177e4 LT |
389 | data->currfid, data->currvid); |
390 | ||
391 | return 0; | |
392 | } | |
393 | ||
394 | /* Phase 2 - core frequency transition */ | |
395 | static int core_frequency_transition(struct powernow_k8_data *data, u32 reqfid) | |
396 | { | |
0e64a0c9 DJ |
397 | u32 vcoreqfid, vcocurrfid, vcofiddiff; |
398 | u32 fid_interval, savevid = data->currvid; | |
1da177e4 | 399 | |
1da177e4 | 400 | if (data->currfid == reqfid) { |
0e64a0c9 DJ |
401 | printk(KERN_ERR PFX "ph2 null fid transition 0x%x\n", |
402 | data->currfid); | |
1da177e4 LT |
403 | return 0; |
404 | } | |
405 | ||
2d06d8c4 | 406 | pr_debug("ph2 (cpu%d): starting, currfid 0x%x, currvid 0x%x, " |
0e64a0c9 | 407 | "reqfid 0x%x\n", |
1da177e4 LT |
408 | smp_processor_id(), |
409 | data->currfid, data->currvid, reqfid); | |
410 | ||
411 | vcoreqfid = convert_fid_to_vco_fid(reqfid); | |
412 | vcocurrfid = convert_fid_to_vco_fid(data->currfid); | |
413 | vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid | |
414 | : vcoreqfid - vcocurrfid; | |
415 | ||
a2e1b4c3 ML |
416 | if ((reqfid <= LO_FID_TABLE_TOP) && (data->currfid <= LO_FID_TABLE_TOP)) |
417 | vcofiddiff = 0; | |
418 | ||
1da177e4 | 419 | while (vcofiddiff > 2) { |
019a61b9 LM |
420 | (data->currfid & 1) ? (fid_interval = 1) : (fid_interval = 2); |
421 | ||
1da177e4 LT |
422 | if (reqfid > data->currfid) { |
423 | if (data->currfid > LO_FID_TABLE_TOP) { | |
0e64a0c9 DJ |
424 | if (write_new_fid(data, |
425 | data->currfid + fid_interval)) | |
1da177e4 | 426 | return 1; |
1da177e4 LT |
427 | } else { |
428 | if (write_new_fid | |
0e64a0c9 DJ |
429 | (data, |
430 | 2 + convert_fid_to_vco_fid(data->currfid))) | |
1da177e4 | 431 | return 1; |
1da177e4 LT |
432 | } |
433 | } else { | |
019a61b9 | 434 | if (write_new_fid(data, data->currfid - fid_interval)) |
1da177e4 LT |
435 | return 1; |
436 | } | |
437 | ||
438 | vcocurrfid = convert_fid_to_vco_fid(data->currfid); | |
439 | vcofiddiff = vcocurrfid > vcoreqfid ? vcocurrfid - vcoreqfid | |
440 | : vcoreqfid - vcocurrfid; | |
441 | } | |
442 | ||
443 | if (write_new_fid(data, reqfid)) | |
444 | return 1; | |
445 | ||
446 | if (query_current_values_with_pending_wait(data)) | |
447 | return 1; | |
448 | ||
449 | if (data->currfid != reqfid) { | |
450 | printk(KERN_ERR PFX | |
0e64a0c9 DJ |
451 | "ph2: mismatch, failed fid transition, " |
452 | "curr 0x%x, req 0x%x\n", | |
1da177e4 LT |
453 | data->currfid, reqfid); |
454 | return 1; | |
455 | } | |
456 | ||
457 | if (savevid != data->currvid) { | |
458 | printk(KERN_ERR PFX "ph2: vid changed, save 0x%x, curr 0x%x\n", | |
459 | savevid, data->currvid); | |
460 | return 1; | |
461 | } | |
462 | ||
2d06d8c4 | 463 | pr_debug("ph2 complete, currfid 0x%x, currvid 0x%x\n", |
1da177e4 LT |
464 | data->currfid, data->currvid); |
465 | ||
466 | return 0; | |
467 | } | |
468 | ||
469 | /* Phase 3 - core voltage transition flow ... jump to the final vid. */ | |
0e64a0c9 DJ |
470 | static int core_voltage_post_transition(struct powernow_k8_data *data, |
471 | u32 reqvid) | |
1da177e4 LT |
472 | { |
473 | u32 savefid = data->currfid; | |
474 | u32 savereqvid = reqvid; | |
475 | ||
2d06d8c4 | 476 | pr_debug("ph3 (cpu%d): starting, currfid 0x%x, currvid 0x%x\n", |
1da177e4 LT |
477 | smp_processor_id(), |
478 | data->currfid, data->currvid); | |
479 | ||
480 | if (reqvid != data->currvid) { | |
481 | if (write_new_vid(data, reqvid)) | |
482 | return 1; | |
483 | ||
484 | if (savefid != data->currfid) { | |
485 | printk(KERN_ERR PFX | |
486 | "ph3: bad fid change, save 0x%x, curr 0x%x\n", | |
487 | savefid, data->currfid); | |
488 | return 1; | |
489 | } | |
490 | ||
491 | if (data->currvid != reqvid) { | |
492 | printk(KERN_ERR PFX | |
0e64a0c9 DJ |
493 | "ph3: failed vid transition\n, " |
494 | "req 0x%x, curr 0x%x", | |
1da177e4 LT |
495 | reqvid, data->currvid); |
496 | return 1; | |
497 | } | |
498 | } | |
499 | ||
500 | if (query_current_values_with_pending_wait(data)) | |
501 | return 1; | |
502 | ||
503 | if (savereqvid != data->currvid) { | |
2d06d8c4 | 504 | pr_debug("ph3 failed, currvid 0x%x\n", data->currvid); |
1da177e4 LT |
505 | return 1; |
506 | } | |
507 | ||
508 | if (savefid != data->currfid) { | |
2d06d8c4 | 509 | pr_debug("ph3 failed, currfid changed 0x%x\n", |
1da177e4 LT |
510 | data->currfid); |
511 | return 1; | |
512 | } | |
513 | ||
2d06d8c4 | 514 | pr_debug("ph3 complete, currfid 0x%x, currvid 0x%x\n", |
1da177e4 LT |
515 | data->currfid, data->currvid); |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
1ff6e97f | 520 | static void check_supported_cpu(void *_rc) |
1da177e4 | 521 | { |
1da177e4 | 522 | u32 eax, ebx, ecx, edx; |
1ff6e97f | 523 | int *rc = _rc; |
1da177e4 | 524 | |
1ff6e97f | 525 | *rc = -ENODEV; |
1da177e4 | 526 | |
7b543a53 | 527 | if (__this_cpu_read(cpu_info.x86_vendor) != X86_VENDOR_AMD) |
1ff6e97f | 528 | return; |
1da177e4 LT |
529 | |
530 | eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); | |
1f729e06 DJ |
531 | if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) && |
532 | ((eax & CPUID_XFAM) < CPUID_XFAM_10H)) | |
1ff6e97f | 533 | return; |
2c906ae6 | 534 | |
1f729e06 DJ |
535 | if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { |
536 | if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || | |
99fbe1ac | 537 | ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) { |
0e64a0c9 DJ |
538 | printk(KERN_INFO PFX |
539 | "Processor cpuid %x not supported\n", eax); | |
1ff6e97f | 540 | return; |
1f729e06 | 541 | } |
1da177e4 | 542 | |
1f729e06 DJ |
543 | eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); |
544 | if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { | |
545 | printk(KERN_INFO PFX | |
546 | "No frequency change capabilities detected\n"); | |
1ff6e97f | 547 | return; |
1f729e06 | 548 | } |
1da177e4 | 549 | |
1f729e06 | 550 | cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); |
0e64a0c9 DJ |
551 | if ((edx & P_STATE_TRANSITION_CAPABLE) |
552 | != P_STATE_TRANSITION_CAPABLE) { | |
553 | printk(KERN_INFO PFX | |
554 | "Power state transitions not supported\n"); | |
1ff6e97f | 555 | return; |
1f729e06 DJ |
556 | } |
557 | } else { /* must be a HW Pstate capable processor */ | |
558 | cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); | |
559 | if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE) | |
560 | cpu_family = CPU_HW_PSTATE; | |
561 | else | |
1ff6e97f | 562 | return; |
1da177e4 LT |
563 | } |
564 | ||
1ff6e97f | 565 | *rc = 0; |
1da177e4 LT |
566 | } |
567 | ||
0e64a0c9 DJ |
568 | static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, |
569 | u8 maxvid) | |
1da177e4 LT |
570 | { |
571 | unsigned int j; | |
572 | u8 lastfid = 0xff; | |
573 | ||
574 | for (j = 0; j < data->numps; j++) { | |
575 | if (pst[j].vid > LEAST_VID) { | |
2fd47094 TR |
576 | printk(KERN_ERR FW_BUG PFX "vid %d invalid : 0x%x\n", |
577 | j, pst[j].vid); | |
1da177e4 LT |
578 | return -EINVAL; |
579 | } | |
0e64a0c9 DJ |
580 | if (pst[j].vid < data->rvo) { |
581 | /* vid + rvo >= 0 */ | |
2fd47094 TR |
582 | printk(KERN_ERR FW_BUG PFX "0 vid exceeded with pstate" |
583 | " %d\n", j); | |
1da177e4 LT |
584 | return -ENODEV; |
585 | } | |
0e64a0c9 DJ |
586 | if (pst[j].vid < maxvid + data->rvo) { |
587 | /* vid + rvo >= maxvid */ | |
2fd47094 TR |
588 | printk(KERN_ERR FW_BUG PFX "maxvid exceeded with pstate" |
589 | " %d\n", j); | |
1da177e4 LT |
590 | return -ENODEV; |
591 | } | |
8aae8284 | 592 | if (pst[j].fid > MAX_FID) { |
2fd47094 TR |
593 | printk(KERN_ERR FW_BUG PFX "maxfid exceeded with pstate" |
594 | " %d\n", j); | |
8aae8284 JS |
595 | return -ENODEV; |
596 | } | |
8aae8284 | 597 | if (j && (pst[j].fid < HI_FID_TABLE_BOTTOM)) { |
1da177e4 | 598 | /* Only first fid is allowed to be in "low" range */ |
2fd47094 TR |
599 | printk(KERN_ERR FW_BUG PFX "two low fids - %d : " |
600 | "0x%x\n", j, pst[j].fid); | |
1da177e4 LT |
601 | return -EINVAL; |
602 | } | |
603 | if (pst[j].fid < lastfid) | |
604 | lastfid = pst[j].fid; | |
605 | } | |
606 | if (lastfid & 1) { | |
2fd47094 | 607 | printk(KERN_ERR FW_BUG PFX "lastfid invalid\n"); |
1da177e4 LT |
608 | return -EINVAL; |
609 | } | |
610 | if (lastfid > LO_FID_TABLE_TOP) | |
0e64a0c9 DJ |
611 | printk(KERN_INFO FW_BUG PFX |
612 | "first fid not from lo freq table\n"); | |
1da177e4 LT |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
f0adb134 KR |
617 | static void invalidate_entry(struct cpufreq_frequency_table *powernow_table, |
618 | unsigned int entry) | |
0e64a0c9 | 619 | { |
f0adb134 | 620 | powernow_table[entry].frequency = CPUFREQ_ENTRY_INVALID; |
0e64a0c9 DJ |
621 | } |
622 | ||
1da177e4 LT |
623 | static void print_basics(struct powernow_k8_data *data) |
624 | { | |
625 | int j; | |
626 | for (j = 0; j < data->numps; j++) { | |
0e64a0c9 DJ |
627 | if (data->powernow_table[j].frequency != |
628 | CPUFREQ_ENTRY_INVALID) { | |
e7bdd7a5 | 629 | if (cpu_family == CPU_HW_PSTATE) { |
0e64a0c9 DJ |
630 | printk(KERN_INFO PFX |
631 | " %d : pstate %d (%d MHz)\n", j, | |
4ae5c49f | 632 | data->powernow_table[j].index, |
9a60ddbc | 633 | data->powernow_table[j].frequency/1000); |
1f729e06 | 634 | } else { |
0e64a0c9 | 635 | printk(KERN_INFO PFX |
9e918695 | 636 | "fid 0x%x (%d MHz), vid 0x%x\n", |
9a60ddbc DJ |
637 | data->powernow_table[j].index & 0xff, |
638 | data->powernow_table[j].frequency/1000, | |
639 | data->powernow_table[j].index >> 8); | |
1f729e06 DJ |
640 | } |
641 | } | |
1da177e4 LT |
642 | } |
643 | if (data->batps) | |
0e64a0c9 DJ |
644 | printk(KERN_INFO PFX "Only %d pstates on battery\n", |
645 | data->batps); | |
1da177e4 LT |
646 | } |
647 | ||
ca446d06 AH |
648 | static u32 freq_from_fid_did(u32 fid, u32 did) |
649 | { | |
650 | u32 mhz = 0; | |
651 | ||
652 | if (boot_cpu_data.x86 == 0x10) | |
653 | mhz = (100 * (fid + 0x10)) >> did; | |
654 | else if (boot_cpu_data.x86 == 0x11) | |
655 | mhz = (100 * (fid + 8)) >> did; | |
656 | else | |
657 | BUG(); | |
658 | ||
659 | return mhz * 1000; | |
660 | } | |
661 | ||
0e64a0c9 DJ |
662 | static int fill_powernow_table(struct powernow_k8_data *data, |
663 | struct pst_s *pst, u8 maxvid) | |
1da177e4 LT |
664 | { |
665 | struct cpufreq_frequency_table *powernow_table; | |
666 | unsigned int j; | |
667 | ||
0e64a0c9 DJ |
668 | if (data->batps) { |
669 | /* use ACPI support to get full speed on mains power */ | |
670 | printk(KERN_WARNING PFX | |
671 | "Only %d pstates usable (use ACPI driver for full " | |
672 | "range\n", data->batps); | |
1da177e4 LT |
673 | data->numps = data->batps; |
674 | } | |
675 | ||
0e64a0c9 | 676 | for (j = 1; j < data->numps; j++) { |
1da177e4 LT |
677 | if (pst[j-1].fid >= pst[j].fid) { |
678 | printk(KERN_ERR PFX "PST out of sequence\n"); | |
679 | return -EINVAL; | |
680 | } | |
681 | } | |
682 | ||
683 | if (data->numps < 2) { | |
684 | printk(KERN_ERR PFX "no p states to transition\n"); | |
685 | return -ENODEV; | |
686 | } | |
687 | ||
688 | if (check_pst_table(data, pst, maxvid)) | |
689 | return -EINVAL; | |
690 | ||
691 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | |
692 | * (data->numps + 1)), GFP_KERNEL); | |
693 | if (!powernow_table) { | |
694 | printk(KERN_ERR PFX "powernow_table memory alloc failure\n"); | |
695 | return -ENOMEM; | |
696 | } | |
697 | ||
698 | for (j = 0; j < data->numps; j++) { | |
0e64a0c9 | 699 | int freq; |
1da177e4 LT |
700 | powernow_table[j].index = pst[j].fid; /* lower 8 bits */ |
701 | powernow_table[j].index |= (pst[j].vid << 8); /* upper 8 bits */ | |
0e64a0c9 DJ |
702 | freq = find_khz_freq_from_fid(pst[j].fid); |
703 | powernow_table[j].frequency = freq; | |
1da177e4 LT |
704 | } |
705 | powernow_table[data->numps].frequency = CPUFREQ_TABLE_END; | |
706 | powernow_table[data->numps].index = 0; | |
707 | ||
708 | if (query_current_values_with_pending_wait(data)) { | |
709 | kfree(powernow_table); | |
710 | return -EIO; | |
711 | } | |
712 | ||
2d06d8c4 | 713 | pr_debug("cfid 0x%x, cvid 0x%x\n", data->currfid, data->currvid); |
1da177e4 | 714 | data->powernow_table = powernow_table; |
7ad728f9 | 715 | if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) |
2e497620 | 716 | print_basics(data); |
1da177e4 LT |
717 | |
718 | for (j = 0; j < data->numps; j++) | |
0e64a0c9 DJ |
719 | if ((pst[j].fid == data->currfid) && |
720 | (pst[j].vid == data->currvid)) | |
1da177e4 LT |
721 | return 0; |
722 | ||
2d06d8c4 | 723 | pr_debug("currfid/vid do not match PST, ignoring\n"); |
1da177e4 LT |
724 | return 0; |
725 | } | |
726 | ||
727 | /* Find and validate the PSB/PST table in BIOS. */ | |
728 | static int find_psb_table(struct powernow_k8_data *data) | |
729 | { | |
730 | struct psb_s *psb; | |
731 | unsigned int i; | |
732 | u32 mvs; | |
733 | u8 maxvid; | |
734 | u32 cpst = 0; | |
735 | u32 thiscpuid; | |
736 | ||
737 | for (i = 0xc0000; i < 0xffff0; i += 0x10) { | |
738 | /* Scan BIOS looking for the signature. */ | |
739 | /* It can not be at ffff0 - it is too big. */ | |
740 | ||
741 | psb = phys_to_virt(i); | |
742 | if (memcmp(psb, PSB_ID_STRING, PSB_ID_STRING_LEN) != 0) | |
743 | continue; | |
744 | ||
2d06d8c4 | 745 | pr_debug("found PSB header at 0x%p\n", psb); |
1da177e4 | 746 | |
2d06d8c4 | 747 | pr_debug("table vers: 0x%x\n", psb->tableversion); |
1da177e4 | 748 | if (psb->tableversion != PSB_VERSION_1_4) { |
2fd47094 | 749 | printk(KERN_ERR FW_BUG PFX "PSB table is not v1.4\n"); |
1da177e4 LT |
750 | return -ENODEV; |
751 | } | |
752 | ||
2d06d8c4 | 753 | pr_debug("flags: 0x%x\n", psb->flags1); |
1da177e4 | 754 | if (psb->flags1) { |
2fd47094 | 755 | printk(KERN_ERR FW_BUG PFX "unknown flags\n"); |
1da177e4 LT |
756 | return -ENODEV; |
757 | } | |
758 | ||
759 | data->vstable = psb->vstable; | |
2d06d8c4 | 760 | pr_debug("voltage stabilization time: %d(*20us)\n", |
0e64a0c9 | 761 | data->vstable); |
1da177e4 | 762 | |
2d06d8c4 | 763 | pr_debug("flags2: 0x%x\n", psb->flags2); |
1da177e4 LT |
764 | data->rvo = psb->flags2 & 3; |
765 | data->irt = ((psb->flags2) >> 2) & 3; | |
766 | mvs = ((psb->flags2) >> 4) & 3; | |
767 | data->vidmvs = 1 << mvs; | |
768 | data->batps = ((psb->flags2) >> 6) & 3; | |
769 | ||
2d06d8c4 DB |
770 | pr_debug("ramp voltage offset: %d\n", data->rvo); |
771 | pr_debug("isochronous relief time: %d\n", data->irt); | |
772 | pr_debug("maximum voltage step: %d - 0x%x\n", mvs, data->vidmvs); | |
1da177e4 | 773 | |
2d06d8c4 | 774 | pr_debug("numpst: 0x%x\n", psb->num_tables); |
1da177e4 | 775 | cpst = psb->num_tables; |
0e64a0c9 DJ |
776 | if ((psb->cpuid == 0x00000fc0) || |
777 | (psb->cpuid == 0x00000fe0)) { | |
1da177e4 | 778 | thiscpuid = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); |
0e64a0c9 DJ |
779 | if ((thiscpuid == 0x00000fc0) || |
780 | (thiscpuid == 0x00000fe0)) | |
1da177e4 | 781 | cpst = 1; |
1da177e4 LT |
782 | } |
783 | if (cpst != 1) { | |
2fd47094 | 784 | printk(KERN_ERR FW_BUG PFX "numpst must be 1\n"); |
1da177e4 LT |
785 | return -ENODEV; |
786 | } | |
787 | ||
788 | data->plllock = psb->plllocktime; | |
2d06d8c4 DB |
789 | pr_debug("plllocktime: 0x%x (units 1us)\n", psb->plllocktime); |
790 | pr_debug("maxfid: 0x%x\n", psb->maxfid); | |
791 | pr_debug("maxvid: 0x%x\n", psb->maxvid); | |
1da177e4 LT |
792 | maxvid = psb->maxvid; |
793 | ||
794 | data->numps = psb->numps; | |
2d06d8c4 | 795 | pr_debug("numpstates: 0x%x\n", data->numps); |
0e64a0c9 DJ |
796 | return fill_powernow_table(data, |
797 | (struct pst_s *)(psb+1), maxvid); | |
1da177e4 LT |
798 | } |
799 | /* | |
800 | * If you see this message, complain to BIOS manufacturer. If | |
801 | * he tells you "we do not support Linux" or some similar | |
802 | * nonsense, remember that Windows 2000 uses the same legacy | |
803 | * mechanism that the old Linux PSB driver uses. Tell them it | |
804 | * is broken with Windows 2000. | |
805 | * | |
806 | * The reference to the AMD documentation is chapter 9 in the | |
807 | * BIOS and Kernel Developer's Guide, which is available on | |
808 | * www.amd.com | |
809 | */ | |
79cc56af | 810 | printk(KERN_ERR FW_BUG PFX "No PSB or ACPI _PSS objects\n"); |
298decfb MR |
811 | printk(KERN_ERR PFX "Make sure that your BIOS is up to date" |
812 | " and Cool'N'Quiet support is enabled in BIOS setup\n"); | |
1da177e4 LT |
813 | return -ENODEV; |
814 | } | |
815 | ||
0e64a0c9 DJ |
816 | static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, |
817 | unsigned int index) | |
1da177e4 | 818 | { |
439913ff | 819 | u64 control; |
0e64a0c9 | 820 | |
f607e3a0 | 821 | if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE)) |
1da177e4 LT |
822 | return; |
823 | ||
21335d02 LH |
824 | control = data->acpi_data.states[index].control; |
825 | data->irt = (control >> IRT_SHIFT) & IRT_MASK; | |
826 | data->rvo = (control >> RVO_SHIFT) & RVO_MASK; | |
827 | data->exttype = (control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; | |
828 | data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK; | |
829 | data->vidmvs = 1 << ((control >> MVS_SHIFT) & MVS_MASK); | |
830 | data->vstable = (control >> VST_SHIFT) & VST_MASK; | |
831 | } | |
1da177e4 LT |
832 | |
833 | static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) | |
834 | { | |
1da177e4 | 835 | struct cpufreq_frequency_table *powernow_table; |
2fdf66b4 | 836 | int ret_val = -ENODEV; |
439913ff | 837 | u64 control, status; |
1da177e4 | 838 | |
f607e3a0 | 839 | if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) { |
2d06d8c4 | 840 | pr_debug("register performance failed: bad ACPI data\n"); |
1da177e4 LT |
841 | return -EIO; |
842 | } | |
843 | ||
844 | /* verify the data contained in the ACPI structures */ | |
f607e3a0 | 845 | if (data->acpi_data.state_count <= 1) { |
2d06d8c4 | 846 | pr_debug("No ACPI P-States\n"); |
1da177e4 LT |
847 | goto err_out; |
848 | } | |
849 | ||
2c701b10 DJ |
850 | control = data->acpi_data.control_register.space_id; |
851 | status = data->acpi_data.status_register.space_id; | |
852 | ||
853 | if ((control != ACPI_ADR_SPACE_FIXED_HARDWARE) || | |
854 | (status != ACPI_ADR_SPACE_FIXED_HARDWARE)) { | |
2d06d8c4 | 855 | pr_debug("Invalid control/status registers (%llx - %llx)\n", |
2c701b10 | 856 | control, status); |
1da177e4 LT |
857 | goto err_out; |
858 | } | |
859 | ||
860 | /* fill in data->powernow_table */ | |
861 | powernow_table = kmalloc((sizeof(struct cpufreq_frequency_table) | |
f607e3a0 | 862 | * (data->acpi_data.state_count + 1)), GFP_KERNEL); |
1da177e4 | 863 | if (!powernow_table) { |
2d06d8c4 | 864 | pr_debug("powernow_table memory alloc failure\n"); |
1da177e4 LT |
865 | goto err_out; |
866 | } | |
867 | ||
db39d552 ML |
868 | /* fill in data */ |
869 | data->numps = data->acpi_data.state_count; | |
870 | powernow_k8_acpi_pst_values(data, 0); | |
871 | ||
e7bdd7a5 | 872 | if (cpu_family == CPU_HW_PSTATE) |
1f729e06 DJ |
873 | ret_val = fill_powernow_table_pstate(data, powernow_table); |
874 | else | |
875 | ret_val = fill_powernow_table_fidvid(data, powernow_table); | |
876 | if (ret_val) | |
877 | goto err_out_mem; | |
878 | ||
0e64a0c9 DJ |
879 | powernow_table[data->acpi_data.state_count].frequency = |
880 | CPUFREQ_TABLE_END; | |
f607e3a0 | 881 | powernow_table[data->acpi_data.state_count].index = 0; |
1f729e06 DJ |
882 | data->powernow_table = powernow_table; |
883 | ||
7ad728f9 | 884 | if (cpumask_first(cpu_core_mask(data->cpu)) == data->cpu) |
2e497620 | 885 | print_basics(data); |
1f729e06 DJ |
886 | |
887 | /* notify BIOS that we exist */ | |
888 | acpi_processor_notify_smm(THIS_MODULE); | |
889 | ||
eaa95840 | 890 | if (!zalloc_cpumask_var(&data->acpi_data.shared_cpu_map, GFP_KERNEL)) { |
2fdf66b4 RR |
891 | printk(KERN_ERR PFX |
892 | "unable to alloc powernow_k8_data cpumask\n"); | |
893 | ret_val = -ENOMEM; | |
894 | goto err_out_mem; | |
895 | } | |
896 | ||
1f729e06 DJ |
897 | return 0; |
898 | ||
899 | err_out_mem: | |
900 | kfree(powernow_table); | |
901 | ||
902 | err_out: | |
f607e3a0 | 903 | acpi_processor_unregister_performance(&data->acpi_data, data->cpu); |
1f729e06 | 904 | |
0e64a0c9 DJ |
905 | /* data->acpi_data.state_count informs us at ->exit() |
906 | * whether ACPI was used */ | |
f607e3a0 | 907 | data->acpi_data.state_count = 0; |
1f729e06 | 908 | |
2fdf66b4 | 909 | return ret_val; |
1f729e06 DJ |
910 | } |
911 | ||
0e64a0c9 DJ |
912 | static int fill_powernow_table_pstate(struct powernow_k8_data *data, |
913 | struct cpufreq_frequency_table *powernow_table) | |
1f729e06 DJ |
914 | { |
915 | int i; | |
c5829cd0 | 916 | u32 hi = 0, lo = 0; |
b30d3304 BP |
917 | rdmsr(MSR_PSTATE_CUR_LIMIT, lo, hi); |
918 | data->max_hw_pstate = (lo & HW_PSTATE_MAX_MASK) >> HW_PSTATE_MAX_SHIFT; | |
1f729e06 | 919 | |
f607e3a0 | 920 | for (i = 0; i < data->acpi_data.state_count; i++) { |
1f729e06 | 921 | u32 index; |
1f729e06 | 922 | |
f607e3a0 | 923 | index = data->acpi_data.states[i].control & HW_PSTATE_MASK; |
c5829cd0 | 924 | if (index > data->max_hw_pstate) { |
0e64a0c9 DJ |
925 | printk(KERN_ERR PFX "invalid pstate %d - " |
926 | "bad value %d.\n", i, index); | |
927 | printk(KERN_ERR PFX "Please report to BIOS " | |
928 | "manufacturer\n"); | |
f0adb134 | 929 | invalidate_entry(powernow_table, i); |
c5829cd0 | 930 | continue; |
1f729e06 | 931 | } |
a8eb2848 AH |
932 | |
933 | ps_to_as[index] = i; | |
934 | ||
ca446d06 | 935 | /* Frequency may be rounded for these */ |
67937064 ML |
936 | if ((boot_cpu_data.x86 == 0x10 && boot_cpu_data.x86_model < 10) |
937 | || boot_cpu_data.x86 == 0x11) { | |
201bf0f1 AH |
938 | |
939 | rdmsr(MSR_PSTATE_DEF_BASE + index, lo, hi); | |
940 | if (!(hi & HW_PSTATE_VALID_MASK)) { | |
941 | pr_debug("invalid pstate %d, ignoring\n", index); | |
942 | invalidate_entry(powernow_table, i); | |
943 | continue; | |
944 | } | |
945 | ||
ca446d06 AH |
946 | powernow_table[i].frequency = |
947 | freq_from_fid_did(lo & 0x3f, (lo >> 6) & 7); | |
948 | } else | |
949 | powernow_table[i].frequency = | |
950 | data->acpi_data.states[i].core_frequency * 1000; | |
201bf0f1 AH |
951 | |
952 | powernow_table[i].index = index; | |
1f729e06 DJ |
953 | } |
954 | return 0; | |
955 | } | |
956 | ||
0e64a0c9 DJ |
957 | static int fill_powernow_table_fidvid(struct powernow_k8_data *data, |
958 | struct cpufreq_frequency_table *powernow_table) | |
1f729e06 DJ |
959 | { |
960 | int i; | |
0e64a0c9 | 961 | |
f607e3a0 | 962 | for (i = 0; i < data->acpi_data.state_count; i++) { |
094ce7fd DJ |
963 | u32 fid; |
964 | u32 vid; | |
0e64a0c9 | 965 | u32 freq, index; |
439913ff | 966 | u64 status, control; |
094ce7fd DJ |
967 | |
968 | if (data->exttype) { | |
0e64a0c9 DJ |
969 | status = data->acpi_data.states[i].status; |
970 | fid = status & EXT_FID_MASK; | |
971 | vid = (status >> VID_SHIFT) & EXT_VID_MASK; | |
841e40b3 | 972 | } else { |
0e64a0c9 DJ |
973 | control = data->acpi_data.states[i].control; |
974 | fid = control & FID_MASK; | |
975 | vid = (control >> VID_SHIFT) & VID_MASK; | |
841e40b3 | 976 | } |
1da177e4 | 977 | |
2d06d8c4 | 978 | pr_debug(" %d : fid 0x%x, vid 0x%x\n", i, fid, vid); |
1da177e4 | 979 | |
0e64a0c9 DJ |
980 | index = fid | (vid<<8); |
981 | powernow_table[i].index = index; | |
982 | ||
983 | freq = find_khz_freq_from_fid(fid); | |
984 | powernow_table[i].frequency = freq; | |
1da177e4 LT |
985 | |
986 | /* verify frequency is OK */ | |
0e64a0c9 | 987 | if ((freq > (MAX_FREQ * 1000)) || (freq < (MIN_FREQ * 1000))) { |
2d06d8c4 | 988 | pr_debug("invalid freq %u kHz, ignoring\n", freq); |
f0adb134 | 989 | invalidate_entry(powernow_table, i); |
1da177e4 LT |
990 | continue; |
991 | } | |
992 | ||
0e64a0c9 DJ |
993 | /* verify voltage is OK - |
994 | * BIOSs are using "off" to indicate invalid */ | |
841e40b3 | 995 | if (vid == VID_OFF) { |
2d06d8c4 | 996 | pr_debug("invalid vid %u, ignoring\n", vid); |
f0adb134 | 997 | invalidate_entry(powernow_table, i); |
1da177e4 LT |
998 | continue; |
999 | } | |
1000 | ||
0e64a0c9 DJ |
1001 | if (freq != (data->acpi_data.states[i].core_frequency * 1000)) { |
1002 | printk(KERN_INFO PFX "invalid freq entries " | |
1003 | "%u kHz vs. %u kHz\n", freq, | |
1004 | (unsigned int) | |
1005 | (data->acpi_data.states[i].core_frequency | |
1006 | * 1000)); | |
f0adb134 | 1007 | invalidate_entry(powernow_table, i); |
1da177e4 LT |
1008 | continue; |
1009 | } | |
1010 | } | |
1da177e4 | 1011 | return 0; |
1da177e4 LT |
1012 | } |
1013 | ||
1014 | static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) | |
1015 | { | |
f607e3a0 | 1016 | if (data->acpi_data.state_count) |
0e64a0c9 DJ |
1017 | acpi_processor_unregister_performance(&data->acpi_data, |
1018 | data->cpu); | |
2fdf66b4 | 1019 | free_cpumask_var(data->acpi_data.shared_cpu_map); |
1da177e4 LT |
1020 | } |
1021 | ||
732553e5 ML |
1022 | static int get_transition_latency(struct powernow_k8_data *data) |
1023 | { | |
1024 | int max_latency = 0; | |
1025 | int i; | |
1026 | for (i = 0; i < data->acpi_data.state_count; i++) { | |
1027 | int cur_latency = data->acpi_data.states[i].transition_latency | |
1028 | + data->acpi_data.states[i].bus_master_latency; | |
1029 | if (cur_latency > max_latency) | |
1030 | max_latency = cur_latency; | |
1031 | } | |
86e13684 TR |
1032 | if (max_latency == 0) { |
1033 | /* | |
c2f4a2c6 BP |
1034 | * Fam 11h and later may return 0 as transition latency. This |
1035 | * is intended and means "very fast". While cpufreq core and | |
1036 | * governors currently can handle that gracefully, better set it | |
1037 | * to 1 to avoid problems in the future. | |
86e13684 | 1038 | */ |
c2f4a2c6 | 1039 | if (boot_cpu_data.x86 < 0x11) |
86e13684 TR |
1040 | printk(KERN_ERR FW_WARN PFX "Invalid zero transition " |
1041 | "latency\n"); | |
1042 | max_latency = 1; | |
1043 | } | |
732553e5 ML |
1044 | /* value in usecs, needs to be in nanoseconds */ |
1045 | return 1000 * max_latency; | |
1046 | } | |
1047 | ||
1da177e4 | 1048 | /* Take a frequency, and issue the fid/vid transition command */ |
0e64a0c9 DJ |
1049 | static int transition_frequency_fidvid(struct powernow_k8_data *data, |
1050 | unsigned int index) | |
1da177e4 | 1051 | { |
1f729e06 DJ |
1052 | u32 fid = 0; |
1053 | u32 vid = 0; | |
065b807c | 1054 | int res, i; |
1da177e4 LT |
1055 | struct cpufreq_freqs freqs; |
1056 | ||
2d06d8c4 | 1057 | pr_debug("cpu %d transition to index %u\n", smp_processor_id(), index); |
1da177e4 | 1058 | |
1f729e06 | 1059 | /* fid/vid correctness check for k8 */ |
1da177e4 | 1060 | /* fid are the lower 8 bits of the index we stored into |
1f729e06 DJ |
1061 | * the cpufreq frequency table in find_psb_table, vid |
1062 | * are the upper 8 bits. | |
1da177e4 | 1063 | */ |
1da177e4 LT |
1064 | fid = data->powernow_table[index].index & 0xFF; |
1065 | vid = (data->powernow_table[index].index & 0xFF00) >> 8; | |
1066 | ||
2d06d8c4 | 1067 | pr_debug("table matched fid 0x%x, giving vid 0x%x\n", fid, vid); |
1da177e4 LT |
1068 | |
1069 | if (query_current_values_with_pending_wait(data)) | |
1070 | return 1; | |
1071 | ||
1072 | if ((data->currvid == vid) && (data->currfid == fid)) { | |
2d06d8c4 | 1073 | pr_debug("target matches current values (fid 0x%x, vid 0x%x)\n", |
1da177e4 LT |
1074 | fid, vid); |
1075 | return 0; | |
1076 | } | |
1077 | ||
2d06d8c4 | 1078 | pr_debug("cpu %d, changing to fid 0x%x, vid 0x%x\n", |
1da177e4 | 1079 | smp_processor_id(), fid, vid); |
1da177e4 LT |
1080 | freqs.old = find_khz_freq_from_fid(data->currfid); |
1081 | freqs.new = find_khz_freq_from_fid(fid); | |
1f729e06 | 1082 | |
8e7c2597 | 1083 | for_each_cpu(i, data->available_cores) { |
065b807c DJ |
1084 | freqs.cpu = i; |
1085 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
1086 | } | |
1da177e4 | 1087 | |
1da177e4 | 1088 | res = transition_fid_vid(data, fid, vid); |
a9d3d206 KRW |
1089 | if (res) |
1090 | return res; | |
1091 | ||
1da177e4 | 1092 | freqs.new = find_khz_freq_from_fid(data->currfid); |
1f729e06 | 1093 | |
8e7c2597 | 1094 | for_each_cpu(i, data->available_cores) { |
1f729e06 DJ |
1095 | freqs.cpu = i; |
1096 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
1097 | } | |
1098 | return res; | |
1099 | } | |
1100 | ||
1101 | /* Take a frequency, and issue the hardware pstate transition command */ | |
0e64a0c9 DJ |
1102 | static int transition_frequency_pstate(struct powernow_k8_data *data, |
1103 | unsigned int index) | |
1f729e06 | 1104 | { |
1f729e06 DJ |
1105 | u32 pstate = 0; |
1106 | int res, i; | |
1107 | struct cpufreq_freqs freqs; | |
1108 | ||
2d06d8c4 | 1109 | pr_debug("cpu %d transition to index %u\n", smp_processor_id(), index); |
1f729e06 | 1110 | |
c5829cd0 | 1111 | /* get MSR index for hardware pstate transition */ |
1f729e06 | 1112 | pstate = index & HW_PSTATE_MASK; |
c5829cd0 | 1113 | if (pstate > data->max_hw_pstate) |
fbb5b89e KRW |
1114 | return -EINVAL; |
1115 | ||
0e64a0c9 DJ |
1116 | freqs.old = find_khz_freq_from_pstate(data->powernow_table, |
1117 | data->currpstate); | |
c5829cd0 | 1118 | freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); |
1f729e06 | 1119 | |
8e7c2597 | 1120 | for_each_cpu(i, data->available_cores) { |
1f729e06 DJ |
1121 | freqs.cpu = i; |
1122 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | |
1123 | } | |
1124 | ||
1125 | res = transition_pstate(data, pstate); | |
c5829cd0 | 1126 | freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); |
1f729e06 | 1127 | |
8e7c2597 | 1128 | for_each_cpu(i, data->available_cores) { |
065b807c DJ |
1129 | freqs.cpu = i; |
1130 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | |
2e3f8faa | 1131 | } |
1da177e4 LT |
1132 | return res; |
1133 | } | |
1134 | ||
1135 | /* Driver entry point to switch to the target frequency */ | |
0e64a0c9 DJ |
1136 | static int powernowk8_target(struct cpufreq_policy *pol, |
1137 | unsigned targfreq, unsigned relation) | |
1da177e4 | 1138 | { |
b8cbe7e8 | 1139 | cpumask_var_t oldmask; |
2c6b8c03 | 1140 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
9180053c AB |
1141 | u32 checkfid; |
1142 | u32 checkvid; | |
1da177e4 LT |
1143 | unsigned int newstate; |
1144 | int ret = -EIO; | |
1145 | ||
4211a303 JS |
1146 | if (!data) |
1147 | return -EINVAL; | |
1148 | ||
9180053c AB |
1149 | checkfid = data->currfid; |
1150 | checkvid = data->currvid; | |
1151 | ||
b8cbe7e8 RR |
1152 | /* only run on specific CPU from here on. */ |
1153 | /* This is poor form: use a workqueue or smp_call_function_single */ | |
1154 | if (!alloc_cpumask_var(&oldmask, GFP_KERNEL)) | |
1155 | return -ENOMEM; | |
1156 | ||
a4636818 | 1157 | cpumask_copy(oldmask, tsk_cpus_allowed(current)); |
b8cbe7e8 | 1158 | set_cpus_allowed_ptr(current, cpumask_of(pol->cpu)); |
1da177e4 LT |
1159 | |
1160 | if (smp_processor_id() != pol->cpu) { | |
8aae8284 | 1161 | printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu); |
1da177e4 LT |
1162 | goto err_out; |
1163 | } | |
1164 | ||
1165 | if (pending_bit_stuck()) { | |
1166 | printk(KERN_ERR PFX "failing targ, change pending bit set\n"); | |
1167 | goto err_out; | |
1168 | } | |
1169 | ||
2d06d8c4 | 1170 | pr_debug("targ: cpu %d, %d kHz, min %d, max %d, relation %d\n", |
1da177e4 LT |
1171 | pol->cpu, targfreq, pol->min, pol->max, relation); |
1172 | ||
83844510 | 1173 | if (query_current_values_with_pending_wait(data)) |
1da177e4 | 1174 | goto err_out; |
1da177e4 | 1175 | |
c5829cd0 | 1176 | if (cpu_family != CPU_HW_PSTATE) { |
2d06d8c4 | 1177 | pr_debug("targ: curr fid 0x%x, vid 0x%x\n", |
1da177e4 LT |
1178 | data->currfid, data->currvid); |
1179 | ||
0e64a0c9 DJ |
1180 | if ((checkvid != data->currvid) || |
1181 | (checkfid != data->currfid)) { | |
1f729e06 | 1182 | printk(KERN_INFO PFX |
0e64a0c9 DJ |
1183 | "error - out of sync, fix 0x%x 0x%x, " |
1184 | "vid 0x%x 0x%x\n", | |
1185 | checkfid, data->currfid, | |
1186 | checkvid, data->currvid); | |
1f729e06 | 1187 | } |
1da177e4 LT |
1188 | } |
1189 | ||
0e64a0c9 DJ |
1190 | if (cpufreq_frequency_table_target(pol, data->powernow_table, |
1191 | targfreq, relation, &newstate)) | |
1da177e4 LT |
1192 | goto err_out; |
1193 | ||
14cc3e2b | 1194 | mutex_lock(&fidvid_mutex); |
065b807c | 1195 | |
1da177e4 LT |
1196 | powernow_k8_acpi_pst_values(data, newstate); |
1197 | ||
e7bdd7a5 | 1198 | if (cpu_family == CPU_HW_PSTATE) |
a8eb2848 AH |
1199 | ret = transition_frequency_pstate(data, |
1200 | data->powernow_table[newstate].index); | |
1f729e06 DJ |
1201 | else |
1202 | ret = transition_frequency_fidvid(data, newstate); | |
1203 | if (ret) { | |
1da177e4 LT |
1204 | printk(KERN_ERR PFX "transition frequency failed\n"); |
1205 | ret = 1; | |
14cc3e2b | 1206 | mutex_unlock(&fidvid_mutex); |
1da177e4 LT |
1207 | goto err_out; |
1208 | } | |
14cc3e2b | 1209 | mutex_unlock(&fidvid_mutex); |
065b807c | 1210 | |
e7bdd7a5 | 1211 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 | 1212 | pol->cur = find_khz_freq_from_pstate(data->powernow_table, |
a8eb2848 | 1213 | data->powernow_table[newstate].index); |
1f729e06 DJ |
1214 | else |
1215 | pol->cur = find_khz_freq_from_fid(data->currfid); | |
1da177e4 LT |
1216 | ret = 0; |
1217 | ||
1218 | err_out: | |
b8cbe7e8 RR |
1219 | set_cpus_allowed_ptr(current, oldmask); |
1220 | free_cpumask_var(oldmask); | |
1da177e4 LT |
1221 | return ret; |
1222 | } | |
1223 | ||
1224 | /* Driver entry point to verify the policy and range of frequencies */ | |
1225 | static int powernowk8_verify(struct cpufreq_policy *pol) | |
1226 | { | |
2c6b8c03 | 1227 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
1da177e4 | 1228 | |
4211a303 JS |
1229 | if (!data) |
1230 | return -EINVAL; | |
1231 | ||
1da177e4 LT |
1232 | return cpufreq_frequency_table_verify(pol, data->powernow_table); |
1233 | } | |
1234 | ||
1ff6e97f RR |
1235 | struct init_on_cpu { |
1236 | struct powernow_k8_data *data; | |
1237 | int rc; | |
1238 | }; | |
1239 | ||
1240 | static void __cpuinit powernowk8_cpu_init_on_cpu(void *_init_on_cpu) | |
1241 | { | |
1242 | struct init_on_cpu *init_on_cpu = _init_on_cpu; | |
1243 | ||
1244 | if (pending_bit_stuck()) { | |
1245 | printk(KERN_ERR PFX "failing init, change pending bit set\n"); | |
1246 | init_on_cpu->rc = -ENODEV; | |
1247 | return; | |
1248 | } | |
1249 | ||
1250 | if (query_current_values_with_pending_wait(init_on_cpu->data)) { | |
1251 | init_on_cpu->rc = -ENODEV; | |
1252 | return; | |
1253 | } | |
1254 | ||
1255 | if (cpu_family == CPU_OPTERON) | |
1256 | fidvid_msr_init(); | |
1257 | ||
1258 | init_on_cpu->rc = 0; | |
1259 | } | |
1260 | ||
1da177e4 | 1261 | /* per CPU init entry point to the driver */ |
aa41eb99 | 1262 | static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) |
1da177e4 | 1263 | { |
b394f1df AM |
1264 | static const char ACPI_PSS_BIOS_BUG_MSG[] = |
1265 | KERN_ERR FW_BUG PFX "No compatible ACPI _PSS objects found.\n" | |
ad361c98 | 1266 | FW_BUG PFX "Try again with latest BIOS.\n"; |
1da177e4 | 1267 | struct powernow_k8_data *data; |
1ff6e97f | 1268 | struct init_on_cpu init_on_cpu; |
d7fa706c | 1269 | int rc; |
a2fed573 | 1270 | struct cpuinfo_x86 *c = &cpu_data(pol->cpu); |
1da177e4 | 1271 | |
8aae8284 JS |
1272 | if (!cpu_online(pol->cpu)) |
1273 | return -ENODEV; | |
1274 | ||
1ff6e97f RR |
1275 | smp_call_function_single(pol->cpu, check_supported_cpu, &rc, 1); |
1276 | if (rc) | |
1da177e4 LT |
1277 | return -ENODEV; |
1278 | ||
bfdc708d | 1279 | data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL); |
1da177e4 LT |
1280 | if (!data) { |
1281 | printk(KERN_ERR PFX "unable to alloc powernow_k8_data"); | |
1282 | return -ENOMEM; | |
1283 | } | |
1da177e4 LT |
1284 | |
1285 | data->cpu = pol->cpu; | |
a266d9f1 | 1286 | data->currpstate = HW_PSTATE_INVALID; |
1da177e4 | 1287 | |
a0abd520 | 1288 | if (powernow_k8_cpu_init_acpi(data)) { |
1da177e4 | 1289 | /* |
0d2eb44f | 1290 | * Use the PSB BIOS structure. This is only available on |
1da177e4 LT |
1291 | * an UP version, and is deprecated by AMD. |
1292 | */ | |
9ed059e1 | 1293 | if (num_online_cpus() != 1) { |
df182977 | 1294 | printk_once(ACPI_PSS_BIOS_BUG_MSG); |
0cb8bc25 | 1295 | goto err_out; |
1da177e4 LT |
1296 | } |
1297 | if (pol->cpu != 0) { | |
2fd47094 TR |
1298 | printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for " |
1299 | "CPU other than CPU0. Complain to your BIOS " | |
1300 | "vendor.\n"); | |
0cb8bc25 | 1301 | goto err_out; |
1da177e4 LT |
1302 | } |
1303 | rc = find_psb_table(data); | |
0cb8bc25 DJ |
1304 | if (rc) |
1305 | goto err_out; | |
1306 | ||
732553e5 ML |
1307 | /* Take a crude guess here. |
1308 | * That guess was in microseconds, so multiply with 1000 */ | |
1309 | pol->cpuinfo.transition_latency = ( | |
1310 | ((data->rvo + 8) * data->vstable * VST_UNITS_20US) + | |
1311 | ((1 << data->irt) * 30)) * 1000; | |
1312 | } else /* ACPI _PSS objects available */ | |
1313 | pol->cpuinfo.transition_latency = get_transition_latency(data); | |
1da177e4 LT |
1314 | |
1315 | /* only run on specific CPU from here on */ | |
1ff6e97f RR |
1316 | init_on_cpu.data = data; |
1317 | smp_call_function_single(data->cpu, powernowk8_cpu_init_on_cpu, | |
1318 | &init_on_cpu, 1); | |
1319 | rc = init_on_cpu.rc; | |
1320 | if (rc != 0) | |
1321 | goto err_out_exit_acpi; | |
1da177e4 | 1322 | |
f607e3a0 | 1323 | if (cpu_family == CPU_HW_PSTATE) |
835481d9 | 1324 | cpumask_copy(pol->cpus, cpumask_of(pol->cpu)); |
f607e3a0 | 1325 | else |
7ad728f9 | 1326 | cpumask_copy(pol->cpus, cpu_core_mask(pol->cpu)); |
835481d9 | 1327 | data->available_cores = pol->cpus; |
1da177e4 | 1328 | |
e7bdd7a5 | 1329 | if (cpu_family == CPU_HW_PSTATE) |
0e64a0c9 DJ |
1330 | pol->cur = find_khz_freq_from_pstate(data->powernow_table, |
1331 | data->currpstate); | |
1f729e06 DJ |
1332 | else |
1333 | pol->cur = find_khz_freq_from_fid(data->currfid); | |
2d06d8c4 | 1334 | pr_debug("policy current frequency %d kHz\n", pol->cur); |
1da177e4 LT |
1335 | |
1336 | /* min/max the cpu is capable of */ | |
1337 | if (cpufreq_frequency_table_cpuinfo(pol, data->powernow_table)) { | |
2fd47094 | 1338 | printk(KERN_ERR FW_BUG PFX "invalid powernow_table\n"); |
1da177e4 LT |
1339 | powernow_k8_cpu_exit_acpi(data); |
1340 | kfree(data->powernow_table); | |
1341 | kfree(data); | |
1342 | return -EINVAL; | |
1343 | } | |
1344 | ||
a2fed573 ML |
1345 | /* Check for APERF/MPERF support in hardware */ |
1346 | if (cpu_has(c, X86_FEATURE_APERFMPERF)) | |
1347 | cpufreq_amd64_driver.getavg = cpufreq_get_measured_perf; | |
1348 | ||
1da177e4 LT |
1349 | cpufreq_frequency_table_get_attr(data->powernow_table, pol->cpu); |
1350 | ||
e7bdd7a5 | 1351 | if (cpu_family == CPU_HW_PSTATE) |
2d06d8c4 | 1352 | pr_debug("cpu_init done, current pstate 0x%x\n", |
0e64a0c9 | 1353 | data->currpstate); |
1f729e06 | 1354 | else |
2d06d8c4 | 1355 | pr_debug("cpu_init done, current fid 0x%x, vid 0x%x\n", |
1f729e06 | 1356 | data->currfid, data->currvid); |
1da177e4 | 1357 | |
2c6b8c03 | 1358 | per_cpu(powernow_data, pol->cpu) = data; |
1da177e4 LT |
1359 | |
1360 | return 0; | |
1361 | ||
1ff6e97f | 1362 | err_out_exit_acpi: |
1da177e4 LT |
1363 | powernow_k8_cpu_exit_acpi(data); |
1364 | ||
0cb8bc25 | 1365 | err_out: |
1da177e4 LT |
1366 | kfree(data); |
1367 | return -ENODEV; | |
1368 | } | |
1369 | ||
0e64a0c9 | 1370 | static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol) |
1da177e4 | 1371 | { |
2c6b8c03 | 1372 | struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); |
1da177e4 LT |
1373 | |
1374 | if (!data) | |
1375 | return -EINVAL; | |
1376 | ||
1377 | powernow_k8_cpu_exit_acpi(data); | |
1378 | ||
1379 | cpufreq_frequency_table_put_attr(pol->cpu); | |
1380 | ||
1381 | kfree(data->powernow_table); | |
1382 | kfree(data); | |
557a701c | 1383 | per_cpu(powernow_data, pol->cpu) = NULL; |
1da177e4 LT |
1384 | |
1385 | return 0; | |
1386 | } | |
1387 | ||
1ff6e97f RR |
1388 | static void query_values_on_cpu(void *_err) |
1389 | { | |
1390 | int *err = _err; | |
0a3aee0d | 1391 | struct powernow_k8_data *data = __this_cpu_read(powernow_data); |
1ff6e97f RR |
1392 | |
1393 | *err = query_current_values_with_pending_wait(data); | |
1394 | } | |
1395 | ||
0e64a0c9 | 1396 | static unsigned int powernowk8_get(unsigned int cpu) |
1da177e4 | 1397 | { |
e15bc455 | 1398 | struct powernow_k8_data *data = per_cpu(powernow_data, cpu); |
1da177e4 | 1399 | unsigned int khz = 0; |
1ff6e97f | 1400 | int err; |
eef5167e JS |
1401 | |
1402 | if (!data) | |
557a701c | 1403 | return 0; |
eef5167e | 1404 | |
1ff6e97f RR |
1405 | smp_call_function_single(cpu, query_values_on_cpu, &err, true); |
1406 | if (err) | |
1da177e4 LT |
1407 | goto out; |
1408 | ||
58389a86 | 1409 | if (cpu_family == CPU_HW_PSTATE) |
fc0e4748 MT |
1410 | khz = find_khz_freq_from_pstate(data->powernow_table, |
1411 | data->currpstate); | |
58389a86 JD |
1412 | else |
1413 | khz = find_khz_freq_from_fid(data->currfid); | |
1414 | ||
1da177e4 | 1415 | |
b9111b7b | 1416 | out: |
1da177e4 LT |
1417 | return khz; |
1418 | } | |
1419 | ||
73860c6b BP |
1420 | static void _cpb_toggle_msrs(bool t) |
1421 | { | |
1422 | int cpu; | |
1423 | ||
1424 | get_online_cpus(); | |
1425 | ||
1426 | rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs); | |
1427 | ||
1428 | for_each_cpu(cpu, cpu_online_mask) { | |
1429 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
1430 | if (t) | |
1431 | reg->l &= ~BIT(25); | |
1432 | else | |
1433 | reg->l |= BIT(25); | |
1434 | } | |
1435 | wrmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs); | |
1436 | ||
1437 | put_online_cpus(); | |
1438 | } | |
1439 | ||
1440 | /* | |
1441 | * Switch on/off core performance boosting. | |
1442 | * | |
1443 | * 0=disable | |
1444 | * 1=enable. | |
1445 | */ | |
1446 | static void cpb_toggle(bool t) | |
1447 | { | |
1448 | if (!cpb_capable) | |
1449 | return; | |
1450 | ||
1451 | if (t && !cpb_enabled) { | |
1452 | cpb_enabled = true; | |
1453 | _cpb_toggle_msrs(t); | |
1454 | printk(KERN_INFO PFX "Core Boosting enabled.\n"); | |
1455 | } else if (!t && cpb_enabled) { | |
1456 | cpb_enabled = false; | |
1457 | _cpb_toggle_msrs(t); | |
1458 | printk(KERN_INFO PFX "Core Boosting disabled.\n"); | |
1459 | } | |
1460 | } | |
1461 | ||
1462 | static ssize_t store_cpb(struct cpufreq_policy *policy, const char *buf, | |
1463 | size_t count) | |
1464 | { | |
1465 | int ret = -EINVAL; | |
1466 | unsigned long val = 0; | |
1467 | ||
1468 | ret = strict_strtoul(buf, 10, &val); | |
1469 | if (!ret && (val == 0 || val == 1) && cpb_capable) | |
1470 | cpb_toggle(val); | |
1471 | else | |
1472 | return -EINVAL; | |
1473 | ||
1474 | return count; | |
1475 | } | |
1476 | ||
1477 | static ssize_t show_cpb(struct cpufreq_policy *policy, char *buf) | |
1478 | { | |
1479 | return sprintf(buf, "%u\n", cpb_enabled); | |
1480 | } | |
1481 | ||
1482 | #define define_one_rw(_name) \ | |
1483 | static struct freq_attr _name = \ | |
1484 | __ATTR(_name, 0644, show_##_name, store_##_name) | |
1485 | ||
1486 | define_one_rw(cpb); | |
1487 | ||
0e64a0c9 | 1488 | static struct freq_attr *powernow_k8_attr[] = { |
1da177e4 | 1489 | &cpufreq_freq_attr_scaling_available_freqs, |
73860c6b | 1490 | &cpb, |
1da177e4 LT |
1491 | NULL, |
1492 | }; | |
1493 | ||
221dee28 | 1494 | static struct cpufreq_driver cpufreq_amd64_driver = { |
e2f74f35 TR |
1495 | .verify = powernowk8_verify, |
1496 | .target = powernowk8_target, | |
1497 | .bios_limit = acpi_processor_get_bios_limit, | |
1498 | .init = powernowk8_cpu_init, | |
1499 | .exit = __devexit_p(powernowk8_cpu_exit), | |
1500 | .get = powernowk8_get, | |
1501 | .name = "powernow-k8", | |
1502 | .owner = THIS_MODULE, | |
1503 | .attr = powernow_k8_attr, | |
1da177e4 LT |
1504 | }; |
1505 | ||
73860c6b BP |
1506 | /* |
1507 | * Clear the boost-disable flag on the CPU_DOWN path so that this cpu | |
1508 | * cannot block the remaining ones from boosting. On the CPU_UP path we | |
1509 | * simply keep the boost-disable flag in sync with the current global | |
1510 | * state. | |
1511 | */ | |
fe501f1e BP |
1512 | static int cpb_notify(struct notifier_block *nb, unsigned long action, |
1513 | void *hcpu) | |
73860c6b BP |
1514 | { |
1515 | unsigned cpu = (long)hcpu; | |
1516 | u32 lo, hi; | |
1517 | ||
1518 | switch (action) { | |
1519 | case CPU_UP_PREPARE: | |
1520 | case CPU_UP_PREPARE_FROZEN: | |
1521 | ||
1522 | if (!cpb_enabled) { | |
1523 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
1524 | lo |= BIT(25); | |
1525 | wrmsr_on_cpu(cpu, MSR_K7_HWCR, lo, hi); | |
1526 | } | |
1527 | break; | |
1528 | ||
1529 | case CPU_DOWN_PREPARE: | |
1530 | case CPU_DOWN_PREPARE_FROZEN: | |
1531 | rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi); | |
1532 | lo &= ~BIT(25); | |
1533 | wrmsr_on_cpu(cpu, MSR_K7_HWCR, lo, hi); | |
1534 | break; | |
1535 | ||
1536 | default: | |
1537 | break; | |
1538 | } | |
1539 | ||
1540 | return NOTIFY_OK; | |
1541 | } | |
1542 | ||
fe501f1e | 1543 | static struct notifier_block cpb_nb = { |
73860c6b BP |
1544 | .notifier_call = cpb_notify, |
1545 | }; | |
1546 | ||
1da177e4 | 1547 | /* driver entry point for init */ |
aa41eb99 | 1548 | static int __cpuinit powernowk8_init(void) |
1da177e4 | 1549 | { |
73860c6b | 1550 | unsigned int i, supported_cpus = 0, cpu; |
ac818314 | 1551 | int rv; |
1da177e4 | 1552 | |
a7201156 | 1553 | for_each_online_cpu(i) { |
1ff6e97f RR |
1554 | int rc; |
1555 | smp_call_function_single(i, check_supported_cpu, &rc, 1); | |
1556 | if (rc == 0) | |
1da177e4 LT |
1557 | supported_cpus++; |
1558 | } | |
1559 | ||
73860c6b BP |
1560 | if (supported_cpus != num_online_cpus()) |
1561 | return -ENODEV; | |
1562 | ||
1563 | printk(KERN_INFO PFX "Found %d %s (%d cpu cores) (" VERSION ")\n", | |
1564 | num_online_nodes(), boot_cpu_data.x86_model_id, supported_cpus); | |
1565 | ||
1566 | if (boot_cpu_has(X86_FEATURE_CPB)) { | |
1567 | ||
1568 | cpb_capable = true; | |
1569 | ||
73860c6b BP |
1570 | msrs = msrs_alloc(); |
1571 | if (!msrs) { | |
1572 | printk(KERN_ERR "%s: Error allocating msrs!\n", __func__); | |
1573 | return -ENOMEM; | |
1574 | } | |
1575 | ||
a536b126 DJ |
1576 | register_cpu_notifier(&cpb_nb); |
1577 | ||
73860c6b BP |
1578 | rdmsr_on_cpus(cpu_online_mask, MSR_K7_HWCR, msrs); |
1579 | ||
1580 | for_each_cpu(cpu, cpu_online_mask) { | |
1581 | struct msr *reg = per_cpu_ptr(msrs, cpu); | |
1582 | cpb_enabled |= !(!!(reg->l & BIT(25))); | |
1583 | } | |
1584 | ||
1585 | printk(KERN_INFO PFX "Core Performance Boosting: %s.\n", | |
1586 | (cpb_enabled ? "on" : "off")); | |
1da177e4 LT |
1587 | } |
1588 | ||
ac818314 NB |
1589 | rv = cpufreq_register_driver(&cpufreq_amd64_driver); |
1590 | if (rv < 0 && boot_cpu_has(X86_FEATURE_CPB)) { | |
1591 | unregister_cpu_notifier(&cpb_nb); | |
1592 | msrs_free(msrs); | |
1593 | msrs = NULL; | |
1594 | } | |
1595 | return rv; | |
1da177e4 LT |
1596 | } |
1597 | ||
1598 | /* driver entry point for term */ | |
1599 | static void __exit powernowk8_exit(void) | |
1600 | { | |
2d06d8c4 | 1601 | pr_debug("exit\n"); |
1da177e4 | 1602 | |
73860c6b BP |
1603 | if (boot_cpu_has(X86_FEATURE_CPB)) { |
1604 | msrs_free(msrs); | |
1605 | msrs = NULL; | |
1606 | ||
1607 | unregister_cpu_notifier(&cpb_nb); | |
1608 | } | |
1609 | ||
1da177e4 LT |
1610 | cpufreq_unregister_driver(&cpufreq_amd64_driver); |
1611 | } | |
1612 | ||
0e64a0c9 DJ |
1613 | MODULE_AUTHOR("Paul Devriendt <paul.devriendt@amd.com> and " |
1614 | "Mark Langsdorf <mark.langsdorf@amd.com>"); | |
1da177e4 LT |
1615 | MODULE_DESCRIPTION("AMD Athlon 64 and Opteron processor frequency driver."); |
1616 | MODULE_LICENSE("GPL"); | |
1617 | ||
1618 | late_initcall(powernowk8_init); | |
1619 | module_exit(powernowk8_exit); |