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b3d627a5 VS |
1 | /* |
2 | * POWERNV cpufreq driver for the IBM POWER processors | |
3 | * | |
4 | * (C) Copyright IBM 2014 | |
5 | * | |
6 | * Author: Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #define pr_fmt(fmt) "powernv-cpufreq: " fmt | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/sysfs.h> | |
24 | #include <linux/cpumask.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/cpufreq.h> | |
27 | #include <linux/smp.h> | |
28 | #include <linux/of.h> | |
cf30af76 | 29 | #include <linux/reboot.h> |
053819e0 | 30 | #include <linux/slab.h> |
6d167a44 | 31 | #include <linux/cpu.h> |
332f0a01 | 32 | #include <linux/hashtable.h> |
c89f2682 | 33 | #include <trace/events/power.h> |
b3d627a5 VS |
34 | |
35 | #include <asm/cputhreads.h> | |
6174bac8 | 36 | #include <asm/firmware.h> |
b3d627a5 | 37 | #include <asm/reg.h> |
f3cae355 | 38 | #include <asm/smp.h> /* Required for cpu_sibling_mask() in UP configs */ |
cb166fa9 | 39 | #include <asm/opal.h> |
eaa2c3ae | 40 | #include <linux/timer.h> |
b3d627a5 | 41 | |
332f0a01 GS |
42 | #define POWERNV_MAX_PSTATES_ORDER 8 |
43 | #define POWERNV_MAX_PSTATES (1UL << (POWERNV_MAX_PSTATES_ORDER)) | |
09a972d1 SB |
44 | #define PMSR_PSAFE_ENABLE (1UL << 30) |
45 | #define PMSR_SPR_EM_DISABLE (1UL << 31) | |
ee1f4a7d | 46 | #define MAX_PSTATE_SHIFT 32 |
20b15b76 AA |
47 | #define LPSTATE_SHIFT 48 |
48 | #define GPSTATE_SHIFT 56 | |
b3d627a5 | 49 | |
eaa2c3ae AA |
50 | #define MAX_RAMP_DOWN_TIME 5120 |
51 | /* | |
52 | * On an idle system we want the global pstate to ramp-down from max value to | |
53 | * min over a span of ~5 secs. Also we want it to initially ramp-down slowly and | |
54 | * then ramp-down rapidly later on. | |
55 | * | |
56 | * This gives a percentage rampdown for time elapsed in milliseconds. | |
57 | * ramp_down_percentage = ((ms * ms) >> 18) | |
58 | * ~= 3.8 * (sec * sec) | |
59 | * | |
60 | * At 0 ms ramp_down_percent = 0 | |
61 | * At 5120 ms ramp_down_percent = 100 | |
62 | */ | |
63 | #define ramp_down_percent(time) ((time * time) >> 18) | |
64 | ||
65 | /* Interval after which the timer is queued to bring down global pstate */ | |
66 | #define GPSTATE_TIMER_INTERVAL 2000 | |
67 | ||
68 | /** | |
69 | * struct global_pstate_info - Per policy data structure to maintain history of | |
70 | * global pstates | |
09ca4c9b AA |
71 | * @highest_lpstate_idx: The local pstate index from which we are |
72 | * ramping down | |
eaa2c3ae | 73 | * @elapsed_time: Time in ms spent in ramping down from |
09ca4c9b | 74 | * highest_lpstate_idx |
eaa2c3ae AA |
75 | * @last_sampled_time: Time from boot in ms when global pstates were |
76 | * last set | |
09ca4c9b AA |
77 | * @last_lpstate_idx, Last set value of local pstate and global |
78 | * last_gpstate_idx pstate in terms of cpufreq table index | |
eaa2c3ae AA |
79 | * @timer: Is used for ramping down if cpu goes idle for |
80 | * a long time with global pstate held high | |
81 | * @gpstate_lock: A spinlock to maintain synchronization between | |
82 | * routines called by the timer handler and | |
83 | * governer's target_index calls | |
84 | */ | |
85 | struct global_pstate_info { | |
09ca4c9b | 86 | int highest_lpstate_idx; |
eaa2c3ae AA |
87 | unsigned int elapsed_time; |
88 | unsigned int last_sampled_time; | |
09ca4c9b AA |
89 | int last_lpstate_idx; |
90 | int last_gpstate_idx; | |
eaa2c3ae AA |
91 | spinlock_t gpstate_lock; |
92 | struct timer_list timer; | |
1d1fe902 | 93 | struct cpufreq_policy *policy; |
eaa2c3ae AA |
94 | }; |
95 | ||
b3d627a5 | 96 | static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1]; |
332f0a01 GS |
97 | |
98 | DEFINE_HASHTABLE(pstate_revmap, POWERNV_MAX_PSTATES_ORDER); | |
99 | /** | |
100 | * struct pstate_idx_revmap_data: Entry in the hashmap pstate_revmap | |
101 | * indexed by a function of pstate id. | |
102 | * | |
103 | * @pstate_id: pstate id for this entry. | |
104 | * | |
105 | * @cpufreq_table_idx: Index into the powernv_freqs | |
106 | * cpufreq_frequency_table for frequency | |
107 | * corresponding to pstate_id. | |
108 | * | |
109 | * @hentry: hlist_node that hooks this entry into the pstate_revmap | |
110 | * hashtable | |
111 | */ | |
112 | struct pstate_idx_revmap_data { | |
967b87fd | 113 | u8 pstate_id; |
332f0a01 GS |
114 | unsigned int cpufreq_table_idx; |
115 | struct hlist_node hentry; | |
116 | }; | |
117 | ||
cb166fa9 | 118 | static bool rebooting, throttled, occ_reset; |
b3d627a5 | 119 | |
c89f2682 SB |
120 | static const char * const throttle_reason[] = { |
121 | "No throttling", | |
122 | "Power Cap", | |
123 | "Processor Over Temperature", | |
124 | "Power Supply Failure", | |
125 | "Over Current", | |
126 | "OCC Reset" | |
127 | }; | |
128 | ||
1b028984 SB |
129 | enum throttle_reason_type { |
130 | NO_THROTTLE = 0, | |
131 | POWERCAP, | |
132 | CPU_OVERTEMP, | |
133 | POWER_SUPPLY_FAILURE, | |
134 | OVERCURRENT, | |
135 | OCC_RESET_THROTTLE, | |
136 | OCC_MAX_REASON | |
137 | }; | |
138 | ||
053819e0 SB |
139 | static struct chip { |
140 | unsigned int id; | |
141 | bool throttled; | |
c89f2682 SB |
142 | bool restore; |
143 | u8 throttle_reason; | |
735366fc SB |
144 | cpumask_t mask; |
145 | struct work_struct throttle; | |
1b028984 SB |
146 | int throttle_turbo; |
147 | int throttle_sub_turbo; | |
148 | int reason[OCC_MAX_REASON]; | |
053819e0 SB |
149 | } *chips; |
150 | ||
151 | static int nr_chips; | |
3e5963bc | 152 | static DEFINE_PER_CPU(struct chip *, chip_info); |
053819e0 | 153 | |
b3d627a5 | 154 | /* |
09ca4c9b AA |
155 | * Note: |
156 | * The set of pstates consists of contiguous integers. | |
157 | * powernv_pstate_info stores the index of the frequency table for | |
158 | * max, min and nominal frequencies. It also stores number of | |
159 | * available frequencies. | |
b3d627a5 | 160 | * |
09ca4c9b AA |
161 | * powernv_pstate_info.nominal indicates the index to the highest |
162 | * non-turbo frequency. | |
b3d627a5 VS |
163 | */ |
164 | static struct powernv_pstate_info { | |
09ca4c9b AA |
165 | unsigned int min; |
166 | unsigned int max; | |
167 | unsigned int nominal; | |
168 | unsigned int nr_pstates; | |
b12f7a2b | 169 | bool wof_enabled; |
b3d627a5 VS |
170 | } powernv_pstate_info; |
171 | ||
967b87fd | 172 | static inline u8 extract_pstate(u64 pmsr_val, unsigned int shift) |
ee1f4a7d | 173 | { |
967b87fd | 174 | return ((pmsr_val >> shift) & 0xFF); |
ee1f4a7d GS |
175 | } |
176 | ||
177 | #define extract_local_pstate(x) extract_pstate(x, LPSTATE_SHIFT) | |
178 | #define extract_global_pstate(x) extract_pstate(x, GPSTATE_SHIFT) | |
179 | #define extract_max_pstate(x) extract_pstate(x, MAX_PSTATE_SHIFT) | |
180 | ||
332f0a01 GS |
181 | /* Use following functions for conversions between pstate_id and index */ |
182 | ||
183 | /** | |
184 | * idx_to_pstate : Returns the pstate id corresponding to the | |
185 | * frequency in the cpufreq frequency table | |
186 | * powernv_freqs indexed by @i. | |
187 | * | |
188 | * If @i is out of bound, this will return the pstate | |
189 | * corresponding to the nominal frequency. | |
190 | */ | |
967b87fd | 191 | static inline u8 idx_to_pstate(unsigned int i) |
09ca4c9b | 192 | { |
8e859467 | 193 | if (unlikely(i >= powernv_pstate_info.nr_pstates)) { |
332f0a01 | 194 | pr_warn_once("idx_to_pstate: index %u is out of bound\n", i); |
8e859467 AA |
195 | return powernv_freqs[powernv_pstate_info.nominal].driver_data; |
196 | } | |
197 | ||
09ca4c9b AA |
198 | return powernv_freqs[i].driver_data; |
199 | } | |
200 | ||
332f0a01 GS |
201 | /** |
202 | * pstate_to_idx : Returns the index in the cpufreq frequencytable | |
203 | * powernv_freqs for the frequency whose corresponding | |
204 | * pstate id is @pstate. | |
205 | * | |
206 | * If no frequency corresponding to @pstate is found, | |
207 | * this will return the index of the nominal | |
208 | * frequency. | |
209 | */ | |
967b87fd | 210 | static unsigned int pstate_to_idx(u8 pstate) |
09ca4c9b | 211 | { |
332f0a01 GS |
212 | unsigned int key = pstate % POWERNV_MAX_PSTATES; |
213 | struct pstate_idx_revmap_data *revmap_data; | |
8e859467 | 214 | |
332f0a01 GS |
215 | hash_for_each_possible(pstate_revmap, revmap_data, hentry, key) { |
216 | if (revmap_data->pstate_id == pstate) | |
217 | return revmap_data->cpufreq_table_idx; | |
8e859467 | 218 | } |
332f0a01 | 219 | |
967b87fd | 220 | pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate); |
332f0a01 | 221 | return powernv_pstate_info.nominal; |
09ca4c9b AA |
222 | } |
223 | ||
eaa2c3ae AA |
224 | static inline void reset_gpstates(struct cpufreq_policy *policy) |
225 | { | |
226 | struct global_pstate_info *gpstates = policy->driver_data; | |
227 | ||
09ca4c9b | 228 | gpstates->highest_lpstate_idx = 0; |
eaa2c3ae AA |
229 | gpstates->elapsed_time = 0; |
230 | gpstates->last_sampled_time = 0; | |
09ca4c9b AA |
231 | gpstates->last_lpstate_idx = 0; |
232 | gpstates->last_gpstate_idx = 0; | |
eaa2c3ae AA |
233 | } |
234 | ||
b3d627a5 VS |
235 | /* |
236 | * Initialize the freq table based on data obtained | |
237 | * from the firmware passed via device-tree | |
238 | */ | |
239 | static int init_powernv_pstates(void) | |
240 | { | |
241 | struct device_node *power_mgt; | |
09ca4c9b | 242 | int i, nr_pstates = 0; |
b3d627a5 VS |
243 | const __be32 *pstate_ids, *pstate_freqs; |
244 | u32 len_ids, len_freqs; | |
09ca4c9b | 245 | u32 pstate_min, pstate_max, pstate_nominal; |
b12f7a2b | 246 | u32 pstate_turbo, pstate_ultra_turbo; |
b3d627a5 VS |
247 | |
248 | power_mgt = of_find_node_by_path("/ibm,opal/power-mgt"); | |
249 | if (!power_mgt) { | |
250 | pr_warn("power-mgt node not found\n"); | |
251 | return -ENODEV; | |
252 | } | |
253 | ||
254 | if (of_property_read_u32(power_mgt, "ibm,pstate-min", &pstate_min)) { | |
255 | pr_warn("ibm,pstate-min node not found\n"); | |
256 | return -ENODEV; | |
257 | } | |
258 | ||
259 | if (of_property_read_u32(power_mgt, "ibm,pstate-max", &pstate_max)) { | |
260 | pr_warn("ibm,pstate-max node not found\n"); | |
261 | return -ENODEV; | |
262 | } | |
263 | ||
264 | if (of_property_read_u32(power_mgt, "ibm,pstate-nominal", | |
265 | &pstate_nominal)) { | |
266 | pr_warn("ibm,pstate-nominal not found\n"); | |
267 | return -ENODEV; | |
268 | } | |
b12f7a2b SB |
269 | |
270 | if (of_property_read_u32(power_mgt, "ibm,pstate-ultra-turbo", | |
271 | &pstate_ultra_turbo)) { | |
272 | powernv_pstate_info.wof_enabled = false; | |
273 | goto next; | |
274 | } | |
275 | ||
276 | if (of_property_read_u32(power_mgt, "ibm,pstate-turbo", | |
277 | &pstate_turbo)) { | |
278 | powernv_pstate_info.wof_enabled = false; | |
279 | goto next; | |
280 | } | |
281 | ||
282 | if (pstate_turbo == pstate_ultra_turbo) | |
283 | powernv_pstate_info.wof_enabled = false; | |
284 | else | |
285 | powernv_pstate_info.wof_enabled = true; | |
286 | ||
287 | next: | |
967b87fd | 288 | pr_info("cpufreq pstate min 0x%x nominal 0x%x max 0x%x\n", pstate_min, |
b3d627a5 | 289 | pstate_nominal, pstate_max); |
b12f7a2b SB |
290 | pr_info("Workload Optimized Frequency is %s in the platform\n", |
291 | (powernv_pstate_info.wof_enabled) ? "enabled" : "disabled"); | |
b3d627a5 VS |
292 | |
293 | pstate_ids = of_get_property(power_mgt, "ibm,pstate-ids", &len_ids); | |
294 | if (!pstate_ids) { | |
295 | pr_warn("ibm,pstate-ids not found\n"); | |
296 | return -ENODEV; | |
297 | } | |
298 | ||
299 | pstate_freqs = of_get_property(power_mgt, "ibm,pstate-frequencies-mhz", | |
300 | &len_freqs); | |
301 | if (!pstate_freqs) { | |
302 | pr_warn("ibm,pstate-frequencies-mhz not found\n"); | |
303 | return -ENODEV; | |
304 | } | |
305 | ||
6174bac8 VS |
306 | if (len_ids != len_freqs) { |
307 | pr_warn("Entries in ibm,pstate-ids and " | |
308 | "ibm,pstate-frequencies-mhz does not match\n"); | |
309 | } | |
310 | ||
b3d627a5 VS |
311 | nr_pstates = min(len_ids, len_freqs) / sizeof(u32); |
312 | if (!nr_pstates) { | |
313 | pr_warn("No PStates found\n"); | |
314 | return -ENODEV; | |
315 | } | |
316 | ||
09ca4c9b | 317 | powernv_pstate_info.nr_pstates = nr_pstates; |
b3d627a5 | 318 | pr_debug("NR PStates %d\n", nr_pstates); |
ee1f4a7d | 319 | |
b3d627a5 VS |
320 | for (i = 0; i < nr_pstates; i++) { |
321 | u32 id = be32_to_cpu(pstate_ids[i]); | |
322 | u32 freq = be32_to_cpu(pstate_freqs[i]); | |
332f0a01 GS |
323 | struct pstate_idx_revmap_data *revmap_data; |
324 | unsigned int key; | |
b3d627a5 VS |
325 | |
326 | pr_debug("PState id %d freq %d MHz\n", id, freq); | |
327 | powernv_freqs[i].frequency = freq * 1000; /* kHz */ | |
967b87fd | 328 | powernv_freqs[i].driver_data = id & 0xFF; |
09ca4c9b | 329 | |
332f0a01 GS |
330 | revmap_data = (struct pstate_idx_revmap_data *) |
331 | kmalloc(sizeof(*revmap_data), GFP_KERNEL); | |
332 | ||
967b87fd | 333 | revmap_data->pstate_id = id & 0xFF; |
332f0a01 | 334 | revmap_data->cpufreq_table_idx = i; |
967b87fd | 335 | key = (revmap_data->pstate_id) % POWERNV_MAX_PSTATES; |
332f0a01 GS |
336 | hash_add(pstate_revmap, &revmap_data->hentry, key); |
337 | ||
09ca4c9b AA |
338 | if (id == pstate_max) |
339 | powernv_pstate_info.max = i; | |
3fa4680b | 340 | if (id == pstate_nominal) |
09ca4c9b | 341 | powernv_pstate_info.nominal = i; |
3fa4680b | 342 | if (id == pstate_min) |
09ca4c9b | 343 | powernv_pstate_info.min = i; |
b12f7a2b SB |
344 | |
345 | if (powernv_pstate_info.wof_enabled && id == pstate_turbo) { | |
346 | int j; | |
347 | ||
348 | for (j = i - 1; j >= (int)powernv_pstate_info.max; j--) | |
349 | powernv_freqs[j].flags = CPUFREQ_BOOST_FREQ; | |
350 | } | |
b3d627a5 | 351 | } |
09ca4c9b | 352 | |
b3d627a5 VS |
353 | /* End of list marker entry */ |
354 | powernv_freqs[i].frequency = CPUFREQ_TABLE_END; | |
b3d627a5 VS |
355 | return 0; |
356 | } | |
357 | ||
358 | /* Returns the CPU frequency corresponding to the pstate_id. */ | |
967b87fd | 359 | static unsigned int pstate_id_to_freq(u8 pstate_id) |
b3d627a5 VS |
360 | { |
361 | int i; | |
362 | ||
09ca4c9b | 363 | i = pstate_to_idx(pstate_id); |
6174bac8 | 364 | if (i >= powernv_pstate_info.nr_pstates || i < 0) { |
967b87fd | 365 | pr_warn("PState id 0x%x outside of PState table, reporting nominal id 0x%x instead\n", |
09ca4c9b AA |
366 | pstate_id, idx_to_pstate(powernv_pstate_info.nominal)); |
367 | i = powernv_pstate_info.nominal; | |
6174bac8 | 368 | } |
b3d627a5 VS |
369 | |
370 | return powernv_freqs[i].frequency; | |
371 | } | |
372 | ||
373 | /* | |
374 | * cpuinfo_nominal_freq_show - Show the nominal CPU frequency as indicated by | |
375 | * the firmware | |
376 | */ | |
377 | static ssize_t cpuinfo_nominal_freq_show(struct cpufreq_policy *policy, | |
378 | char *buf) | |
379 | { | |
380 | return sprintf(buf, "%u\n", | |
09ca4c9b | 381 | powernv_freqs[powernv_pstate_info.nominal].frequency); |
b3d627a5 VS |
382 | } |
383 | ||
384 | struct freq_attr cpufreq_freq_attr_cpuinfo_nominal_freq = | |
385 | __ATTR_RO(cpuinfo_nominal_freq); | |
386 | ||
b12f7a2b SB |
387 | #define SCALING_BOOST_FREQS_ATTR_INDEX 2 |
388 | ||
b3d627a5 VS |
389 | static struct freq_attr *powernv_cpu_freq_attr[] = { |
390 | &cpufreq_freq_attr_scaling_available_freqs, | |
391 | &cpufreq_freq_attr_cpuinfo_nominal_freq, | |
b12f7a2b | 392 | &cpufreq_freq_attr_scaling_boost_freqs, |
b3d627a5 VS |
393 | NULL, |
394 | }; | |
395 | ||
1b028984 SB |
396 | #define throttle_attr(name, member) \ |
397 | static ssize_t name##_show(struct cpufreq_policy *policy, char *buf) \ | |
398 | { \ | |
399 | struct chip *chip = per_cpu(chip_info, policy->cpu); \ | |
400 | \ | |
401 | return sprintf(buf, "%u\n", chip->member); \ | |
402 | } \ | |
403 | \ | |
404 | static struct freq_attr throttle_attr_##name = __ATTR_RO(name) \ | |
405 | ||
406 | throttle_attr(unthrottle, reason[NO_THROTTLE]); | |
407 | throttle_attr(powercap, reason[POWERCAP]); | |
408 | throttle_attr(overtemp, reason[CPU_OVERTEMP]); | |
409 | throttle_attr(supply_fault, reason[POWER_SUPPLY_FAILURE]); | |
410 | throttle_attr(overcurrent, reason[OVERCURRENT]); | |
411 | throttle_attr(occ_reset, reason[OCC_RESET_THROTTLE]); | |
412 | throttle_attr(turbo_stat, throttle_turbo); | |
413 | throttle_attr(sub_turbo_stat, throttle_sub_turbo); | |
414 | ||
415 | static struct attribute *throttle_attrs[] = { | |
416 | &throttle_attr_unthrottle.attr, | |
417 | &throttle_attr_powercap.attr, | |
418 | &throttle_attr_overtemp.attr, | |
419 | &throttle_attr_supply_fault.attr, | |
420 | &throttle_attr_overcurrent.attr, | |
421 | &throttle_attr_occ_reset.attr, | |
422 | &throttle_attr_turbo_stat.attr, | |
423 | &throttle_attr_sub_turbo_stat.attr, | |
424 | NULL, | |
425 | }; | |
426 | ||
427 | static const struct attribute_group throttle_attr_grp = { | |
428 | .name = "throttle_stats", | |
429 | .attrs = throttle_attrs, | |
430 | }; | |
431 | ||
b3d627a5 VS |
432 | /* Helper routines */ |
433 | ||
434 | /* Access helpers to power mgt SPR */ | |
435 | ||
436 | static inline unsigned long get_pmspr(unsigned long sprn) | |
437 | { | |
438 | switch (sprn) { | |
439 | case SPRN_PMCR: | |
440 | return mfspr(SPRN_PMCR); | |
441 | ||
442 | case SPRN_PMICR: | |
443 | return mfspr(SPRN_PMICR); | |
444 | ||
445 | case SPRN_PMSR: | |
446 | return mfspr(SPRN_PMSR); | |
447 | } | |
448 | BUG(); | |
449 | } | |
450 | ||
451 | static inline void set_pmspr(unsigned long sprn, unsigned long val) | |
452 | { | |
453 | switch (sprn) { | |
454 | case SPRN_PMCR: | |
455 | mtspr(SPRN_PMCR, val); | |
456 | return; | |
457 | ||
458 | case SPRN_PMICR: | |
459 | mtspr(SPRN_PMICR, val); | |
460 | return; | |
461 | } | |
462 | BUG(); | |
463 | } | |
464 | ||
465 | /* | |
466 | * Use objects of this type to query/update | |
467 | * pstates on a remote CPU via smp_call_function. | |
468 | */ | |
469 | struct powernv_smp_call_data { | |
470 | unsigned int freq; | |
967b87fd GS |
471 | u8 pstate_id; |
472 | u8 gpstate_id; | |
b3d627a5 VS |
473 | }; |
474 | ||
475 | /* | |
476 | * powernv_read_cpu_freq: Reads the current frequency on this CPU. | |
477 | * | |
478 | * Called via smp_call_function. | |
479 | * | |
480 | * Note: The caller of the smp_call_function should pass an argument of | |
481 | * the type 'struct powernv_smp_call_data *' along with this function. | |
482 | * | |
483 | * The current frequency on this CPU will be returned via | |
484 | * ((struct powernv_smp_call_data *)arg)->freq; | |
485 | */ | |
486 | static void powernv_read_cpu_freq(void *arg) | |
487 | { | |
488 | unsigned long pmspr_val; | |
b3d627a5 VS |
489 | struct powernv_smp_call_data *freq_data = arg; |
490 | ||
491 | pmspr_val = get_pmspr(SPRN_PMSR); | |
ee1f4a7d | 492 | freq_data->pstate_id = extract_local_pstate(pmspr_val); |
b3d627a5 VS |
493 | freq_data->freq = pstate_id_to_freq(freq_data->pstate_id); |
494 | ||
967b87fd GS |
495 | pr_debug("cpu %d pmsr %016lX pstate_id 0x%x frequency %d kHz\n", |
496 | raw_smp_processor_id(), pmspr_val, freq_data->pstate_id, | |
497 | freq_data->freq); | |
b3d627a5 VS |
498 | } |
499 | ||
500 | /* | |
501 | * powernv_cpufreq_get: Returns the CPU frequency as reported by the | |
502 | * firmware for CPU 'cpu'. This value is reported through the sysfs | |
503 | * file cpuinfo_cur_freq. | |
504 | */ | |
60d1ea4e | 505 | static unsigned int powernv_cpufreq_get(unsigned int cpu) |
b3d627a5 VS |
506 | { |
507 | struct powernv_smp_call_data freq_data; | |
508 | ||
509 | smp_call_function_any(cpu_sibling_mask(cpu), powernv_read_cpu_freq, | |
510 | &freq_data, 1); | |
511 | ||
512 | return freq_data.freq; | |
513 | } | |
514 | ||
515 | /* | |
516 | * set_pstate: Sets the pstate on this CPU. | |
517 | * | |
518 | * This is called via an smp_call_function. | |
519 | * | |
520 | * The caller must ensure that freq_data is of the type | |
521 | * (struct powernv_smp_call_data *) and the pstate_id which needs to be set | |
522 | * on this CPU should be present in freq_data->pstate_id. | |
523 | */ | |
eaa2c3ae | 524 | static void set_pstate(void *data) |
b3d627a5 VS |
525 | { |
526 | unsigned long val; | |
eaa2c3ae AA |
527 | struct powernv_smp_call_data *freq_data = data; |
528 | unsigned long pstate_ul = freq_data->pstate_id; | |
529 | unsigned long gpstate_ul = freq_data->gpstate_id; | |
b3d627a5 VS |
530 | |
531 | val = get_pmspr(SPRN_PMCR); | |
532 | val = val & 0x0000FFFFFFFFFFFFULL; | |
533 | ||
534 | pstate_ul = pstate_ul & 0xFF; | |
eaa2c3ae | 535 | gpstate_ul = gpstate_ul & 0xFF; |
b3d627a5 VS |
536 | |
537 | /* Set both global(bits 56..63) and local(bits 48..55) PStates */ | |
eaa2c3ae | 538 | val = val | (gpstate_ul << 56) | (pstate_ul << 48); |
b3d627a5 VS |
539 | |
540 | pr_debug("Setting cpu %d pmcr to %016lX\n", | |
541 | raw_smp_processor_id(), val); | |
542 | set_pmspr(SPRN_PMCR, val); | |
543 | } | |
544 | ||
cf30af76 SB |
545 | /* |
546 | * get_nominal_index: Returns the index corresponding to the nominal | |
547 | * pstate in the cpufreq table | |
548 | */ | |
549 | static inline unsigned int get_nominal_index(void) | |
550 | { | |
09ca4c9b | 551 | return powernv_pstate_info.nominal; |
cf30af76 SB |
552 | } |
553 | ||
735366fc | 554 | static void powernv_cpufreq_throttle_check(void *data) |
09a972d1 | 555 | { |
3e5963bc | 556 | struct chip *chip; |
735366fc | 557 | unsigned int cpu = smp_processor_id(); |
09a972d1 | 558 | unsigned long pmsr; |
967b87fd | 559 | u8 pmsr_pmax; |
09ca4c9b | 560 | unsigned int pmsr_pmax_idx; |
09a972d1 SB |
561 | |
562 | pmsr = get_pmspr(SPRN_PMSR); | |
3e5963bc | 563 | chip = this_cpu_read(chip_info); |
053819e0 | 564 | |
09a972d1 | 565 | /* Check for Pmax Capping */ |
ee1f4a7d | 566 | pmsr_pmax = extract_max_pstate(pmsr); |
09ca4c9b AA |
567 | pmsr_pmax_idx = pstate_to_idx(pmsr_pmax); |
568 | if (pmsr_pmax_idx != powernv_pstate_info.max) { | |
3e5963bc | 569 | if (chip->throttled) |
053819e0 | 570 | goto next; |
3e5963bc | 571 | chip->throttled = true; |
09ca4c9b | 572 | if (pmsr_pmax_idx > powernv_pstate_info.nominal) { |
967b87fd | 573 | pr_warn_once("CPU %d on Chip %u has Pmax(0x%x) reduced below that of nominal frequency(0x%x)\n", |
3e5963bc | 574 | cpu, chip->id, pmsr_pmax, |
09ca4c9b | 575 | idx_to_pstate(powernv_pstate_info.nominal)); |
1b028984 SB |
576 | chip->throttle_sub_turbo++; |
577 | } else { | |
578 | chip->throttle_turbo++; | |
579 | } | |
3e5963bc MN |
580 | trace_powernv_throttle(chip->id, |
581 | throttle_reason[chip->throttle_reason], | |
c89f2682 | 582 | pmsr_pmax); |
3e5963bc MN |
583 | } else if (chip->throttled) { |
584 | chip->throttled = false; | |
585 | trace_powernv_throttle(chip->id, | |
586 | throttle_reason[chip->throttle_reason], | |
c89f2682 | 587 | pmsr_pmax); |
09a972d1 SB |
588 | } |
589 | ||
3dd3ebe5 | 590 | /* Check if Psafe_mode_active is set in PMSR. */ |
053819e0 | 591 | next: |
3dd3ebe5 | 592 | if (pmsr & PMSR_PSAFE_ENABLE) { |
09a972d1 SB |
593 | throttled = true; |
594 | pr_info("Pstate set to safe frequency\n"); | |
595 | } | |
596 | ||
597 | /* Check if SPR_EM_DISABLE is set in PMSR */ | |
598 | if (pmsr & PMSR_SPR_EM_DISABLE) { | |
599 | throttled = true; | |
600 | pr_info("Frequency Control disabled from OS\n"); | |
601 | } | |
602 | ||
603 | if (throttled) { | |
604 | pr_info("PMSR = %16lx\n", pmsr); | |
c89f2682 | 605 | pr_warn("CPU Frequency could be throttled\n"); |
09a972d1 SB |
606 | } |
607 | } | |
608 | ||
eaa2c3ae AA |
609 | /** |
610 | * calc_global_pstate - Calculate global pstate | |
09ca4c9b AA |
611 | * @elapsed_time: Elapsed time in milliseconds |
612 | * @local_pstate_idx: New local pstate | |
613 | * @highest_lpstate_idx: pstate from which its ramping down | |
eaa2c3ae AA |
614 | * |
615 | * Finds the appropriate global pstate based on the pstate from which its | |
616 | * ramping down and the time elapsed in ramping down. It follows a quadratic | |
617 | * equation which ensures that it reaches ramping down to pmin in 5sec. | |
618 | */ | |
619 | static inline int calc_global_pstate(unsigned int elapsed_time, | |
09ca4c9b AA |
620 | int highest_lpstate_idx, |
621 | int local_pstate_idx) | |
eaa2c3ae | 622 | { |
09ca4c9b | 623 | int index_diff; |
eaa2c3ae AA |
624 | |
625 | /* | |
626 | * Using ramp_down_percent we get the percentage of rampdown | |
627 | * that we are expecting to be dropping. Difference between | |
09ca4c9b | 628 | * highest_lpstate_idx and powernv_pstate_info.min will give a absolute |
eaa2c3ae AA |
629 | * number of how many pstates we will drop eventually by the end of |
630 | * 5 seconds, then just scale it get the number pstates to be dropped. | |
631 | */ | |
09ca4c9b AA |
632 | index_diff = ((int)ramp_down_percent(elapsed_time) * |
633 | (powernv_pstate_info.min - highest_lpstate_idx)) / 100; | |
eaa2c3ae AA |
634 | |
635 | /* Ensure that global pstate is >= to local pstate */ | |
09ca4c9b AA |
636 | if (highest_lpstate_idx + index_diff >= local_pstate_idx) |
637 | return local_pstate_idx; | |
eaa2c3ae | 638 | else |
09ca4c9b | 639 | return highest_lpstate_idx + index_diff; |
eaa2c3ae AA |
640 | } |
641 | ||
642 | static inline void queue_gpstate_timer(struct global_pstate_info *gpstates) | |
643 | { | |
644 | unsigned int timer_interval; | |
645 | ||
646 | /* | |
647 | * Setting up timer to fire after GPSTATE_TIMER_INTERVAL ms, But | |
648 | * if it exceeds MAX_RAMP_DOWN_TIME ms for ramp down time. | |
649 | * Set timer such that it fires exactly at MAX_RAMP_DOWN_TIME | |
650 | * seconds of ramp down time. | |
651 | */ | |
652 | if ((gpstates->elapsed_time + GPSTATE_TIMER_INTERVAL) | |
653 | > MAX_RAMP_DOWN_TIME) | |
654 | timer_interval = MAX_RAMP_DOWN_TIME - gpstates->elapsed_time; | |
655 | else | |
656 | timer_interval = GPSTATE_TIMER_INTERVAL; | |
657 | ||
7bc54b65 | 658 | mod_timer(&gpstates->timer, jiffies + msecs_to_jiffies(timer_interval)); |
eaa2c3ae AA |
659 | } |
660 | ||
661 | /** | |
662 | * gpstate_timer_handler | |
663 | * | |
664 | * @data: pointer to cpufreq_policy on which timer was queued | |
665 | * | |
666 | * This handler brings down the global pstate closer to the local pstate | |
667 | * according quadratic equation. Queues a new timer if it is still not equal | |
668 | * to local pstate | |
669 | */ | |
1d1fe902 | 670 | void gpstate_timer_handler(struct timer_list *t) |
eaa2c3ae | 671 | { |
1d1fe902 KC |
672 | struct global_pstate_info *gpstates = from_timer(gpstates, t, timer); |
673 | struct cpufreq_policy *policy = gpstates->policy; | |
20b15b76 AA |
674 | int gpstate_idx, lpstate_idx; |
675 | unsigned long val; | |
eaa2c3ae AA |
676 | unsigned int time_diff = jiffies_to_msecs(jiffies) |
677 | - gpstates->last_sampled_time; | |
678 | struct powernv_smp_call_data freq_data; | |
679 | ||
680 | if (!spin_trylock(&gpstates->gpstate_lock)) | |
681 | return; | |
c0f7f5b6 SB |
682 | /* |
683 | * If the timer has migrated to the different cpu then bring | |
684 | * it back to one of the policy->cpus | |
685 | */ | |
686 | if (!cpumask_test_cpu(raw_smp_processor_id(), policy->cpus)) { | |
687 | gpstates->timer.expires = jiffies + msecs_to_jiffies(1); | |
688 | add_timer_on(&gpstates->timer, cpumask_first(policy->cpus)); | |
689 | spin_unlock(&gpstates->gpstate_lock); | |
690 | return; | |
691 | } | |
eaa2c3ae | 692 | |
20b15b76 AA |
693 | /* |
694 | * If PMCR was last updated was using fast_swtich then | |
695 | * We may have wrong in gpstate->last_lpstate_idx | |
696 | * value. Hence, read from PMCR to get correct data. | |
697 | */ | |
698 | val = get_pmspr(SPRN_PMCR); | |
ee1f4a7d GS |
699 | freq_data.gpstate_id = extract_global_pstate(val); |
700 | freq_data.pstate_id = extract_local_pstate(val); | |
20b15b76 AA |
701 | if (freq_data.gpstate_id == freq_data.pstate_id) { |
702 | reset_gpstates(policy); | |
703 | spin_unlock(&gpstates->gpstate_lock); | |
704 | return; | |
705 | } | |
706 | ||
eaa2c3ae AA |
707 | gpstates->last_sampled_time += time_diff; |
708 | gpstates->elapsed_time += time_diff; | |
eaa2c3ae | 709 | |
20b15b76 | 710 | if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) { |
09ca4c9b | 711 | gpstate_idx = pstate_to_idx(freq_data.pstate_id); |
c9a81e68 | 712 | lpstate_idx = gpstate_idx; |
eaa2c3ae | 713 | reset_gpstates(policy); |
09ca4c9b | 714 | gpstates->highest_lpstate_idx = gpstate_idx; |
eaa2c3ae | 715 | } else { |
20b15b76 | 716 | lpstate_idx = pstate_to_idx(freq_data.pstate_id); |
09ca4c9b AA |
717 | gpstate_idx = calc_global_pstate(gpstates->elapsed_time, |
718 | gpstates->highest_lpstate_idx, | |
20b15b76 | 719 | lpstate_idx); |
eaa2c3ae | 720 | } |
20b15b76 AA |
721 | freq_data.gpstate_id = idx_to_pstate(gpstate_idx); |
722 | gpstates->last_gpstate_idx = gpstate_idx; | |
723 | gpstates->last_lpstate_idx = lpstate_idx; | |
eaa2c3ae AA |
724 | /* |
725 | * If local pstate is equal to global pstate, rampdown is over | |
726 | * So timer is not required to be queued. | |
727 | */ | |
09ca4c9b | 728 | if (gpstate_idx != gpstates->last_lpstate_idx) |
eaa2c3ae AA |
729 | queue_gpstate_timer(gpstates); |
730 | ||
c0f7f5b6 | 731 | set_pstate(&freq_data); |
1fd3ff28 | 732 | spin_unlock(&gpstates->gpstate_lock); |
eaa2c3ae AA |
733 | } |
734 | ||
b3d627a5 VS |
735 | /* |
736 | * powernv_cpufreq_target_index: Sets the frequency corresponding to | |
737 | * the cpufreq table entry indexed by new_index on the cpus in the | |
738 | * mask policy->cpus | |
739 | */ | |
740 | static int powernv_cpufreq_target_index(struct cpufreq_policy *policy, | |
741 | unsigned int new_index) | |
742 | { | |
743 | struct powernv_smp_call_data freq_data; | |
09ca4c9b | 744 | unsigned int cur_msec, gpstate_idx; |
eaa2c3ae | 745 | struct global_pstate_info *gpstates = policy->driver_data; |
b3d627a5 | 746 | |
cf30af76 SB |
747 | if (unlikely(rebooting) && new_index != get_nominal_index()) |
748 | return 0; | |
749 | ||
8a10c06a DK |
750 | if (!throttled) { |
751 | /* we don't want to be preempted while | |
752 | * checking if the CPU frequency has been throttled | |
753 | */ | |
754 | preempt_disable(); | |
735366fc | 755 | powernv_cpufreq_throttle_check(NULL); |
8a10c06a DK |
756 | preempt_enable(); |
757 | } | |
09a972d1 | 758 | |
eaa2c3ae AA |
759 | cur_msec = jiffies_to_msecs(get_jiffies_64()); |
760 | ||
1fd3ff28 | 761 | spin_lock(&gpstates->gpstate_lock); |
09ca4c9b | 762 | freq_data.pstate_id = idx_to_pstate(new_index); |
b3d627a5 | 763 | |
eaa2c3ae | 764 | if (!gpstates->last_sampled_time) { |
09ca4c9b AA |
765 | gpstate_idx = new_index; |
766 | gpstates->highest_lpstate_idx = new_index; | |
eaa2c3ae AA |
767 | goto gpstates_done; |
768 | } | |
769 | ||
09ca4c9b | 770 | if (gpstates->last_gpstate_idx < new_index) { |
eaa2c3ae AA |
771 | gpstates->elapsed_time += cur_msec - |
772 | gpstates->last_sampled_time; | |
773 | ||
774 | /* | |
775 | * If its has been ramping down for more than MAX_RAMP_DOWN_TIME | |
776 | * we should be resetting all global pstate related data. Set it | |
777 | * equal to local pstate to start fresh. | |
778 | */ | |
779 | if (gpstates->elapsed_time > MAX_RAMP_DOWN_TIME) { | |
780 | reset_gpstates(policy); | |
09ca4c9b AA |
781 | gpstates->highest_lpstate_idx = new_index; |
782 | gpstate_idx = new_index; | |
eaa2c3ae AA |
783 | } else { |
784 | /* Elaspsed_time is less than 5 seconds, continue to rampdown */ | |
09ca4c9b AA |
785 | gpstate_idx = calc_global_pstate(gpstates->elapsed_time, |
786 | gpstates->highest_lpstate_idx, | |
787 | new_index); | |
eaa2c3ae AA |
788 | } |
789 | } else { | |
790 | reset_gpstates(policy); | |
09ca4c9b AA |
791 | gpstates->highest_lpstate_idx = new_index; |
792 | gpstate_idx = new_index; | |
eaa2c3ae AA |
793 | } |
794 | ||
795 | /* | |
796 | * If local pstate is equal to global pstate, rampdown is over | |
797 | * So timer is not required to be queued. | |
798 | */ | |
09ca4c9b | 799 | if (gpstate_idx != new_index) |
eaa2c3ae | 800 | queue_gpstate_timer(gpstates); |
0bc10b93 AA |
801 | else |
802 | del_timer_sync(&gpstates->timer); | |
eaa2c3ae AA |
803 | |
804 | gpstates_done: | |
09ca4c9b | 805 | freq_data.gpstate_id = idx_to_pstate(gpstate_idx); |
eaa2c3ae | 806 | gpstates->last_sampled_time = cur_msec; |
09ca4c9b AA |
807 | gpstates->last_gpstate_idx = gpstate_idx; |
808 | gpstates->last_lpstate_idx = new_index; | |
eaa2c3ae | 809 | |
1fd3ff28 AA |
810 | spin_unlock(&gpstates->gpstate_lock); |
811 | ||
b3d627a5 VS |
812 | /* |
813 | * Use smp_call_function to send IPI and execute the | |
814 | * mtspr on target CPU. We could do that without IPI | |
815 | * if current CPU is within policy->cpus (core) | |
816 | */ | |
817 | smp_call_function_any(policy->cpus, set_pstate, &freq_data, 1); | |
b3d627a5 VS |
818 | return 0; |
819 | } | |
820 | ||
821 | static int powernv_cpufreq_cpu_init(struct cpufreq_policy *policy) | |
822 | { | |
bf14721c | 823 | int base, i; |
2920e9ce | 824 | struct kernfs_node *kn; |
eaa2c3ae | 825 | struct global_pstate_info *gpstates; |
b3d627a5 VS |
826 | |
827 | base = cpu_first_thread_sibling(policy->cpu); | |
828 | ||
829 | for (i = 0; i < threads_per_core; i++) | |
830 | cpumask_set_cpu(base + i, policy->cpus); | |
831 | ||
2920e9ce SB |
832 | kn = kernfs_find_and_get(policy->kobj.sd, throttle_attr_grp.name); |
833 | if (!kn) { | |
1b028984 SB |
834 | int ret; |
835 | ||
836 | ret = sysfs_create_group(&policy->kobj, &throttle_attr_grp); | |
837 | if (ret) { | |
838 | pr_info("Failed to create throttle stats directory for cpu %d\n", | |
839 | policy->cpu); | |
840 | return ret; | |
841 | } | |
2920e9ce SB |
842 | } else { |
843 | kernfs_put(kn); | |
1b028984 | 844 | } |
eaa2c3ae AA |
845 | |
846 | gpstates = kzalloc(sizeof(*gpstates), GFP_KERNEL); | |
847 | if (!gpstates) | |
848 | return -ENOMEM; | |
849 | ||
850 | policy->driver_data = gpstates; | |
851 | ||
852 | /* initialize timer */ | |
1d1fe902 KC |
853 | gpstates->policy = policy; |
854 | timer_setup(&gpstates->timer, gpstate_timer_handler, | |
855 | TIMER_PINNED | TIMER_DEFERRABLE); | |
eaa2c3ae AA |
856 | gpstates->timer.expires = jiffies + |
857 | msecs_to_jiffies(GPSTATE_TIMER_INTERVAL); | |
858 | spin_lock_init(&gpstates->gpstate_lock); | |
eaa2c3ae | 859 | |
bf14721c | 860 | policy->freq_table = powernv_freqs; |
60c9efb8 | 861 | policy->fast_switch_possible = true; |
bf14721c | 862 | return 0; |
eaa2c3ae AA |
863 | } |
864 | ||
865 | static int powernv_cpufreq_cpu_exit(struct cpufreq_policy *policy) | |
866 | { | |
867 | /* timer is deleted in cpufreq_cpu_stop() */ | |
868 | kfree(policy->driver_data); | |
869 | ||
870 | return 0; | |
b3d627a5 VS |
871 | } |
872 | ||
cf30af76 SB |
873 | static int powernv_cpufreq_reboot_notifier(struct notifier_block *nb, |
874 | unsigned long action, void *unused) | |
875 | { | |
876 | int cpu; | |
877 | struct cpufreq_policy cpu_policy; | |
878 | ||
879 | rebooting = true; | |
880 | for_each_online_cpu(cpu) { | |
881 | cpufreq_get_policy(&cpu_policy, cpu); | |
882 | powernv_cpufreq_target_index(&cpu_policy, get_nominal_index()); | |
883 | } | |
884 | ||
885 | return NOTIFY_DONE; | |
886 | } | |
887 | ||
888 | static struct notifier_block powernv_cpufreq_reboot_nb = { | |
889 | .notifier_call = powernv_cpufreq_reboot_notifier, | |
890 | }; | |
891 | ||
735366fc SB |
892 | void powernv_cpufreq_work_fn(struct work_struct *work) |
893 | { | |
894 | struct chip *chip = container_of(work, struct chip, throttle); | |
22794280 | 895 | unsigned int cpu; |
6d167a44 | 896 | cpumask_t mask; |
735366fc | 897 | |
6d167a44 SB |
898 | get_online_cpus(); |
899 | cpumask_and(&mask, &chip->mask, cpu_online_mask); | |
900 | smp_call_function_any(&mask, | |
735366fc | 901 | powernv_cpufreq_throttle_check, NULL, 0); |
22794280 SB |
902 | |
903 | if (!chip->restore) | |
6d167a44 | 904 | goto out; |
22794280 SB |
905 | |
906 | chip->restore = false; | |
6d167a44 SB |
907 | for_each_cpu(cpu, &mask) { |
908 | int index; | |
22794280 SB |
909 | struct cpufreq_policy policy; |
910 | ||
911 | cpufreq_get_policy(&policy, cpu); | |
82577360 | 912 | index = cpufreq_table_find_index_c(&policy, policy.cur); |
22794280 | 913 | powernv_cpufreq_target_index(&policy, index); |
6d167a44 | 914 | cpumask_andnot(&mask, &mask, policy.cpus); |
22794280 | 915 | } |
6d167a44 SB |
916 | out: |
917 | put_online_cpus(); | |
735366fc SB |
918 | } |
919 | ||
cb166fa9 SB |
920 | static int powernv_cpufreq_occ_msg(struct notifier_block *nb, |
921 | unsigned long msg_type, void *_msg) | |
922 | { | |
923 | struct opal_msg *msg = _msg; | |
924 | struct opal_occ_msg omsg; | |
735366fc | 925 | int i; |
cb166fa9 SB |
926 | |
927 | if (msg_type != OPAL_MSG_OCC) | |
928 | return 0; | |
929 | ||
930 | omsg.type = be64_to_cpu(msg->params[0]); | |
931 | ||
932 | switch (omsg.type) { | |
933 | case OCC_RESET: | |
934 | occ_reset = true; | |
309d0631 | 935 | pr_info("OCC (On Chip Controller - enforces hard thermal/power limits) Resetting\n"); |
cb166fa9 SB |
936 | /* |
937 | * powernv_cpufreq_throttle_check() is called in | |
938 | * target() callback which can detect the throttle state | |
939 | * for governors like ondemand. | |
940 | * But static governors will not call target() often thus | |
941 | * report throttling here. | |
942 | */ | |
943 | if (!throttled) { | |
944 | throttled = true; | |
c89f2682 | 945 | pr_warn("CPU frequency is throttled for duration\n"); |
cb166fa9 | 946 | } |
309d0631 | 947 | |
cb166fa9 SB |
948 | break; |
949 | case OCC_LOAD: | |
309d0631 | 950 | pr_info("OCC Loading, CPU frequency is throttled until OCC is started\n"); |
cb166fa9 SB |
951 | break; |
952 | case OCC_THROTTLE: | |
953 | omsg.chip = be64_to_cpu(msg->params[1]); | |
954 | omsg.throttle_status = be64_to_cpu(msg->params[2]); | |
955 | ||
956 | if (occ_reset) { | |
957 | occ_reset = false; | |
958 | throttled = false; | |
309d0631 | 959 | pr_info("OCC Active, CPU frequency is no longer throttled\n"); |
735366fc | 960 | |
22794280 SB |
961 | for (i = 0; i < nr_chips; i++) { |
962 | chips[i].restore = true; | |
735366fc | 963 | schedule_work(&chips[i].throttle); |
22794280 | 964 | } |
735366fc | 965 | |
cb166fa9 SB |
966 | return 0; |
967 | } | |
968 | ||
c89f2682 SB |
969 | for (i = 0; i < nr_chips; i++) |
970 | if (chips[i].id == omsg.chip) | |
971 | break; | |
972 | ||
973 | if (omsg.throttle_status >= 0 && | |
1b028984 | 974 | omsg.throttle_status <= OCC_MAX_THROTTLE_STATUS) { |
c89f2682 | 975 | chips[i].throttle_reason = omsg.throttle_status; |
1b028984 SB |
976 | chips[i].reason[omsg.throttle_status]++; |
977 | } | |
735366fc | 978 | |
c89f2682 SB |
979 | if (!omsg.throttle_status) |
980 | chips[i].restore = true; | |
981 | ||
982 | schedule_work(&chips[i].throttle); | |
cb166fa9 SB |
983 | } |
984 | return 0; | |
985 | } | |
986 | ||
987 | static struct notifier_block powernv_cpufreq_opal_nb = { | |
988 | .notifier_call = powernv_cpufreq_occ_msg, | |
989 | .next = NULL, | |
990 | .priority = 0, | |
991 | }; | |
992 | ||
b120339c PM |
993 | static void powernv_cpufreq_stop_cpu(struct cpufreq_policy *policy) |
994 | { | |
995 | struct powernv_smp_call_data freq_data; | |
eaa2c3ae | 996 | struct global_pstate_info *gpstates = policy->driver_data; |
b120339c | 997 | |
09ca4c9b AA |
998 | freq_data.pstate_id = idx_to_pstate(powernv_pstate_info.min); |
999 | freq_data.gpstate_id = idx_to_pstate(powernv_pstate_info.min); | |
b120339c | 1000 | smp_call_function_single(policy->cpu, set_pstate, &freq_data, 1); |
eaa2c3ae | 1001 | del_timer_sync(&gpstates->timer); |
b120339c PM |
1002 | } |
1003 | ||
60c9efb8 AA |
1004 | static unsigned int powernv_fast_switch(struct cpufreq_policy *policy, |
1005 | unsigned int target_freq) | |
1006 | { | |
1007 | int index; | |
1008 | struct powernv_smp_call_data freq_data; | |
1009 | ||
1010 | index = cpufreq_table_find_index_dl(policy, target_freq); | |
1011 | freq_data.pstate_id = powernv_freqs[index].driver_data; | |
1012 | freq_data.gpstate_id = powernv_freqs[index].driver_data; | |
1013 | set_pstate(&freq_data); | |
1014 | ||
1015 | return powernv_freqs[index].frequency; | |
1016 | } | |
1017 | ||
b3d627a5 VS |
1018 | static struct cpufreq_driver powernv_cpufreq_driver = { |
1019 | .name = "powernv-cpufreq", | |
1020 | .flags = CPUFREQ_CONST_LOOPS, | |
1021 | .init = powernv_cpufreq_cpu_init, | |
eaa2c3ae | 1022 | .exit = powernv_cpufreq_cpu_exit, |
b3d627a5 VS |
1023 | .verify = cpufreq_generic_frequency_table_verify, |
1024 | .target_index = powernv_cpufreq_target_index, | |
60c9efb8 | 1025 | .fast_switch = powernv_fast_switch, |
b3d627a5 | 1026 | .get = powernv_cpufreq_get, |
b120339c | 1027 | .stop_cpu = powernv_cpufreq_stop_cpu, |
b3d627a5 VS |
1028 | .attr = powernv_cpu_freq_attr, |
1029 | }; | |
1030 | ||
053819e0 SB |
1031 | static int init_chip_info(void) |
1032 | { | |
1033 | unsigned int chip[256]; | |
1034 | unsigned int cpu, i; | |
1035 | unsigned int prev_chip_id = UINT_MAX; | |
96c4726f | 1036 | |
3e5963bc | 1037 | for_each_possible_cpu(cpu) { |
053819e0 SB |
1038 | unsigned int id = cpu_to_chip_id(cpu); |
1039 | ||
1040 | if (prev_chip_id != id) { | |
1041 | prev_chip_id = id; | |
1042 | chip[nr_chips++] = id; | |
1043 | } | |
1044 | } | |
1045 | ||
c89f2682 | 1046 | chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL); |
053819e0 | 1047 | if (!chips) |
3e5963bc | 1048 | return -ENOMEM; |
053819e0 SB |
1049 | |
1050 | for (i = 0; i < nr_chips; i++) { | |
1051 | chips[i].id = chip[i]; | |
735366fc SB |
1052 | cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i])); |
1053 | INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn); | |
3e5963bc MN |
1054 | for_each_cpu(cpu, &chips[i].mask) |
1055 | per_cpu(chip_info, cpu) = &chips[i]; | |
053819e0 SB |
1056 | } |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
c5e29ea7 SB |
1061 | static inline void clean_chip_info(void) |
1062 | { | |
1063 | kfree(chips); | |
c5e29ea7 SB |
1064 | } |
1065 | ||
1066 | static inline void unregister_all_notifiers(void) | |
1067 | { | |
1068 | opal_message_notifier_unregister(OPAL_MSG_OCC, | |
1069 | &powernv_cpufreq_opal_nb); | |
1070 | unregister_reboot_notifier(&powernv_cpufreq_reboot_nb); | |
1071 | } | |
1072 | ||
b3d627a5 VS |
1073 | static int __init powernv_cpufreq_init(void) |
1074 | { | |
1075 | int rc = 0; | |
1076 | ||
6174bac8 | 1077 | /* Don't probe on pseries (guest) platforms */ |
e4d54f71 | 1078 | if (!firmware_has_feature(FW_FEATURE_OPAL)) |
6174bac8 VS |
1079 | return -ENODEV; |
1080 | ||
b3d627a5 VS |
1081 | /* Discover pstates from device tree and init */ |
1082 | rc = init_powernv_pstates(); | |
c5e29ea7 SB |
1083 | if (rc) |
1084 | goto out; | |
b3d627a5 | 1085 | |
053819e0 SB |
1086 | /* Populate chip info */ |
1087 | rc = init_chip_info(); | |
1088 | if (rc) | |
c5e29ea7 | 1089 | goto out; |
053819e0 | 1090 | |
cf30af76 | 1091 | register_reboot_notifier(&powernv_cpufreq_reboot_nb); |
cb166fa9 | 1092 | opal_message_notifier_register(OPAL_MSG_OCC, &powernv_cpufreq_opal_nb); |
c5e29ea7 | 1093 | |
b12f7a2b SB |
1094 | if (powernv_pstate_info.wof_enabled) |
1095 | powernv_cpufreq_driver.boost_enabled = true; | |
1096 | else | |
1097 | powernv_cpu_freq_attr[SCALING_BOOST_FREQS_ATTR_INDEX] = NULL; | |
1098 | ||
c5e29ea7 | 1099 | rc = cpufreq_register_driver(&powernv_cpufreq_driver); |
b12f7a2b SB |
1100 | if (rc) { |
1101 | pr_info("Failed to register the cpufreq driver (%d)\n", rc); | |
1102 | goto cleanup_notifiers; | |
1103 | } | |
c5e29ea7 | 1104 | |
b12f7a2b SB |
1105 | if (powernv_pstate_info.wof_enabled) |
1106 | cpufreq_enable_boost_support(); | |
1107 | ||
1108 | return 0; | |
1109 | cleanup_notifiers: | |
c5e29ea7 SB |
1110 | unregister_all_notifiers(); |
1111 | clean_chip_info(); | |
1112 | out: | |
1113 | pr_info("Platform driver disabled. System does not support PState control\n"); | |
1114 | return rc; | |
b3d627a5 VS |
1115 | } |
1116 | module_init(powernv_cpufreq_init); | |
1117 | ||
1118 | static void __exit powernv_cpufreq_exit(void) | |
1119 | { | |
1120 | cpufreq_unregister_driver(&powernv_cpufreq_driver); | |
c5e29ea7 SB |
1121 | unregister_all_notifiers(); |
1122 | clean_chip_info(); | |
b3d627a5 VS |
1123 | } |
1124 | module_exit(powernv_cpufreq_exit); | |
1125 | ||
1126 | MODULE_LICENSE("GPL"); | |
1127 | MODULE_AUTHOR("Vaidyanathan Srinivasan <svaidy at linux.vnet.ibm.com>"); |