[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / pxa3xx-cpufreq.c

/*
 * Copyright (C) 2008 Marvell International Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/slab.h>
#include <linux/io.h>

#include <mach/generic.h>
#include <mach/pxa3xx-regs.h>

#define HSS_104M	(0)
#define HSS_156M	(1)
#define HSS_208M	(2)
#define HSS_312M	(3)

#define SMCFS_78M	(0)
#define SMCFS_104M	(2)
#define SMCFS_208M	(5)

#define SFLFS_104M	(0)
#define SFLFS_156M	(1)
#define SFLFS_208M	(2)
#define SFLFS_312M	(3)

#define XSPCLK_156M	(0)
#define XSPCLK_NONE	(3)

#define DMCFS_26M	(0)
#define DMCFS_260M	(3)

struct pxa3xx_freq_info {
	unsigned int cpufreq_mhz;
	unsigned int core_xl : 5;
	unsigned int core_xn : 3;
	unsigned int hss : 2;
	unsigned int dmcfs : 2;
	unsigned int smcfs : 3;
	unsigned int sflfs : 2;
	unsigned int df_clkdiv : 3;

	int	vcc_core;	/* in mV */
	int	vcc_sram;	/* in mV */
};

#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
{									\
	.cpufreq_mhz	= cpufreq,					\
	.core_xl	= _xl,						\
	.core_xn	= _xn,						\
	.hss		= HSS_##_hss##M,				\
	.dmcfs		= DMCFS_##_dmc##M,				\
	.smcfs		= SMCFS_##_smc##M,				\
	.sflfs		= SFLFS_##_sfl##M,				\
	.df_clkdiv	= _dfi,						\
	.vcc_core	= vcore,					\
	.vcc_sram	= vsram,					\
}

static struct pxa3xx_freq_info pxa300_freqs[] = {
	/*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
	OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
	OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
	OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
	OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
};

static struct pxa3xx_freq_info pxa320_freqs[] = {
	/*  CPU XL XN  HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
	OP(104,  8, 1, 104, 260,  78, 104, 3, 1000, 1100), /* 104MHz */
	OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
	OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
	OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
	OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
};

static unsigned int pxa3xx_freqs_num;
static struct pxa3xx_freq_info *pxa3xx_freqs;
static struct cpufreq_frequency_table *pxa3xx_freqs_table;

static int setup_freqs_table(struct cpufreq_policy *policy,
			     struct pxa3xx_freq_info *freqs, int num)
{
	struct cpufreq_frequency_table *table;
	int i;

	table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
	if (table == NULL)
		return -ENOMEM;

	for (i = 0; i < num; i++) {
		table[i].driver_data = i;
		table[i].frequency = freqs[i].cpufreq_mhz * 1000;
	}
	table[num].driver_data = i;
	table[num].frequency = CPUFREQ_TABLE_END;

	pxa3xx_freqs = freqs;
	pxa3xx_freqs_num = num;
	pxa3xx_freqs_table = table;

	return cpufreq_table_validate_and_show(policy, table);
}

static void __update_core_freq(struct pxa3xx_freq_info *info)
{
	uint32_t mask = ACCR_XN_MASK | ACCR_XL_MASK;
	uint32_t accr = ACCR;
	uint32_t xclkcfg;

	accr &= ~(ACCR_XN_MASK | ACCR_XL_MASK | ACCR_XSPCLK_MASK);
	accr |= ACCR_XN(info->core_xn) | ACCR_XL(info->core_xl);

	/* No clock until core PLL is re-locked */
	accr |= ACCR_XSPCLK(XSPCLK_NONE);

	xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2;	/* turbo bit */

	ACCR = accr;
	__asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));

	while ((ACSR & mask) != (accr & mask))
		cpu_relax();
}

static void __update_bus_freq(struct pxa3xx_freq_info *info)
{
	uint32_t mask;
	uint32_t accr = ACCR;

	mask = ACCR_SMCFS_MASK | ACCR_SFLFS_MASK | ACCR_HSS_MASK |
		ACCR_DMCFS_MASK;

	accr &= ~mask;
	accr |= ACCR_SMCFS(info->smcfs) | ACCR_SFLFS(info->sflfs) |
		ACCR_HSS(info->hss) | ACCR_DMCFS(info->dmcfs);

	ACCR = accr;

	while ((ACSR & mask) != (accr & mask))
		cpu_relax();
}

static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
{
	return pxa3xx_get_clk_frequency_khz(0);
}

static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
			      unsigned int target_freq,
			      unsigned int relation)
{
	struct pxa3xx_freq_info *next;
	struct cpufreq_freqs freqs;
	unsigned long flags;
	int idx;

	if (policy->cpu != 0)
		return -EINVAL;

	/* Lookup the next frequency */
	if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
				target_freq, relation, &idx))
		return -EINVAL;

	next = &pxa3xx_freqs[idx];

	freqs.old = policy->cur;
	freqs.new = next->cpufreq_mhz * 1000;

	pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
			freqs.old / 1000, freqs.new / 1000,
			(freqs.old == freqs.new) ? " (skipped)" : "");

	if (freqs.old == target_freq)
		return 0;

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);

	local_irq_save(flags);
	__update_core_freq(next);
	__update_bus_freq(next);
	local_irq_restore(flags);

	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);

	return 0;
}

static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
{
	int ret = -EINVAL;

	/* set default policy and cpuinfo */
	policy->min = policy->cpuinfo.min_freq = 104000;
	policy->max = policy->cpuinfo.max_freq =
		(cpu_is_pxa320()) ? 806000 : 624000;
	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */

	if (cpu_is_pxa300() || cpu_is_pxa310())
		ret = setup_freqs_table(policy, pxa300_freqs,
					ARRAY_SIZE(pxa300_freqs));

	if (cpu_is_pxa320())
		ret = setup_freqs_table(policy, pxa320_freqs,
					ARRAY_SIZE(pxa320_freqs));

	if (ret) {
		pr_err("failed to setup frequency table\n");
		return ret;
	}

	pr_info("CPUFREQ support for PXA3xx initialized\n");
	return 0;
}

static struct cpufreq_driver pxa3xx_cpufreq_driver = {
	.verify		= cpufreq_generic_frequency_table_verify,
	.target		= pxa3xx_cpufreq_set,
	.init		= pxa3xx_cpufreq_init,
	.exit		= cpufreq_generic_exit,
	.get		= pxa3xx_cpufreq_get,
	.name		= "pxa3xx-cpufreq",
};

static int __init cpufreq_init(void)
{
	if (cpu_is_pxa3xx())
		return cpufreq_register_driver(&pxa3xx_cpufreq_driver);

	return 0;
}
module_init(cpufreq_init);

static void __exit cpufreq_exit(void)
{
	cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
}
module_exit(cpufreq_exit);

MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
MODULE_LICENSE("GPL");
Commit	Line	Data
4f788bb2	1	/*
4f788bb2 EM	2	* Copyright (C) 2008 Marvell International Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/sched.h>
	13	#include <linux/init.h>
	14	#include <linux/cpufreq.h>
5a0e3ad6	15	#include <linux/slab.h>
23019a73	16	#include <linux/io.h>
4f788bb2	17
adde904b	18	#include <mach/generic.h>
4f788bb2 EM	19	#include <mach/pxa3xx-regs.h>
4f788bb2 EM	20
4f788bb2 EM	21	#define HSS_104M (0)
	22	#define HSS_156M (1)
	23	#define HSS_208M (2)
	24	#define HSS_312M (3)
	25
	26	#define SMCFS_78M (0)
	27	#define SMCFS_104M (2)
	28	#define SMCFS_208M (5)
	29
	30	#define SFLFS_104M (0)
	31	#define SFLFS_156M (1)
	32	#define SFLFS_208M (2)
	33	#define SFLFS_312M (3)
	34
	35	#define XSPCLK_156M (0)
	36	#define XSPCLK_NONE (3)
	37
	38	#define DMCFS_26M (0)
	39	#define DMCFS_260M (3)
	40
	41	struct pxa3xx_freq_info {
	42	unsigned int cpufreq_mhz;
	43	unsigned int core_xl : 5;
	44	unsigned int core_xn : 3;
	45	unsigned int hss : 2;
	46	unsigned int dmcfs : 2;
	47	unsigned int smcfs : 3;
	48	unsigned int sflfs : 2;
	49	unsigned int df_clkdiv : 3;
	50
	51	int vcc_core; /* in mV */
	52	int vcc_sram; /* in mV */
	53	};
	54
	55	#define OP(cpufreq, _xl, _xn, _hss, _dmc, _smc, _sfl, _dfi, vcore, vsram) \
	56	{ \
	57	.cpufreq_mhz = cpufreq, \
	58	.core_xl = _xl, \
	59	.core_xn = _xn, \
	60	.hss = HSS_##_hss##M, \
	61	.dmcfs = DMCFS_##_dmc##M, \
	62	.smcfs = SMCFS_##_smc##M, \
	63	.sflfs = SFLFS_##_sfl##M, \
	64	.df_clkdiv = _dfi, \
	65	.vcc_core = vcore, \
	66	.vcc_sram = vsram, \
	67	}
	68
	69	static struct pxa3xx_freq_info pxa300_freqs[] = {
	70	/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
	71	OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
	72	OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
	73	OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
	74	OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
	75	};
	76
	77	static struct pxa3xx_freq_info pxa320_freqs[] = {
	78	/* CPU XL XN HSS DMEM SMEM SRAM DFI VCC_CORE VCC_SRAM */
	79	OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
	80	OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
	81	OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
	82	OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
	83	OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
	84	};
85
86	static unsigned int pxa3xx_freqs_num;
87	static struct pxa3xx_freq_info *pxa3xx_freqs;
88	static struct cpufreq_frequency_table *pxa3xx_freqs_table;
89
90	static int setup_freqs_table(struct cpufreq_policy *policy,
91	struct pxa3xx_freq_info *freqs, int num)
92	{
93	struct cpufreq_frequency_table *table;
15cc921b	94	int i;
4f788bb2 EM	95
	96	table = kzalloc((num + 1) * sizeof(*table), GFP_KERNEL);
	97	if (table == NULL)
	98	return -ENOMEM;
	99
	100	for (i = 0; i < num; i++) {
50701588	101	table[i].driver_data = i;
4f788bb2 EM	102	table[i].frequency = freqs[i].cpufreq_mhz * 1000;
4f788bb2 EM	103	}
50701588	104	table[num].driver_data = i;
4f788bb2 EM	105	table[num].frequency = CPUFREQ_TABLE_END;
	106
	107	pxa3xx_freqs = freqs;
	108	pxa3xx_freqs_num = num;
	109	pxa3xx_freqs_table = table;
	110
15cc921b	111	return cpufreq_table_validate_and_show(policy, table);
4f788bb2 EM	112	}
	113
	114	static void __update_core_freq(struct pxa3xx_freq_info *info)
	115	{
	116	uint32_t mask = ACCR_XN_MASK \| ACCR_XL_MASK;
	117	uint32_t accr = ACCR;
	118	uint32_t xclkcfg;
	119
	120	accr &= ~(ACCR_XN_MASK \| ACCR_XL_MASK \| ACCR_XSPCLK_MASK);
	121	accr \|= ACCR_XN(info->core_xn) \| ACCR_XL(info->core_xl);
	122
	123	/* No clock until core PLL is re-locked */
	124	accr \|= ACCR_XSPCLK(XSPCLK_NONE);
	125
	126	xclkcfg = (info->core_xn == 2) ? 0x3 : 0x2; /* turbo bit */
	127
	128	ACCR = accr;
	129	__asm__("mcr p14, 0, %0, c6, c0, 0\n" : : "r"(xclkcfg));
	130
	131	while ((ACSR & mask) != (accr & mask))
	132	cpu_relax();
	133	}
	134
	135	static void __update_bus_freq(struct pxa3xx_freq_info *info)
	136	{
	137	uint32_t mask;
	138	uint32_t accr = ACCR;
	139
	140	mask = ACCR_SMCFS_MASK \| ACCR_SFLFS_MASK \| ACCR_HSS_MASK \|
	141	ACCR_DMCFS_MASK;
	142
	143	accr &= ~mask;
	144	accr \|= ACCR_SMCFS(info->smcfs) \| ACCR_SFLFS(info->sflfs) \|
	145	ACCR_HSS(info->hss) \| ACCR_DMCFS(info->dmcfs);
	146
	147	ACCR = accr;
	148
	149	while ((ACSR & mask) != (accr & mask))
	150	cpu_relax();
	151	}
	152
4f788bb2 EM	153	static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
4f788bb2 EM	154	{
ecf89b8a	155	return pxa3xx_get_clk_frequency_khz(0);
4f788bb2 EM	156	}
	157
	158	static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
	159	unsigned int target_freq,
	160	unsigned int relation)
	161	{
	162	struct pxa3xx_freq_info *next;
	163	struct cpufreq_freqs freqs;
	164	unsigned long flags;
	165	int idx;
	166
	167	if (policy->cpu != 0)
	168	return -EINVAL;
	169
	170	/* Lookup the next frequency */
	171	if (cpufreq_frequency_table_target(policy, pxa3xx_freqs_table,
	172	target_freq, relation, &idx))
	173	return -EINVAL;
	174
	175	next = &pxa3xx_freqs[idx];
	176
	177	freqs.old = policy->cur;
	178	freqs.new = next->cpufreq_mhz * 1000;
4f788bb2 EM	179
	180	pr_debug("CPU frequency from %d MHz to %d MHz%s\n",
	181	freqs.old / 1000, freqs.new / 1000,
	182	(freqs.old == freqs.new) ? " (skipped)" : "");
	183
	184	if (freqs.old == target_freq)
	185	return 0;
	186
b43a7ffb	187	cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
4f788bb2 EM	188
	189	local_irq_save(flags);
	190	__update_core_freq(next);
	191	__update_bus_freq(next);
	192	local_irq_restore(flags);
	193
b43a7ffb	194	cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
4f788bb2 EM	195
	196	return 0;
	197	}
	198
50e77fcd	199	static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
4f788bb2 EM	200	{
	201	int ret = -EINVAL;
	202
	203	/* set default policy and cpuinfo */
200ea8e2 VK	204	policy->min = policy->cpuinfo.min_freq = 104000;
	205	policy->max = policy->cpuinfo.max_freq =
	206	(cpu_is_pxa320()) ? 806000 : 624000;
4f788bb2	207	policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
4f788bb2 EM	208
4f788bb2 EM	209	if (cpu_is_pxa300() \|\| cpu_is_pxa310())
8ee3f8e0 JL	210	ret = setup_freqs_table(policy, pxa300_freqs,
8ee3f8e0 JL	211	ARRAY_SIZE(pxa300_freqs));
4f788bb2 EM	212
4f788bb2 EM	213	if (cpu_is_pxa320())
8ee3f8e0 JL	214	ret = setup_freqs_table(policy, pxa320_freqs,
8ee3f8e0 JL	215	ARRAY_SIZE(pxa320_freqs));
4f788bb2 EM	216
	217	if (ret) {
	218	pr_err("failed to setup frequency table\n");
	219	return ret;
	220	}
	221
	222	pr_info("CPUFREQ support for PXA3xx initialized\n");
	223	return 0;
	224	}
	225
	226	static struct cpufreq_driver pxa3xx_cpufreq_driver = {
bf36e48d	227	.verify = cpufreq_generic_frequency_table_verify,
4f788bb2 EM	228	.target = pxa3xx_cpufreq_set,
4f788bb2 EM	229	.init = pxa3xx_cpufreq_init,
bf36e48d	230	.exit = cpufreq_generic_exit,
4f788bb2 EM	231	.get = pxa3xx_cpufreq_get,
	232	.name = "pxa3xx-cpufreq",
	233	};
	234
	235	static int __init cpufreq_init(void)
	236	{
	237	if (cpu_is_pxa3xx())
	238	return cpufreq_register_driver(&pxa3xx_cpufreq_driver);
	239
	240	return 0;
	241	}
	242	module_init(cpufreq_init);
	243
	244	static void __exit cpufreq_exit(void)
	245	{
	246	cpufreq_unregister_driver(&pxa3xx_cpufreq_driver);
	247	}
	248	module_exit(cpufreq_exit);
	249
	250	MODULE_DESCRIPTION("CPU frequency scaling driver for PXA3xx");
	251	MODULE_LICENSE("GPL");