[mirror_ubuntu-eoan-kernel.git] / drivers / cpufreq / qcom-cpufreq-hw.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <linux/bitfield.h>
#include <linux/cpufreq.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>

#define LUT_MAX_ENTRIES			40U
#define LUT_SRC				GENMASK(31, 30)
#define LUT_L_VAL			GENMASK(7, 0)
#define LUT_CORE_COUNT			GENMASK(18, 16)
#define LUT_VOLT			GENMASK(11, 0)
#define LUT_ROW_SIZE			32
#define CLK_HW_DIV			2

/* Register offsets */
#define REG_ENABLE			0x0
#define REG_FREQ_LUT			0x110
#define REG_VOLT_LUT			0x114
#define REG_PERF_STATE			0x920

static unsigned long cpu_hw_rate, xo_rate;
static struct platform_device *global_pdev;

static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
					unsigned int index)
{
	void __iomem *perf_state_reg = policy->driver_data;

	writel_relaxed(index, perf_state_reg);

	return 0;
}

static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
{
	void __iomem *perf_state_reg;
	struct cpufreq_policy *policy;
	unsigned int index;

	policy = cpufreq_cpu_get_raw(cpu);
	if (!policy)
		return 0;

	perf_state_reg = policy->driver_data;

	index = readl_relaxed(perf_state_reg);
	index = min(index, LUT_MAX_ENTRIES - 1);

	return policy->freq_table[index].frequency;
}

static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
						unsigned int target_freq)
{
	void __iomem *perf_state_reg = policy->driver_data;
	int index;

	index = policy->cached_resolved_idx;
	if (index < 0)
		return 0;

	writel_relaxed(index, perf_state_reg);

	return policy->freq_table[index].frequency;
}

static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
				    struct cpufreq_policy *policy,
				    void __iomem *base)
{
	u32 data, src, lval, i, core_count, prev_cc = 0, prev_freq = 0, freq;
	u32 volt;
	unsigned int max_cores = cpumask_weight(policy->cpus);
	struct cpufreq_frequency_table	*table;

	table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
	if (!table)
		return -ENOMEM;

	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
		data = readl_relaxed(base + REG_FREQ_LUT +
				      i * LUT_ROW_SIZE);
		src = FIELD_GET(LUT_SRC, data);
		lval = FIELD_GET(LUT_L_VAL, data);
		core_count = FIELD_GET(LUT_CORE_COUNT, data);

		data = readl_relaxed(base + REG_VOLT_LUT +
				      i * LUT_ROW_SIZE);
		volt = FIELD_GET(LUT_VOLT, data) * 1000;

		if (src)
			freq = xo_rate * lval / 1000;
		else
			freq = cpu_hw_rate / 1000;

		if (freq != prev_freq && core_count == max_cores) {
			table[i].frequency = freq;
			dev_pm_opp_add(cpu_dev, freq * 1000, volt);
			dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
				freq, core_count);
		} else {
			table[i].frequency = CPUFREQ_ENTRY_INVALID;
		}

		/*
		 * Two of the same frequencies with the same core counts means
		 * end of table
		 */
		if (i > 0 && prev_freq == freq && prev_cc == core_count) {
			struct cpufreq_frequency_table *prev = &table[i - 1];

			/*
			 * Only treat the last frequency that might be a boost
			 * as the boost frequency
			 */
			if (prev_cc != max_cores) {
				prev->frequency = prev_freq;
				prev->flags = CPUFREQ_BOOST_FREQ;
				dev_pm_opp_add(cpu_dev,	prev_freq * 1000, volt);
			}

			break;
		}

		prev_cc = core_count;
		prev_freq = freq;
	}

	table[i].frequency = CPUFREQ_TABLE_END;
	policy->freq_table = table;
	dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);

	return 0;
}

static void qcom_get_related_cpus(int index, struct cpumask *m)
{
	struct device_node *cpu_np;
	struct of_phandle_args args;
	int cpu, ret;

	for_each_possible_cpu(cpu) {
		cpu_np = of_cpu_device_node_get(cpu);
		if (!cpu_np)
			continue;

		ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
						 "#freq-domain-cells", 0,
						 &args);
		of_node_put(cpu_np);
		if (ret < 0)
			continue;

		if (index == args.args[0])
			cpumask_set_cpu(cpu, m);
	}
}

static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
{
	struct device *dev = &global_pdev->dev;
	struct of_phandle_args args;
	struct device_node *cpu_np;
	struct device *cpu_dev;
	struct resource *res;
	void __iomem *base;
	int ret, index;

	cpu_dev = get_cpu_device(policy->cpu);
	if (!cpu_dev) {
		pr_err("%s: failed to get cpu%d device\n", __func__,
		       policy->cpu);
		return -ENODEV;
	}

	cpu_np = of_cpu_device_node_get(policy->cpu);
	if (!cpu_np)
		return -EINVAL;

	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
					 "#freq-domain-cells", 0, &args);
	of_node_put(cpu_np);
	if (ret)
		return ret;

	index = args.args[0];

	res = platform_get_resource(global_pdev, IORESOURCE_MEM, index);
	if (!res)
		return -ENODEV;

	base = devm_ioremap(dev, res->start, resource_size(res));
	if (!base)
		return -ENOMEM;

	/* HW should be in enabled state to proceed */
	if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
		dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
		ret = -ENODEV;
		goto error;
	}

	qcom_get_related_cpus(index, policy->cpus);
	if (!cpumask_weight(policy->cpus)) {
		dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
		ret = -ENOENT;
		goto error;
	}

	policy->driver_data = base + REG_PERF_STATE;

	ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
	if (ret) {
		dev_err(dev, "Domain-%d failed to read LUT\n", index);
		goto error;
	}

	ret = dev_pm_opp_get_opp_count(cpu_dev);
	if (ret <= 0) {
		dev_err(cpu_dev, "Failed to add OPPs\n");
		ret = -ENODEV;
		goto error;
	}

	dev_pm_opp_of_register_em(policy->cpus);

	policy->fast_switch_possible = true;

	return 0;
error:
	devm_iounmap(dev, base);
	return ret;
}

static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
{
	struct device *cpu_dev = get_cpu_device(policy->cpu);
	void __iomem *base = policy->driver_data - REG_PERF_STATE;

	dev_pm_opp_remove_all_dynamic(cpu_dev);
	kfree(policy->freq_table);
	devm_iounmap(&global_pdev->dev, base);

	return 0;
}

static struct freq_attr *qcom_cpufreq_hw_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	&cpufreq_freq_attr_scaling_boost_freqs,
	NULL
};

static struct cpufreq_driver cpufreq_qcom_hw_driver = {
	.flags		= CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
			  CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
			  CPUFREQ_IS_COOLING_DEV,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qcom_cpufreq_hw_target_index,
	.get		= qcom_cpufreq_hw_get,
	.init		= qcom_cpufreq_hw_cpu_init,
	.exit		= qcom_cpufreq_hw_cpu_exit,
	.fast_switch    = qcom_cpufreq_hw_fast_switch,
	.name		= "qcom-cpufreq-hw",
	.attr		= qcom_cpufreq_hw_attr,
};

static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
{
	struct clk *clk;
	int ret;

	clk = clk_get(&pdev->dev, "xo");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	xo_rate = clk_get_rate(clk);
	clk_put(clk);

	clk = clk_get(&pdev->dev, "alternate");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
	clk_put(clk);

	global_pdev = pdev;

	ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
	if (ret)
		dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
	else
		dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");

	return ret;
}

static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
{
	return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
}

static const struct of_device_id qcom_cpufreq_hw_match[] = {
	{ .compatible = "qcom,cpufreq-hw" },
	{}
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);

static struct platform_driver qcom_cpufreq_hw_driver = {
	.probe = qcom_cpufreq_hw_driver_probe,
	.remove = qcom_cpufreq_hw_driver_remove,
	.driver = {
		.name = "qcom-cpufreq-hw",
		.of_match_table = qcom_cpufreq_hw_match,
	},
};

static int __init qcom_cpufreq_hw_init(void)
{
	return platform_driver_register(&qcom_cpufreq_hw_driver);
}
device_initcall(qcom_cpufreq_hw_init);

static void __exit qcom_cpufreq_hw_exit(void)
{
	platform_driver_unregister(&qcom_cpufreq_hw_driver);
}
module_exit(qcom_cpufreq_hw_exit);

MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2849dd8b TD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/cpufreq.h>
	8	#include <linux/init.h>
	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/of_address.h>
	12	#include <linux/of_platform.h>
55538fbc	13	#include <linux/pm_opp.h>
2849dd8b TD	14	#include <linux/slab.h>
	15
	16	#define LUT_MAX_ENTRIES 40U
	17	#define LUT_SRC GENMASK(31, 30)
	18	#define LUT_L_VAL GENMASK(7, 0)
	19	#define LUT_CORE_COUNT GENMASK(18, 16)
55538fbc	20	#define LUT_VOLT GENMASK(11, 0)
2849dd8b TD	21	#define LUT_ROW_SIZE 32
	22	#define CLK_HW_DIV 2
	23
	24	/* Register offsets */
	25	#define REG_ENABLE 0x0
55538fbc TD	26	#define REG_FREQ_LUT 0x110
55538fbc TD	27	#define REG_VOLT_LUT 0x114
2849dd8b TD	28	#define REG_PERF_STATE 0x920
	29
	30	static unsigned long cpu_hw_rate, xo_rate;
	31	static struct platform_device *global_pdev;
	32
	33	static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
	34	unsigned int index)
	35	{
	36	void __iomem *perf_state_reg = policy->driver_data;
	37
	38	writel_relaxed(index, perf_state_reg);
	39
	40	return 0;
	41	}
	42
	43	static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
	44	{
	45	void __iomem *perf_state_reg;
	46	struct cpufreq_policy *policy;
	47	unsigned int index;
	48
	49	policy = cpufreq_cpu_get_raw(cpu);
	50	if (!policy)
	51	return 0;
	52
	53	perf_state_reg = policy->driver_data;
	54
	55	index = readl_relaxed(perf_state_reg);
	56	index = min(index, LUT_MAX_ENTRIES - 1);
	57
	58	return policy->freq_table[index].frequency;
	59	}
	60
	61	static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
	62	unsigned int target_freq)
	63	{
	64	void __iomem *perf_state_reg = policy->driver_data;
	65	int index;
	66
	67	index = policy->cached_resolved_idx;
	68	if (index < 0)
	69	return 0;
	70
	71	writel_relaxed(index, perf_state_reg);
	72
	73	return policy->freq_table[index].frequency;
	74	}
	75
55538fbc	76	static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
2849dd8b TD	77	struct cpufreq_policy *policy,
	78	void __iomem *base)
	79	{
	80	u32 data, src, lval, i, core_count, prev_cc = 0, prev_freq = 0, freq;
55538fbc	81	u32 volt;
2849dd8b TD	82	unsigned int max_cores = cpumask_weight(policy->cpus);
	83	struct cpufreq_frequency_table *table;
	84
	85	table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
	86	if (!table)
	87	return -ENOMEM;
	88
	89	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
55538fbc TD	90	data = readl_relaxed(base + REG_FREQ_LUT +
55538fbc TD	91	i * LUT_ROW_SIZE);
2849dd8b TD	92	src = FIELD_GET(LUT_SRC, data);
	93	lval = FIELD_GET(LUT_L_VAL, data);
	94	core_count = FIELD_GET(LUT_CORE_COUNT, data);
	95
55538fbc TD	96	data = readl_relaxed(base + REG_VOLT_LUT +
	97	i * LUT_ROW_SIZE);
	98	volt = FIELD_GET(LUT_VOLT, data) * 1000;
	99
2849dd8b TD	100	if (src)
	101	freq = xo_rate * lval / 1000;
	102	else
	103	freq = cpu_hw_rate / 1000;
	104
55538fbc	105	if (freq != prev_freq && core_count == max_cores) {
2849dd8b	106	table[i].frequency = freq;
55538fbc TD	107	dev_pm_opp_add(cpu_dev, freq * 1000, volt);
55538fbc TD	108	dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
2849dd8b	109	freq, core_count);
55538fbc TD	110	} else {
55538fbc TD	111	table[i].frequency = CPUFREQ_ENTRY_INVALID;
2849dd8b TD	112	}
	113
	114	/*
	115	* Two of the same frequencies with the same core counts means
	116	* end of table
	117	*/
	118	if (i > 0 && prev_freq == freq && prev_cc == core_count) {
	119	struct cpufreq_frequency_table *prev = &table[i - 1];
	120
	121	/*
	122	* Only treat the last frequency that might be a boost
	123	* as the boost frequency
	124	*/
	125	if (prev_cc != max_cores) {
	126	prev->frequency = prev_freq;
	127	prev->flags = CPUFREQ_BOOST_FREQ;
55538fbc	128	dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt);
2849dd8b TD	129	}
	130
	131	break;
	132	}
	133
	134	prev_cc = core_count;
	135	prev_freq = freq;
	136	}
	137
	138	table[i].frequency = CPUFREQ_TABLE_END;
	139	policy->freq_table = table;
55538fbc	140	dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
2849dd8b TD	141
	142	return 0;
	143	}
	144
	145	static void qcom_get_related_cpus(int index, struct cpumask *m)
	146	{
	147	struct device_node *cpu_np;
	148	struct of_phandle_args args;
	149	int cpu, ret;
	150
	151	for_each_possible_cpu(cpu) {
	152	cpu_np = of_cpu_device_node_get(cpu);
	153	if (!cpu_np)
	154	continue;
	155
	156	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
	157	"#freq-domain-cells", 0,
	158	&args);
	159	of_node_put(cpu_np);
	160	if (ret < 0)
	161	continue;
	162
	163	if (index == args.args[0])
	164	cpumask_set_cpu(cpu, m);
	165	}
	166	}
	167
	168	static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
	169	{
	170	struct device *dev = &global_pdev->dev;
	171	struct of_phandle_args args;
	172	struct device_node *cpu_np;
55538fbc	173	struct device *cpu_dev;
2849dd8b TD	174	struct resource *res;
	175	void __iomem *base;
	176	int ret, index;
	177
55538fbc TD	178	cpu_dev = get_cpu_device(policy->cpu);
	179	if (!cpu_dev) {
	180	pr_err("%s: failed to get cpu%d device\n", __func__,
	181	policy->cpu);
	182	return -ENODEV;
	183	}
	184
2849dd8b TD	185	cpu_np = of_cpu_device_node_get(policy->cpu);
	186	if (!cpu_np)
	187	return -EINVAL;
	188
	189	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
	190	"#freq-domain-cells", 0, &args);
	191	of_node_put(cpu_np);
	192	if (ret)
	193	return ret;
	194
	195	index = args.args[0];
	196
	197	res = platform_get_resource(global_pdev, IORESOURCE_MEM, index);
	198	if (!res)
	199	return -ENODEV;
	200
	201	base = devm_ioremap(dev, res->start, resource_size(res));
	202	if (!base)
	203	return -ENOMEM;
	204
	205	/* HW should be in enabled state to proceed */
	206	if (!(readl_relaxed(base + REG_ENABLE) & 0x1)) {
	207	dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
	208	ret = -ENODEV;
	209	goto error;
	210	}
	211
	212	qcom_get_related_cpus(index, policy->cpus);
	213	if (!cpumask_weight(policy->cpus)) {
	214	dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
	215	ret = -ENOENT;
	216	goto error;
	217	}
	218
	219	policy->driver_data = base + REG_PERF_STATE;
	220
55538fbc	221	ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy, base);
2849dd8b TD	222	if (ret) {
	223	dev_err(dev, "Domain-%d failed to read LUT\n", index);
	224	goto error;
	225	}
	226
55538fbc TD	227	ret = dev_pm_opp_get_opp_count(cpu_dev);
	228	if (ret <= 0) {
	229	dev_err(cpu_dev, "Failed to add OPPs\n");
	230	ret = -ENODEV;
	231	goto error;
	232	}
	233
dab53505 MK	234	dev_pm_opp_of_register_em(policy->cpus);
dab53505 MK	235
2849dd8b TD	236	policy->fast_switch_possible = true;
	237
	238	return 0;
	239	error:
	240	devm_iounmap(dev, base);
	241	return ret;
	242	}
	243
	244	static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
	245	{
55538fbc	246	struct device *cpu_dev = get_cpu_device(policy->cpu);
2849dd8b TD	247	void __iomem *base = policy->driver_data - REG_PERF_STATE;
2849dd8b TD	248
55538fbc	249	dev_pm_opp_remove_all_dynamic(cpu_dev);
2849dd8b TD	250	kfree(policy->freq_table);
	251	devm_iounmap(&global_pdev->dev, base);
	252
	253	return 0;
	254	}
	255
	256	static struct freq_attr *qcom_cpufreq_hw_attr[] = {
	257	&cpufreq_freq_attr_scaling_available_freqs,
	258	&cpufreq_freq_attr_scaling_boost_freqs,
	259	NULL
	260	};
	261
	262	static struct cpufreq_driver cpufreq_qcom_hw_driver = {
	263	.flags = CPUFREQ_STICKY \| CPUFREQ_NEED_INITIAL_FREQ_CHECK \|
4c5ff1c8 AK	264	CPUFREQ_HAVE_GOVERNOR_PER_POLICY \|
4c5ff1c8 AK	265	CPUFREQ_IS_COOLING_DEV,
2849dd8b TD	266	.verify = cpufreq_generic_frequency_table_verify,
	267	.target_index = qcom_cpufreq_hw_target_index,
	268	.get = qcom_cpufreq_hw_get,
	269	.init = qcom_cpufreq_hw_cpu_init,
	270	.exit = qcom_cpufreq_hw_cpu_exit,
	271	.fast_switch = qcom_cpufreq_hw_fast_switch,
	272	.name = "qcom-cpufreq-hw",
	273	.attr = qcom_cpufreq_hw_attr,
	274	};
	275
	276	static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
	277	{
	278	struct clk *clk;
	279	int ret;
	280
	281	clk = clk_get(&pdev->dev, "xo");
	282	if (IS_ERR(clk))
	283	return PTR_ERR(clk);
	284
	285	xo_rate = clk_get_rate(clk);
	286	clk_put(clk);
	287
	288	clk = clk_get(&pdev->dev, "alternate");
	289	if (IS_ERR(clk))
	290	return PTR_ERR(clk);
	291
	292	cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
	293	clk_put(clk);
	294
	295	global_pdev = pdev;
	296
	297	ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
	298	if (ret)
	299	dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
	300	else
	301	dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
	302
	303	return ret;
	304	}
	305
	306	static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
	307	{
	308	return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
	309	}
	310
	311	static const struct of_device_id qcom_cpufreq_hw_match[] = {
	312	{ .compatible = "qcom,cpufreq-hw" },
	313	{}
	314	};
	315	MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
	316
	317	static struct platform_driver qcom_cpufreq_hw_driver = {
	318	.probe = qcom_cpufreq_hw_driver_probe,
	319	.remove = qcom_cpufreq_hw_driver_remove,
	320	.driver = {
	321	.name = "qcom-cpufreq-hw",
	322	.of_match_table = qcom_cpufreq_hw_match,
	323	},
	324	};
	325
	326	static int __init qcom_cpufreq_hw_init(void)
	327	{
	328	return platform_driver_register(&qcom_cpufreq_hw_driver);
	329	}
f896d066	330	device_initcall(qcom_cpufreq_hw_init);
2849dd8b TD	331
	332	static void __exit qcom_cpufreq_hw_exit(void)
	333	{
	334	platform_driver_unregister(&qcom_cpufreq_hw_driver);
	335	}
	336	module_exit(qcom_cpufreq_hw_exit);
	337
	338	MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
	339	MODULE_LICENSE("GPL v2");