[mirror_ubuntu-jammy-kernel.git] / drivers / cpufreq / qcom-cpufreq-hw.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
 */

#include <linux/bitfield.h>
#include <linux/cpufreq.h>
#include <linux/init.h>
#include <linux/interconnect.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
#include <linux/slab.h>

#define LUT_MAX_ENTRIES			40U
#define LUT_SRC				GENMASK(31, 30)
#define LUT_L_VAL			GENMASK(7, 0)
#define LUT_CORE_COUNT			GENMASK(18, 16)
#define LUT_VOLT			GENMASK(11, 0)
#define CLK_HW_DIV			2
#define LUT_TURBO_IND			1

struct qcom_cpufreq_soc_data {
	u32 reg_enable;
	u32 reg_freq_lut;
	u32 reg_volt_lut;
	u32 reg_perf_state;
	u8 lut_row_size;
};

struct qcom_cpufreq_data {
	void __iomem *base;
	struct resource *res;
	const struct qcom_cpufreq_soc_data *soc_data;
};

static unsigned long cpu_hw_rate, xo_rate;
static bool icc_scaling_enabled;

static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
			       unsigned long freq_khz)
{
	unsigned long freq_hz = freq_khz * 1000;
	struct dev_pm_opp *opp;
	struct device *dev;
	int ret;

	dev = get_cpu_device(policy->cpu);
	if (!dev)
		return -ENODEV;

	opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
	if (IS_ERR(opp))
		return PTR_ERR(opp);

	ret = dev_pm_opp_set_opp(dev, opp);
	dev_pm_opp_put(opp);
	return ret;
}

static int qcom_cpufreq_update_opp(struct device *cpu_dev,
				   unsigned long freq_khz,
				   unsigned long volt)
{
	unsigned long freq_hz = freq_khz * 1000;
	int ret;

	/* Skip voltage update if the opp table is not available */
	if (!icc_scaling_enabled)
		return dev_pm_opp_add(cpu_dev, freq_hz, volt);

	ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
	if (ret) {
		dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
		return ret;
	}

	return dev_pm_opp_enable(cpu_dev, freq_hz);
}

static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
					unsigned int index)
{
	struct qcom_cpufreq_data *data = policy->driver_data;
	const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
	unsigned long freq = policy->freq_table[index].frequency;

	writel_relaxed(index, data->base + soc_data->reg_perf_state);

	if (icc_scaling_enabled)
		qcom_cpufreq_set_bw(policy, freq);

	return 0;
}

static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
{
	struct qcom_cpufreq_data *data;
	const struct qcom_cpufreq_soc_data *soc_data;
	struct cpufreq_policy *policy;
	unsigned int index;

	policy = cpufreq_cpu_get_raw(cpu);
	if (!policy)
		return 0;

	data = policy->driver_data;
	soc_data = data->soc_data;

	index = readl_relaxed(data->base + soc_data->reg_perf_state);
	index = min(index, LUT_MAX_ENTRIES - 1);

	return policy->freq_table[index].frequency;
}

static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
						unsigned int target_freq)
{
	struct qcom_cpufreq_data *data = policy->driver_data;
	const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
	unsigned int index;

	index = policy->cached_resolved_idx;
	writel_relaxed(index, data->base + soc_data->reg_perf_state);

	return policy->freq_table[index].frequency;
}

static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
				    struct cpufreq_policy *policy)
{
	u32 data, src, lval, i, core_count, prev_freq = 0, freq;
	u32 volt;
	struct cpufreq_frequency_table	*table;
	struct dev_pm_opp *opp;
	unsigned long rate;
	int ret;
	struct qcom_cpufreq_data *drv_data = policy->driver_data;
	const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;

	table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
	if (!table)
		return -ENOMEM;

	ret = dev_pm_opp_of_add_table(cpu_dev);
	if (!ret) {
		/* Disable all opps and cross-validate against LUT later */
		icc_scaling_enabled = true;
		for (rate = 0; ; rate++) {
			opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
			if (IS_ERR(opp))
				break;

			dev_pm_opp_put(opp);
			dev_pm_opp_disable(cpu_dev, rate);
		}
	} else if (ret != -ENODEV) {
		dev_err(cpu_dev, "Invalid opp table in device tree\n");
		return ret;
	} else {
		policy->fast_switch_possible = true;
		icc_scaling_enabled = false;
	}

	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
		data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
				      i * soc_data->lut_row_size);
		src = FIELD_GET(LUT_SRC, data);
		lval = FIELD_GET(LUT_L_VAL, data);
		core_count = FIELD_GET(LUT_CORE_COUNT, data);

		data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
				      i * soc_data->lut_row_size);
		volt = FIELD_GET(LUT_VOLT, data) * 1000;

		if (src)
			freq = xo_rate * lval / 1000;
		else
			freq = cpu_hw_rate / 1000;

		if (freq != prev_freq && core_count != LUT_TURBO_IND) {
			if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
				table[i].frequency = freq;
				dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
				freq, core_count);
			} else {
				dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
				table[i].frequency = CPUFREQ_ENTRY_INVALID;
			}

		} else if (core_count == LUT_TURBO_IND) {
			table[i].frequency = CPUFREQ_ENTRY_INVALID;
		}

		/*
		 * Two of the same frequencies with the same core counts means
		 * end of table
		 */
		if (i > 0 && prev_freq == freq) {
			struct cpufreq_frequency_table *prev = &table[i - 1];

			/*
			 * Only treat the last frequency that might be a boost
			 * as the boost frequency
			 */
			if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
				if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
					prev->frequency = prev_freq;
					prev->flags = CPUFREQ_BOOST_FREQ;
				} else {
					dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
						 freq);
				}
			}

			break;
		}

		prev_freq = freq;
	}

	table[i].frequency = CPUFREQ_TABLE_END;
	policy->freq_table = table;
	dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);

	return 0;
}

static void qcom_get_related_cpus(int index, struct cpumask *m)
{
	struct device_node *cpu_np;
	struct of_phandle_args args;
	int cpu, ret;

	for_each_possible_cpu(cpu) {
		cpu_np = of_cpu_device_node_get(cpu);
		if (!cpu_np)
			continue;

		ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
						 "#freq-domain-cells", 0,
						 &args);
		of_node_put(cpu_np);
		if (ret < 0)
			continue;

		if (index == args.args[0])
			cpumask_set_cpu(cpu, m);
	}
}

static const struct qcom_cpufreq_soc_data qcom_soc_data = {
	.reg_enable = 0x0,
	.reg_freq_lut = 0x110,
	.reg_volt_lut = 0x114,
	.reg_perf_state = 0x920,
	.lut_row_size = 32,
};

static const struct qcom_cpufreq_soc_data epss_soc_data = {
	.reg_enable = 0x0,
	.reg_freq_lut = 0x100,
	.reg_volt_lut = 0x200,
	.reg_perf_state = 0x320,
	.lut_row_size = 4,
};

static const struct of_device_id qcom_cpufreq_hw_match[] = {
	{ .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
	{ .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
	{}
};
MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);

static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
{
	struct platform_device *pdev = cpufreq_get_driver_data();
	struct device *dev = &pdev->dev;
	struct of_phandle_args args;
	struct device_node *cpu_np;
	struct device *cpu_dev;
	struct resource *res;
	void __iomem *base;
	struct qcom_cpufreq_data *data;
	int ret, index;

	cpu_dev = get_cpu_device(policy->cpu);
	if (!cpu_dev) {
		pr_err("%s: failed to get cpu%d device\n", __func__,
		       policy->cpu);
		return -ENODEV;
	}

	cpu_np = of_cpu_device_node_get(policy->cpu);
	if (!cpu_np)
		return -EINVAL;

	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
					 "#freq-domain-cells", 0, &args);
	of_node_put(cpu_np);
	if (ret)
		return ret;

	index = args.args[0];

	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
	if (!res) {
		dev_err(dev, "failed to get mem resource %d\n", index);
		return -ENODEV;
	}

	if (!request_mem_region(res->start, resource_size(res), res->name)) {
		dev_err(dev, "failed to request resource %pR\n", res);
		return -EBUSY;
	}

	base = ioremap(res->start, resource_size(res));
	if (!base) {
		dev_err(dev, "failed to map resource %pR\n", res);
		ret = -ENOMEM;
		goto release_region;
	}

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data) {
		ret = -ENOMEM;
		goto unmap_base;
	}

	data->soc_data = of_device_get_match_data(&pdev->dev);
	data->base = base;
	data->res = res;

	/* HW should be in enabled state to proceed */
	if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
		dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
		ret = -ENODEV;
		goto error;
	}

	qcom_get_related_cpus(index, policy->cpus);
	if (!cpumask_weight(policy->cpus)) {
		dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
		ret = -ENOENT;
		goto error;
	}

	policy->driver_data = data;

	ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
	if (ret) {
		dev_err(dev, "Domain-%d failed to read LUT\n", index);
		goto error;
	}

	ret = dev_pm_opp_get_opp_count(cpu_dev);
	if (ret <= 0) {
		dev_err(cpu_dev, "Failed to add OPPs\n");
		ret = -ENODEV;
		goto error;
	}

	dev_pm_opp_of_register_em(cpu_dev, policy->cpus);

	if (policy_has_boost_freq(policy)) {
		ret = cpufreq_enable_boost_support();
		if (ret)
			dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
	}

	return 0;
error:
	kfree(data);
unmap_base:
	iounmap(base);
release_region:
	release_mem_region(res->start, resource_size(res));
	return ret;
}

static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
{
	struct device *cpu_dev = get_cpu_device(policy->cpu);
	struct qcom_cpufreq_data *data = policy->driver_data;
	struct resource *res = data->res;
	void __iomem *base = data->base;

	dev_pm_opp_remove_all_dynamic(cpu_dev);
	dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
	kfree(policy->freq_table);
	kfree(data);
	iounmap(base);
	release_mem_region(res->start, resource_size(res));

	return 0;
}

static struct freq_attr *qcom_cpufreq_hw_attr[] = {
	&cpufreq_freq_attr_scaling_available_freqs,
	&cpufreq_freq_attr_scaling_boost_freqs,
	NULL
};

static struct cpufreq_driver cpufreq_qcom_hw_driver = {
	.flags		= CPUFREQ_NEED_INITIAL_FREQ_CHECK |
			  CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
			  CPUFREQ_IS_COOLING_DEV,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qcom_cpufreq_hw_target_index,
	.get		= qcom_cpufreq_hw_get,
	.init		= qcom_cpufreq_hw_cpu_init,
	.exit		= qcom_cpufreq_hw_cpu_exit,
	.fast_switch    = qcom_cpufreq_hw_fast_switch,
	.name		= "qcom-cpufreq-hw",
	.attr		= qcom_cpufreq_hw_attr,
};

static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
{
	struct device *cpu_dev;
	struct clk *clk;
	int ret;

	clk = clk_get(&pdev->dev, "xo");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	xo_rate = clk_get_rate(clk);
	clk_put(clk);

	clk = clk_get(&pdev->dev, "alternate");
	if (IS_ERR(clk))
		return PTR_ERR(clk);

	cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
	clk_put(clk);

	cpufreq_qcom_hw_driver.driver_data = pdev;

	/* Check for optional interconnect paths on CPU0 */
	cpu_dev = get_cpu_device(0);
	if (!cpu_dev)
		return -EPROBE_DEFER;

	ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
	if (ret)
		return ret;

	ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
	if (ret)
		dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
	else
		dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");

	return ret;
}

static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
{
	return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
}

static struct platform_driver qcom_cpufreq_hw_driver = {
	.probe = qcom_cpufreq_hw_driver_probe,
	.remove = qcom_cpufreq_hw_driver_remove,
	.driver = {
		.name = "qcom-cpufreq-hw",
		.of_match_table = qcom_cpufreq_hw_match,
	},
};

static int __init qcom_cpufreq_hw_init(void)
{
	return platform_driver_register(&qcom_cpufreq_hw_driver);
}
postcore_initcall(qcom_cpufreq_hw_init);

static void __exit qcom_cpufreq_hw_exit(void)
{
	platform_driver_unregister(&qcom_cpufreq_hw_driver);
}
module_exit(qcom_cpufreq_hw_exit);

MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2849dd8b TD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (c) 2018, The Linux Foundation. All rights reserved.
	4	*/
	5
	6	#include <linux/bitfield.h>
	7	#include <linux/cpufreq.h>
	8	#include <linux/init.h>
51c843cf	9	#include <linux/interconnect.h>
2849dd8b TD	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/of_address.h>
	13	#include <linux/of_platform.h>
55538fbc	14	#include <linux/pm_opp.h>
2849dd8b TD	15	#include <linux/slab.h>
	16
	17	#define LUT_MAX_ENTRIES 40U
	18	#define LUT_SRC GENMASK(31, 30)
	19	#define LUT_L_VAL GENMASK(7, 0)
	20	#define LUT_CORE_COUNT GENMASK(18, 16)
55538fbc	21	#define LUT_VOLT GENMASK(11, 0)
2849dd8b	22	#define CLK_HW_DIV 2
0eae1e37	23	#define LUT_TURBO_IND 1
2849dd8b	24
dcd1fd72 MS	25	struct qcom_cpufreq_soc_data {
	26	u32 reg_enable;
	27	u32 reg_freq_lut;
	28	u32 reg_volt_lut;
	29	u32 reg_perf_state;
	30	u8 lut_row_size;
	31	};
	32
	33	struct qcom_cpufreq_data {
	34	void __iomem *base;
67fc209b	35	struct resource *res;
dcd1fd72 MS	36	const struct qcom_cpufreq_soc_data *soc_data;
dcd1fd72 MS	37	};
2849dd8b TD	38
2849dd8b TD	39	static unsigned long cpu_hw_rate, xo_rate;
51c843cf SS	40	static bool icc_scaling_enabled;
	41
	42	static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
	43	unsigned long freq_khz)
	44	{
	45	unsigned long freq_hz = freq_khz * 1000;
	46	struct dev_pm_opp *opp;
	47	struct device *dev;
	48	int ret;
	49
	50	dev = get_cpu_device(policy->cpu);
	51	if (!dev)
	52	return -ENODEV;
	53
	54	opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
	55	if (IS_ERR(opp))
	56	return PTR_ERR(opp);
	57
8d25157f	58	ret = dev_pm_opp_set_opp(dev, opp);
51c843cf SS	59	dev_pm_opp_put(opp);
	60	return ret;
	61	}
	62
	63	static int qcom_cpufreq_update_opp(struct device *cpu_dev,
	64	unsigned long freq_khz,
	65	unsigned long volt)
	66	{
	67	unsigned long freq_hz = freq_khz * 1000;
	68	int ret;
	69
	70	/* Skip voltage update if the opp table is not available */
	71	if (!icc_scaling_enabled)
	72	return dev_pm_opp_add(cpu_dev, freq_hz, volt);
	73
	74	ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
	75	if (ret) {
	76	dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
	77	return ret;
	78	}
	79
	80	return dev_pm_opp_enable(cpu_dev, freq_hz);
	81	}
2849dd8b TD	82
	83	static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
	84	unsigned int index)
	85	{
dcd1fd72 MS	86	struct qcom_cpufreq_data *data = policy->driver_data;
dcd1fd72 MS	87	const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
ada54f35	88	unsigned long freq = policy->freq_table[index].frequency;
2849dd8b	89
dcd1fd72	90	writel_relaxed(index, data->base + soc_data->reg_perf_state);
2849dd8b	91
51c843cf SS	92	if (icc_scaling_enabled)
	93	qcom_cpufreq_set_bw(policy, freq);
	94
2849dd8b TD	95	return 0;
	96	}
	97
	98	static unsigned int qcom_cpufreq_hw_get(unsigned int cpu)
	99	{
dcd1fd72 MS	100	struct qcom_cpufreq_data *data;
dcd1fd72 MS	101	const struct qcom_cpufreq_soc_data *soc_data;
2849dd8b TD	102	struct cpufreq_policy *policy;
	103	unsigned int index;
	104
	105	policy = cpufreq_cpu_get_raw(cpu);
	106	if (!policy)
	107	return 0;
	108
dcd1fd72 MS	109	data = policy->driver_data;
dcd1fd72 MS	110	soc_data = data->soc_data;
2849dd8b	111
dcd1fd72	112	index = readl_relaxed(data->base + soc_data->reg_perf_state);
2849dd8b TD	113	index = min(index, LUT_MAX_ENTRIES - 1);
	114
	115	return policy->freq_table[index].frequency;
	116	}
	117
	118	static unsigned int qcom_cpufreq_hw_fast_switch(struct cpufreq_policy *policy,
	119	unsigned int target_freq)
	120	{
dcd1fd72 MS	121	struct qcom_cpufreq_data *data = policy->driver_data;
dcd1fd72 MS	122	const struct qcom_cpufreq_soc_data *soc_data = data->soc_data;
292072c3	123	unsigned int index;
2849dd8b TD	124
2849dd8b TD	125	index = policy->cached_resolved_idx;
dcd1fd72	126	writel_relaxed(index, data->base + soc_data->reg_perf_state);
2849dd8b	127
1a0419b0	128	return policy->freq_table[index].frequency;
2849dd8b TD	129	}
2849dd8b TD	130
55538fbc	131	static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
dcd1fd72	132	struct cpufreq_policy *policy)
2849dd8b	133	{
0eae1e37	134	u32 data, src, lval, i, core_count, prev_freq = 0, freq;
55538fbc	135	u32 volt;
2849dd8b	136	struct cpufreq_frequency_table *table;
51c843cf SS	137	struct dev_pm_opp *opp;
	138	unsigned long rate;
	139	int ret;
dcd1fd72 MS	140	struct qcom_cpufreq_data *drv_data = policy->driver_data;
dcd1fd72 MS	141	const struct qcom_cpufreq_soc_data *soc_data = drv_data->soc_data;
2849dd8b TD	142
	143	table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
	144	if (!table)
	145	return -ENOMEM;
	146
51c843cf SS	147	ret = dev_pm_opp_of_add_table(cpu_dev);
	148	if (!ret) {
	149	/* Disable all opps and cross-validate against LUT later */
	150	icc_scaling_enabled = true;
	151	for (rate = 0; ; rate++) {
	152	opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
	153	if (IS_ERR(opp))
	154	break;
	155
	156	dev_pm_opp_put(opp);
	157	dev_pm_opp_disable(cpu_dev, rate);
	158	}
	159	} else if (ret != -ENODEV) {
	160	dev_err(cpu_dev, "Invalid opp table in device tree\n");
	161	return ret;
	162	} else {
afdb219b	163	policy->fast_switch_possible = true;
51c843cf SS	164	icc_scaling_enabled = false;
	165	}
	166
2849dd8b	167	for (i = 0; i < LUT_MAX_ENTRIES; i++) {
dcd1fd72 MS	168	data = readl_relaxed(drv_data->base + soc_data->reg_freq_lut +
dcd1fd72 MS	169	i * soc_data->lut_row_size);
2849dd8b TD	170	src = FIELD_GET(LUT_SRC, data);
	171	lval = FIELD_GET(LUT_L_VAL, data);
	172	core_count = FIELD_GET(LUT_CORE_COUNT, data);
	173
dcd1fd72 MS	174	data = readl_relaxed(drv_data->base + soc_data->reg_volt_lut +
dcd1fd72 MS	175	i * soc_data->lut_row_size);
55538fbc TD	176	volt = FIELD_GET(LUT_VOLT, data) * 1000;
55538fbc TD	177
2849dd8b TD	178	if (src)
	179	freq = xo_rate * lval / 1000;
	180	else
	181	freq = cpu_hw_rate / 1000;
	182
0eae1e37	183	if (freq != prev_freq && core_count != LUT_TURBO_IND) {
bc9b9c5a MK	184	if (!qcom_cpufreq_update_opp(cpu_dev, freq, volt)) {
	185	table[i].frequency = freq;
	186	dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
2849dd8b	187	freq, core_count);
bc9b9c5a MK	188	} else {
	189	dev_warn(cpu_dev, "failed to update OPP for freq=%d\n", freq);
	190	table[i].frequency = CPUFREQ_ENTRY_INVALID;
	191	}
	192
0eae1e37	193	} else if (core_count == LUT_TURBO_IND) {
55538fbc	194	table[i].frequency = CPUFREQ_ENTRY_INVALID;
2849dd8b TD	195	}
	196
	197	/*
	198	* Two of the same frequencies with the same core counts means
	199	* end of table
	200	*/
0eae1e37	201	if (i > 0 && prev_freq == freq) {
2849dd8b TD	202	struct cpufreq_frequency_table *prev = &table[i - 1];
	203
	204	/*
	205	* Only treat the last frequency that might be a boost
	206	* as the boost frequency
	207	*/
0eae1e37	208	if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
bc9b9c5a MK	209	if (!qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt)) {
	210	prev->frequency = prev_freq;
	211	prev->flags = CPUFREQ_BOOST_FREQ;
	212	} else {
	213	dev_warn(cpu_dev, "failed to update OPP for freq=%d\n",
	214	freq);
	215	}
2849dd8b TD	216	}
	217
	218	break;
	219	}
	220
2849dd8b TD	221	prev_freq = freq;
	222	}
	223
	224	table[i].frequency = CPUFREQ_TABLE_END;
	225	policy->freq_table = table;
55538fbc	226	dev_pm_opp_set_sharing_cpus(cpu_dev, policy->cpus);
2849dd8b TD	227
	228	return 0;
	229	}
	230
	231	static void qcom_get_related_cpus(int index, struct cpumask *m)
	232	{
	233	struct device_node *cpu_np;
	234	struct of_phandle_args args;
	235	int cpu, ret;
	236
	237	for_each_possible_cpu(cpu) {
	238	cpu_np = of_cpu_device_node_get(cpu);
	239	if (!cpu_np)
	240	continue;
	241
	242	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
	243	"#freq-domain-cells", 0,
	244	&args);
	245	of_node_put(cpu_np);
	246	if (ret < 0)
	247	continue;
	248
	249	if (index == args.args[0])
	250	cpumask_set_cpu(cpu, m);
	251	}
	252	}
	253
dcd1fd72 MS	254	static const struct qcom_cpufreq_soc_data qcom_soc_data = {
	255	.reg_enable = 0x0,
	256	.reg_freq_lut = 0x110,
	257	.reg_volt_lut = 0x114,
	258	.reg_perf_state = 0x920,
	259	.lut_row_size = 32,
	260	};
	261
49b59f4c MS	262	static const struct qcom_cpufreq_soc_data epss_soc_data = {
	263	.reg_enable = 0x0,
	264	.reg_freq_lut = 0x100,
	265	.reg_volt_lut = 0x200,
	266	.reg_perf_state = 0x320,
	267	.lut_row_size = 4,
	268	};
	269
dcd1fd72 MS	270	static const struct of_device_id qcom_cpufreq_hw_match[] = {
dcd1fd72 MS	271	{ .compatible = "qcom,cpufreq-hw", .data = &qcom_soc_data },
49b59f4c	272	{ .compatible = "qcom,cpufreq-epss", .data = &epss_soc_data },
dcd1fd72 MS	273	{}
	274	};
	275	MODULE_DEVICE_TABLE(of, qcom_cpufreq_hw_match);
	276
2849dd8b TD	277	static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
2849dd8b TD	278	{
bd74e286 MS	279	struct platform_device *pdev = cpufreq_get_driver_data();
bd74e286 MS	280	struct device *dev = &pdev->dev;
2849dd8b TD	281	struct of_phandle_args args;
2849dd8b TD	282	struct device_node *cpu_np;
55538fbc	283	struct device *cpu_dev;
67fc209b	284	struct resource *res;
2849dd8b	285	void __iomem *base;
dcd1fd72	286	struct qcom_cpufreq_data *data;
2849dd8b TD	287	int ret, index;
2849dd8b TD	288
55538fbc TD	289	cpu_dev = get_cpu_device(policy->cpu);
	290	if (!cpu_dev) {
	291	pr_err("%s: failed to get cpu%d device\n", __func__,
	292	policy->cpu);
	293	return -ENODEV;
	294	}
	295
2849dd8b TD	296	cpu_np = of_cpu_device_node_get(policy->cpu);
	297	if (!cpu_np)
	298	return -EINVAL;
	299
	300	ret = of_parse_phandle_with_args(cpu_np, "qcom,freq-domain",
	301	"#freq-domain-cells", 0, &args);
	302	of_node_put(cpu_np);
	303	if (ret)
	304	return ret;
	305
	306	index = args.args[0];
	307
67fc209b SG	308	res = platform_get_resource(pdev, IORESOURCE_MEM, index);
	309	if (!res) {
	310	dev_err(dev, "failed to get mem resource %d\n", index);
	311	return -ENODEV;
	312	}
	313
	314	if (!request_mem_region(res->start, resource_size(res), res->name)) {
	315	dev_err(dev, "failed to request resource %pR\n", res);
	316	return -EBUSY;
	317	}
2849dd8b	318
67fc209b	319	base = ioremap(res->start, resource_size(res));
536eb97a	320	if (!base) {
67fc209b	321	dev_err(dev, "failed to map resource %pR\n", res);
536eb97a	322	ret = -ENOMEM;
67fc209b SG	323	goto release_region;
	324	}
	325
	326	data = kzalloc(sizeof(*data), GFP_KERNEL);
dcd1fd72 MS	327	if (!data) {
dcd1fd72 MS	328	ret = -ENOMEM;
67fc209b	329	goto unmap_base;
dcd1fd72 MS	330	}
	331
	332	data->soc_data = of_device_get_match_data(&pdev->dev);
	333	data->base = base;
67fc209b	334	data->res = res;
2849dd8b TD	335
2849dd8b TD	336	/* HW should be in enabled state to proceed */
dcd1fd72	337	if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) {
2849dd8b TD	338	dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index);
	339	ret = -ENODEV;
	340	goto error;
	341	}
	342
	343	qcom_get_related_cpus(index, policy->cpus);
	344	if (!cpumask_weight(policy->cpus)) {
	345	dev_err(dev, "Domain-%d failed to get related CPUs\n", index);
	346	ret = -ENOENT;
	347	goto error;
	348	}
	349
dcd1fd72	350	policy->driver_data = data;
2849dd8b	351
dcd1fd72	352	ret = qcom_cpufreq_hw_read_lut(cpu_dev, policy);
2849dd8b TD	353	if (ret) {
	354	dev_err(dev, "Domain-%d failed to read LUT\n", index);
	355	goto error;
	356	}
	357
55538fbc TD	358	ret = dev_pm_opp_get_opp_count(cpu_dev);
	359	if (ret <= 0) {
	360	dev_err(cpu_dev, "Failed to add OPPs\n");
	361	ret = -ENODEV;
	362	goto error;
	363	}
	364
0e0ffa85	365	dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
dab53505	366
26699172 SG	367	if (policy_has_boost_freq(policy)) {
	368	ret = cpufreq_enable_boost_support();
	369	if (ret)
	370	dev_warn(cpu_dev, "failed to enable boost: %d\n", ret);
	371	}
	372
2849dd8b TD	373	return 0;
2849dd8b TD	374	error:
67fc209b SG	375	kfree(data);
67fc209b SG	376	unmap_base:
02fc4095	377	iounmap(base);
67fc209b SG	378	release_region:
67fc209b SG	379	release_mem_region(res->start, resource_size(res));
2849dd8b TD	380	return ret;
	381	}
	382
	383	static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
	384	{
55538fbc	385	struct device *cpu_dev = get_cpu_device(policy->cpu);
dcd1fd72	386	struct qcom_cpufreq_data *data = policy->driver_data;
67fc209b SG	387	struct resource *res = data->res;
67fc209b SG	388	void __iomem *base = data->base;
2849dd8b	389
55538fbc	390	dev_pm_opp_remove_all_dynamic(cpu_dev);
51c843cf	391	dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
2849dd8b	392	kfree(policy->freq_table);
67fc209b SG	393	kfree(data);
	394	iounmap(base);
	395	release_mem_region(res->start, resource_size(res));
2849dd8b TD	396
	397	return 0;
	398	}
	399
	400	static struct freq_attr *qcom_cpufreq_hw_attr[] = {
	401	&cpufreq_freq_attr_scaling_available_freqs,
	402	&cpufreq_freq_attr_scaling_boost_freqs,
	403	NULL
	404	};
	405
	406	static struct cpufreq_driver cpufreq_qcom_hw_driver = {
5ae4a4b4	407	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK \|
4c5ff1c8 AK	408	CPUFREQ_HAVE_GOVERNOR_PER_POLICY \|
4c5ff1c8 AK	409	CPUFREQ_IS_COOLING_DEV,
2849dd8b TD	410	.verify = cpufreq_generic_frequency_table_verify,
	411	.target_index = qcom_cpufreq_hw_target_index,
	412	.get = qcom_cpufreq_hw_get,
	413	.init = qcom_cpufreq_hw_cpu_init,
	414	.exit = qcom_cpufreq_hw_cpu_exit,
	415	.fast_switch = qcom_cpufreq_hw_fast_switch,
	416	.name = "qcom-cpufreq-hw",
	417	.attr = qcom_cpufreq_hw_attr,
	418	};
	419
	420	static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
	421	{
51c843cf	422	struct device *cpu_dev;
2849dd8b TD	423	struct clk *clk;
	424	int ret;
	425
	426	clk = clk_get(&pdev->dev, "xo");
	427	if (IS_ERR(clk))
	428	return PTR_ERR(clk);
	429
	430	xo_rate = clk_get_rate(clk);
	431	clk_put(clk);
	432
	433	clk = clk_get(&pdev->dev, "alternate");
	434	if (IS_ERR(clk))
	435	return PTR_ERR(clk);
	436
	437	cpu_hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
	438	clk_put(clk);
	439
bd74e286	440	cpufreq_qcom_hw_driver.driver_data = pdev;
2849dd8b	441
51c843cf SS	442	/* Check for optional interconnect paths on CPU0 */
	443	cpu_dev = get_cpu_device(0);
	444	if (!cpu_dev)
	445	return -EPROBE_DEFER;
	446
	447	ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
	448	if (ret)
	449	return ret;
	450
2849dd8b TD	451	ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
	452	if (ret)
	453	dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
	454	else
	455	dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n");
	456
	457	return ret;
	458	}
	459
	460	static int qcom_cpufreq_hw_driver_remove(struct platform_device *pdev)
	461	{
	462	return cpufreq_unregister_driver(&cpufreq_qcom_hw_driver);
	463	}
	464
2849dd8b TD	465	static struct platform_driver qcom_cpufreq_hw_driver = {
	466	.probe = qcom_cpufreq_hw_driver_probe,
	467	.remove = qcom_cpufreq_hw_driver_remove,
	468	.driver = {
	469	.name = "qcom-cpufreq-hw",
	470	.of_match_table = qcom_cpufreq_hw_match,
	471	},
	472	};
	473
	474	static int __init qcom_cpufreq_hw_init(void)
	475	{
	476	return platform_driver_register(&qcom_cpufreq_hw_driver);
	477	}
11ff4bdd	478	postcore_initcall(qcom_cpufreq_hw_init);
2849dd8b TD	479
	480	static void __exit qcom_cpufreq_hw_exit(void)
	481	{
	482	platform_driver_unregister(&qcom_cpufreq_hw_driver);
	483	}
	484	module_exit(qcom_cpufreq_hw_exit);
	485
	486	MODULE_DESCRIPTION("QCOM CPUFREQ HW Driver");
	487	MODULE_LICENSE("GPL v2");