[mirror_ubuntu-zesty-kernel.git] / drivers / cpufreq / qoriq-cpufreq.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/cpu_cooling.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>

#if !defined(CONFIG_ARM)
#include <asm/smp.h>	/* for get_hard_smp_processor_id() in UP configs */
#endif

/**
 * struct cpu_data
 * @pclk: the parent clock of cpu
 * @table: frequency table
 */
struct cpu_data {
	struct clk **pclk;
	struct cpufreq_frequency_table *table;
	struct thermal_cooling_device *cdev;
};

/**
 * struct soc_data - SoC specific data
 * @freq_mask: mask the disallowed frequencies
 * @flag: unique flags
 */
struct soc_data {
	u32 freq_mask[4];
	u32 flag;
};

#define FREQ_MASK	1
/* see hardware specification for the allowed frqeuencies */
static const struct soc_data sdata[] = {
	{ /* used by p2041 and p3041 */
		.freq_mask = {0x8, 0x8, 0x2, 0x2},
		.flag = FREQ_MASK,
	},
	{ /* used by p5020 */
		.freq_mask = {0x8, 0x2},
		.flag = FREQ_MASK,
	},
	{ /* used by p4080, p5040 */
		.freq_mask = {0},
		.flag = 0,
	},
};

/*
 * the minimum allowed core frequency, in Hz
 * for chassis v1.0, >= platform frequency
 * for chassis v2.0, >= platform frequency / 2
 */
static u32 min_cpufreq;
static const u32 *fmask;

#if defined(CONFIG_ARM)
static int get_cpu_physical_id(int cpu)
{
	return topology_core_id(cpu);
}
#else
static int get_cpu_physical_id(int cpu)
{
	return get_hard_smp_processor_id(cpu);
}
#endif

static u32 get_bus_freq(void)
{
	struct device_node *soc;
	u32 sysfreq;

	soc = of_find_node_by_type(NULL, "soc");
	if (!soc)
		return 0;

	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
		sysfreq = 0;

	of_node_put(soc);

	return sysfreq;
}

static struct device_node *cpu_to_clk_node(int cpu)
{
	struct device_node *np, *clk_np;

	if (!cpu_present(cpu))
		return NULL;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return NULL;

	clk_np = of_parse_phandle(np, "clocks", 0);
	if (!clk_np)
		return NULL;

	of_node_put(np);

	return clk_np;
}

/* traverse cpu nodes to get cpu mask of sharing clock wire */
static void set_affected_cpus(struct cpufreq_policy *policy)
{
	struct device_node *np, *clk_np;
	struct cpumask *dstp = policy->cpus;
	int i;

	np = cpu_to_clk_node(policy->cpu);
	if (!np)
		return;

	for_each_present_cpu(i) {
		clk_np = cpu_to_clk_node(i);
		if (!clk_np)
			continue;

		if (clk_np == np)
			cpumask_set_cpu(i, dstp);

		of_node_put(clk_np);
	}
	of_node_put(np);
}

/* reduce the duplicated frequencies in frequency table */
static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j;

	for (i = 1; i < count; i++) {
		for (j = 0; j < i; j++) {
			if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
					freq_table[j].frequency !=
					freq_table[i].frequency)
				continue;

			freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
			break;
		}
	}
}

/* sort the frequencies in frequency table in descenting order */
static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j, ind;
	unsigned int freq, max_freq;
	struct cpufreq_frequency_table table;

	for (i = 0; i < count - 1; i++) {
		max_freq = freq_table[i].frequency;
		ind = i;
		for (j = i + 1; j < count; j++) {
			freq = freq_table[j].frequency;
			if (freq == CPUFREQ_ENTRY_INVALID ||
					freq <= max_freq)
				continue;
			ind = j;
			max_freq = freq;
		}

		if (ind != i) {
			/* exchange the frequencies */
			table.driver_data = freq_table[i].driver_data;
			table.frequency = freq_table[i].frequency;
			freq_table[i].driver_data = freq_table[ind].driver_data;
			freq_table[i].frequency = freq_table[ind].frequency;
			freq_table[ind].driver_data = table.driver_data;
			freq_table[ind].frequency = table.frequency;
		}
	}
}

static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	struct device_node *np, *pnode;
	int i, count, ret;
	u32 freq, mask;
	struct clk *clk;
	struct cpufreq_frequency_table *table;
	struct cpu_data *data;
	unsigned int cpu = policy->cpu;
	u64 u64temp;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return -ENODEV;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		goto err_np;

	policy->clk = of_clk_get(np, 0);
	if (IS_ERR(policy->clk)) {
		pr_err("%s: no clock information\n", __func__);
		goto err_nomem2;
	}

	pnode = of_parse_phandle(np, "clocks", 0);
	if (!pnode) {
		pr_err("%s: could not get clock information\n", __func__);
		goto err_nomem2;
	}

	count = of_property_count_strings(pnode, "clock-names");
	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	if (!data->pclk) {
		pr_err("%s: no memory\n", __func__);
		goto err_node;
	}

	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	if (!table) {
		pr_err("%s: no memory\n", __func__);
		goto err_pclk;
	}

	if (fmask)
		mask = fmask[get_cpu_physical_id(cpu)];
	else
		mask = 0x0;

	for (i = 0; i < count; i++) {
		clk = of_clk_get(pnode, i);
		data->pclk[i] = clk;
		freq = clk_get_rate(clk);
		/*
		 * the clock is valid if its frequency is not masked
		 * and large than minimum allowed frequency.
		 */
		if (freq < min_cpufreq || (mask & (1 << i)))
			table[i].frequency = CPUFREQ_ENTRY_INVALID;
		else
			table[i].frequency = freq / 1000;
		table[i].driver_data = i;
	}
	freq_table_redup(table, count);
	freq_table_sort(table, count);
	table[i].frequency = CPUFREQ_TABLE_END;

	/* set the min and max frequency properly */
	ret = cpufreq_table_validate_and_show(policy, table);
	if (ret) {
		pr_err("invalid frequency table: %d\n", ret);
		goto err_nomem1;
	}

	data->table = table;

	/* update ->cpus if we have cluster, no harm if not */
	set_affected_cpus(policy);
	policy->driver_data = data;

	/* Minimum transition latency is 12 platform clocks */
	u64temp = 12ULL * NSEC_PER_SEC;
	do_div(u64temp, get_bus_freq());
	policy->cpuinfo.transition_latency = u64temp + 1;

	of_node_put(np);
	of_node_put(pnode);

	return 0;

err_nomem1:
	kfree(table);
err_pclk:
	kfree(data->pclk);
err_node:
	of_node_put(pnode);
err_nomem2:
	policy->driver_data = NULL;
	kfree(data);
err_np:
	of_node_put(np);

	return -ENODEV;
}

static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	struct cpu_data *data = policy->driver_data;

	cpufreq_cooling_unregister(data->cdev);
	kfree(data->pclk);
	kfree(data->table);
	kfree(data);
	policy->driver_data = NULL;

	return 0;
}

static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
		unsigned int index)
{
	struct clk *parent;
	struct cpu_data *data = policy->driver_data;

	parent = data->pclk[data->table[index].driver_data];
	return clk_set_parent(policy->clk, parent);
}


static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
{
	struct cpu_data *cpud = policy->driver_data;
	struct device_node *np = of_get_cpu_node(policy->cpu, NULL);

	if (of_find_property(np, "#cooling-cells", NULL)) {
		cpud->cdev = of_cpufreq_cooling_register(np,
							 policy->related_cpus);

		if (IS_ERR(cpud->cdev) && PTR_ERR(cpud->cdev) != -ENOSYS) {
			pr_err("cpu%d is not running as cooling device: %ld\n",
					policy->cpu, PTR_ERR(cpud->cdev));

			cpud->cdev = NULL;
		}
	}

	of_node_put(np);
}

static struct cpufreq_driver qoriq_cpufreq_driver = {
	.name		= "qoriq_cpufreq",
	.flags		= CPUFREQ_CONST_LOOPS,
	.init		= qoriq_cpufreq_cpu_init,
	.exit		= qoriq_cpufreq_cpu_exit,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qoriq_cpufreq_target,
	.get		= cpufreq_generic_get,
	.ready		= qoriq_cpufreq_ready,
	.attr		= cpufreq_generic_attr,
};

static const struct of_device_id node_matches[] __initconst = {
	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	{}
};

static int __init qoriq_cpufreq_init(void)
{
	int ret;
	struct device_node  *np;
	const struct of_device_id *match;
	const struct soc_data *data;

	np = of_find_matching_node(NULL, node_matches);
	if (!np)
		return -ENODEV;

	match = of_match_node(node_matches, np);
	data = match->data;
	if (data) {
		if (data->flag)
			fmask = data->freq_mask;
		min_cpufreq = get_bus_freq();
	} else {
		min_cpufreq = get_bus_freq() / 2;
	}

	of_node_put(np);

	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
	if (!ret)
		pr_info("Freescale QorIQ CPU frequency scaling driver\n");

	return ret;
}
module_init(qoriq_cpufreq_init);

static void __exit qoriq_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
}
module_exit(qoriq_cpufreq_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
Commit	Line	Data
defa4c73 TY	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
a4f20742	4	* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
defa4c73 TY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/clk.h>
	14	#include <linux/cpufreq.h>
8ae1702a	15	#include <linux/cpu_cooling.h>
defa4c73	16	#include <linux/errno.h>
defa4c73 TY	17	#include <linux/init.h>
	18	#include <linux/kernel.h>
	19	#include <linux/module.h>
	20	#include <linux/mutex.h>
	21	#include <linux/of.h>
	22	#include <linux/slab.h>
	23	#include <linux/smp.h>
	24
4492d1a2	25	#if !defined(CONFIG_ARM)
5877b4f4	26	#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
4492d1a2	27	#endif
5877b4f4	28
defa4c73	29	/**
a4f20742	30	* struct cpu_data
8a95c144	31	* @pclk: the parent clock of cpu
defa4c73 TY	32	* @table: frequency table
	33	*/
	34	struct cpu_data {
8a95c144	35	struct clk **pclk;
defa4c73	36	struct cpufreq_frequency_table *table;
8ae1702a	37	struct thermal_cooling_device *cdev;
defa4c73 TY	38	};
	39
	40	/**
	41	* struct soc_data - SoC specific data
	42	* @freq_mask: mask the disallowed frequencies
	43	* @flag: unique flags
	44	*/
	45	struct soc_data {
	46	u32 freq_mask[4];
	47	u32 flag;
	48	};
	49
	50	#define FREQ_MASK 1
	51	/* see hardware specification for the allowed frqeuencies */
	52	static const struct soc_data sdata[] = {
	53	{ /* used by p2041 and p3041 */
	54	.freq_mask = {0x8, 0x8, 0x2, 0x2},
	55	.flag = FREQ_MASK,
	56	},
	57	{ /* used by p5020 */
	58	.freq_mask = {0x8, 0x2},
	59	.flag = FREQ_MASK,
	60	},
	61	{ /* used by p4080, p5040 */
	62	.freq_mask = {0},
	63	.flag = 0,
	64	},
	65	};
	66
	67	/*
	68	* the minimum allowed core frequency, in Hz
	69	* for chassis v1.0, >= platform frequency
	70	* for chassis v2.0, >= platform frequency / 2
	71	*/
	72	static u32 min_cpufreq;
	73	static const u32 *fmask;
	74
a4f20742 TY	75	#if defined(CONFIG_ARM)
	76	static int get_cpu_physical_id(int cpu)
	77	{
	78	return topology_core_id(cpu);
	79	}
	80	#else
	81	static int get_cpu_physical_id(int cpu)
	82	{
	83	return get_hard_smp_processor_id(cpu);
	84	}
	85	#endif
	86
	87	static u32 get_bus_freq(void)
	88	{
	89	struct device_node *soc;
	90	u32 sysfreq;
	91
	92	soc = of_find_node_by_type(NULL, "soc");
	93	if (!soc)
	94	return 0;
	95
	96	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
	97	sysfreq = 0;
	98
	99	of_node_put(soc);
defa4c73	100
a4f20742 TY	101	return sysfreq;
a4f20742 TY	102	}
defa4c73	103
a4f20742	104	static struct device_node *cpu_to_clk_node(int cpu)
defa4c73	105	{
a4f20742 TY	106	struct device_node np, clk_np;
	107
	108	if (!cpu_present(cpu))
	109	return NULL;
	110
	111	np = of_get_cpu_node(cpu, NULL);
	112	if (!np)
	113	return NULL;
	114
	115	clk_np = of_parse_phandle(np, "clocks", 0);
	116	if (!clk_np)
	117	return NULL;
	118
	119	of_node_put(np);
	120
	121	return clk_np;
	122	}
	123
	124	/* traverse cpu nodes to get cpu mask of sharing clock wire */
	125	static void set_affected_cpus(struct cpufreq_policy *policy)
	126	{
	127	struct device_node np, clk_np;
	128	struct cpumask *dstp = policy->cpus;
	129	int i;
	130
	131	np = cpu_to_clk_node(policy->cpu);
	132	if (!np)
	133	return;
	134
	135	for_each_present_cpu(i) {
	136	clk_np = cpu_to_clk_node(i);
	137	if (!clk_np)
	138	continue;
	139
	140	if (clk_np == np)
	141	cpumask_set_cpu(i, dstp);
	142
	143	of_node_put(clk_np);
	144	}
	145	of_node_put(np);
defa4c73	146	}
defa4c73	147
defa4c73 TY	148	/* reduce the duplicated frequencies in frequency table */
	149	static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
	150	int count)
	151	{
	152	int i, j;
	153
	154	for (i = 1; i < count; i++) {
	155	for (j = 0; j < i; j++) {
	156	if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID \|\|
	157	freq_table[j].frequency !=
	158	freq_table[i].frequency)
	159	continue;
	160
	161	freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	162	break;
	163	}
	164	}
	165	}
	166
	167	/* sort the frequencies in frequency table in descenting order */
	168	static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
	169	int count)
	170	{
	171	int i, j, ind;
	172	unsigned int freq, max_freq;
	173	struct cpufreq_frequency_table table;
a4f20742	174
defa4c73 TY	175	for (i = 0; i < count - 1; i++) {
	176	max_freq = freq_table[i].frequency;
	177	ind = i;
	178	for (j = i + 1; j < count; j++) {
	179	freq = freq_table[j].frequency;
	180	if (freq == CPUFREQ_ENTRY_INVALID \|\|
	181	freq <= max_freq)
	182	continue;
	183	ind = j;
	184	max_freq = freq;
	185	}
	186
	187	if (ind != i) {
	188	/* exchange the frequencies */
	189	table.driver_data = freq_table[i].driver_data;
	190	table.frequency = freq_table[i].frequency;
	191	freq_table[i].driver_data = freq_table[ind].driver_data;
	192	freq_table[i].frequency = freq_table[ind].frequency;
	193	freq_table[ind].driver_data = table.driver_data;
	194	freq_table[ind].frequency = table.frequency;
	195	}
	196	}
	197	}
	198
a4f20742	199	static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
defa4c73	200	{
8a95c144	201	struct device_node np, pnode;
defa4c73 TY	202	int i, count, ret;
	203	u32 freq, mask;
	204	struct clk *clk;
	205	struct cpufreq_frequency_table *table;
	206	struct cpu_data *data;
	207	unsigned int cpu = policy->cpu;
906fe033	208	u64 u64temp;
defa4c73 TY	209
	210	np = of_get_cpu_node(cpu, NULL);
	211	if (!np)
	212	return -ENODEV;
	213
	214	data = kzalloc(sizeof(*data), GFP_KERNEL);
a4f20742	215	if (!data)
defa4c73	216	goto err_np;
defa4c73	217
652ed95d VK	218	policy->clk = of_clk_get(np, 0);
652ed95d VK	219	if (IS_ERR(policy->clk)) {
defa4c73 TY	220	pr_err("%s: no clock information\n", __func__);
	221	goto err_nomem2;
	222	}
	223
8a95c144 TY	224	pnode = of_parse_phandle(np, "clocks", 0);
8a95c144 TY	225	if (!pnode) {
defa4c73 TY	226	pr_err("%s: could not get clock information\n", __func__);
	227	goto err_nomem2;
	228	}
	229
8a95c144 TY	230	count = of_property_count_strings(pnode, "clock-names");
	231	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	232	if (!data->pclk) {
	233	pr_err("%s: no memory\n", __func__);
	234	goto err_node;
	235	}
	236
defa4c73 TY	237	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	238	if (!table) {
	239	pr_err("%s: no memory\n", __func__);
8a95c144	240	goto err_pclk;
defa4c73 TY	241	}
	242
	243	if (fmask)
a4f20742	244	mask = fmask[get_cpu_physical_id(cpu)];
defa4c73 TY	245	else
	246	mask = 0x0;
	247
	248	for (i = 0; i < count; i++) {
8a95c144 TY	249	clk = of_clk_get(pnode, i);
8a95c144 TY	250	data->pclk[i] = clk;
defa4c73 TY	251	freq = clk_get_rate(clk);
	252	/*
	253	* the clock is valid if its frequency is not masked
	254	* and large than minimum allowed frequency.
	255	*/
	256	if (freq < min_cpufreq \|\| (mask & (1 << i)))
	257	table[i].frequency = CPUFREQ_ENTRY_INVALID;
	258	else
	259	table[i].frequency = freq / 1000;
	260	table[i].driver_data = i;
	261	}
	262	freq_table_redup(table, count);
	263	freq_table_sort(table, count);
	264	table[i].frequency = CPUFREQ_TABLE_END;
	265
	266	/* set the min and max frequency properly */
6b4147db	267	ret = cpufreq_table_validate_and_show(policy, table);
defa4c73 TY	268	if (ret) {
	269	pr_err("invalid frequency table: %d\n", ret);
	270	goto err_nomem1;
	271	}
	272
	273	data->table = table;
defa4c73 TY	274
defa4c73 TY	275	/* update ->cpus if we have cluster, no harm if not */
a4f20742 TY	276	set_affected_cpus(policy);
a4f20742 TY	277	policy->driver_data = data;
defa4c73	278
906fe033 ES	279	/* Minimum transition latency is 12 platform clocks */
906fe033 ES	280	u64temp = 12ULL * NSEC_PER_SEC;
a4f20742	281	do_div(u64temp, get_bus_freq());
906fe033	282	policy->cpuinfo.transition_latency = u64temp + 1;
6712d293	283
defa4c73	284	of_node_put(np);
8a95c144	285	of_node_put(pnode);
defa4c73 TY	286
	287	return 0;
	288
	289	err_nomem1:
	290	kfree(table);
8a95c144 TY	291	err_pclk:
8a95c144 TY	292	kfree(data->pclk);
defa4c73	293	err_node:
8a95c144	294	of_node_put(pnode);
defa4c73	295	err_nomem2:
a4f20742	296	policy->driver_data = NULL;
defa4c73 TY	297	kfree(data);
	298	err_np:
	299	of_node_put(np);
	300
	301	return -ENODEV;
	302	}
	303
495c716f	304	static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
defa4c73	305	{
a4f20742	306	struct cpu_data *data = policy->driver_data;
defa4c73	307
394cb831	308	cpufreq_cooling_unregister(data->cdev);
8a95c144	309	kfree(data->pclk);
defa4c73 TY	310	kfree(data->table);
defa4c73 TY	311	kfree(data);
a4f20742	312	policy->driver_data = NULL;
defa4c73 TY	313
	314	return 0;
	315	}
	316
a4f20742	317	static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
9c0ebcf7	318	unsigned int index)
defa4c73	319	{
defa4c73	320	struct clk *parent;
a4f20742	321	struct cpu_data *data = policy->driver_data;
defa4c73	322
8a95c144	323	parent = data->pclk[data->table[index].driver_data];
652ed95d	324	return clk_set_parent(policy->clk, parent);
defa4c73 TY	325	}
defa4c73 TY	326
8ae1702a HJ	327
	328	static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
	329	{
	330	struct cpu_data *cpud = policy->driver_data;
	331	struct device_node *np = of_get_cpu_node(policy->cpu, NULL);
	332
	333	if (of_find_property(np, "#cooling-cells", NULL)) {
	334	cpud->cdev = of_cpufreq_cooling_register(np,
	335	policy->related_cpus);
	336
27b8fe8d JH	337	if (IS_ERR(cpud->cdev) && PTR_ERR(cpud->cdev) != -ENOSYS) {
27b8fe8d JH	338	pr_err("cpu%d is not running as cooling device: %ld\n",
8ae1702a HJ	339	policy->cpu, PTR_ERR(cpud->cdev));
	340
	341	cpud->cdev = NULL;
	342	}
	343	}
	344
	345	of_node_put(np);
	346	}
	347
a4f20742 TY	348	static struct cpufreq_driver qoriq_cpufreq_driver = {
a4f20742 TY	349	.name = "qoriq_cpufreq",
defa4c73	350	.flags = CPUFREQ_CONST_LOOPS,
a4f20742	351	.init = qoriq_cpufreq_cpu_init,
495c716f	352	.exit = qoriq_cpufreq_cpu_exit,
dc2398d7	353	.verify = cpufreq_generic_frequency_table_verify,
a4f20742	354	.target_index = qoriq_cpufreq_target,
652ed95d	355	.get = cpufreq_generic_get,
8ae1702a	356	.ready = qoriq_cpufreq_ready,
dc2398d7	357	.attr = cpufreq_generic_attr,
defa4c73 TY	358	};
defa4c73 TY	359
a4f20742	360	static const struct of_device_id node_matches[] __initconst = {
defa4c73 TY	361	{ .compatible = "fsl,p2041-clockgen", .data = &sdata[0], },
	362	{ .compatible = "fsl,p3041-clockgen", .data = &sdata[0], },
	363	{ .compatible = "fsl,p5020-clockgen", .data = &sdata[1], },
	364	{ .compatible = "fsl,p4080-clockgen", .data = &sdata[2], },
	365	{ .compatible = "fsl,p5040-clockgen", .data = &sdata[2], },
	366	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	367	{}
	368	};
	369
a4f20742	370	static int __init qoriq_cpufreq_init(void)
defa4c73 TY	371	{
	372	int ret;
	373	struct device_node *np;
	374	const struct of_device_id *match;
	375	const struct soc_data *data;
defa4c73 TY	376
	377	np = of_find_matching_node(NULL, node_matches);
	378	if (!np)
	379	return -ENODEV;
	380
defa4c73 TY	381	match = of_match_node(node_matches, np);
	382	data = match->data;
	383	if (data) {
	384	if (data->flag)
	385	fmask = data->freq_mask;
a4f20742	386	min_cpufreq = get_bus_freq();
defa4c73	387	} else {
a4f20742	388	min_cpufreq = get_bus_freq() / 2;
defa4c73 TY	389	}
	390
	391	of_node_put(np);
	392
a4f20742	393	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
defa4c73	394	if (!ret)
a4f20742	395	pr_info("Freescale QorIQ CPU frequency scaling driver\n");
defa4c73 TY	396
defa4c73 TY	397	return ret;
defa4c73	398	}
a4f20742	399	module_init(qoriq_cpufreq_init);
defa4c73	400
a4f20742	401	static void __exit qoriq_cpufreq_exit(void)
defa4c73	402	{
a4f20742	403	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
defa4c73	404	}
a4f20742	405	module_exit(qoriq_cpufreq_exit);
defa4c73 TY	406
	407	MODULE_LICENSE("GPL");
	408	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
a4f20742	409	MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");