[mirror_ubuntu-artful-kernel.git] / drivers / cpufreq / qoriq-cpufreq.c

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define pr_fmt(fmt)	KBUILD_MODNAME ": " fmt

#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/cpufreq.h>
#include <linux/cpu_cooling.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/slab.h>
#include <linux/smp.h>

#if !defined(CONFIG_ARM)
#include <asm/smp.h>	/* for get_hard_smp_processor_id() in UP configs */
#endif

/**
 * struct cpu_data
 * @pclk: the parent clock of cpu
 * @table: frequency table
 */
struct cpu_data {
	struct clk **pclk;
	struct cpufreq_frequency_table *table;
	struct thermal_cooling_device *cdev;
};

/*
 * Don't use cpufreq on this SoC -- used when the SoC would have otherwise
 * matched a more generic compatible.
 */
#define SOC_BLACKLIST		1

/**
 * struct soc_data - SoC specific data
 * @flags: SOC_xxx
 */
struct soc_data {
	u32 flags;
};

static u32 get_bus_freq(void)
{
	struct device_node *soc;
	u32 sysfreq;

	soc = of_find_node_by_type(NULL, "soc");
	if (!soc)
		return 0;

	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
		sysfreq = 0;

	of_node_put(soc);

	return sysfreq;
}

static struct clk *cpu_to_clk(int cpu)
{
	struct device_node *np;
	struct clk *clk;

	if (!cpu_present(cpu))
		return NULL;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return NULL;

	clk = of_clk_get(np, 0);
	of_node_put(np);
	return clk;
}

/* traverse cpu nodes to get cpu mask of sharing clock wire */
static void set_affected_cpus(struct cpufreq_policy *policy)
{
	struct cpumask *dstp = policy->cpus;
	struct clk *clk;
	int i;

	for_each_present_cpu(i) {
		clk = cpu_to_clk(i);
		if (IS_ERR(clk)) {
			pr_err("%s: no clock for cpu %d\n", __func__, i);
			continue;
		}

		if (clk_is_match(policy->clk, clk))
			cpumask_set_cpu(i, dstp);
	}
}

/* reduce the duplicated frequencies in frequency table */
static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j;

	for (i = 1; i < count; i++) {
		for (j = 0; j < i; j++) {
			if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID ||
					freq_table[j].frequency !=
					freq_table[i].frequency)
				continue;

			freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
			break;
		}
	}
}

/* sort the frequencies in frequency table in descenting order */
static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
		int count)
{
	int i, j, ind;
	unsigned int freq, max_freq;
	struct cpufreq_frequency_table table;

	for (i = 0; i < count - 1; i++) {
		max_freq = freq_table[i].frequency;
		ind = i;
		for (j = i + 1; j < count; j++) {
			freq = freq_table[j].frequency;
			if (freq == CPUFREQ_ENTRY_INVALID ||
					freq <= max_freq)
				continue;
			ind = j;
			max_freq = freq;
		}

		if (ind != i) {
			/* exchange the frequencies */
			table.driver_data = freq_table[i].driver_data;
			table.frequency = freq_table[i].frequency;
			freq_table[i].driver_data = freq_table[ind].driver_data;
			freq_table[i].frequency = freq_table[ind].frequency;
			freq_table[ind].driver_data = table.driver_data;
			freq_table[ind].frequency = table.frequency;
		}
	}
}

static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
{
	struct device_node *np;
	int i, count, ret;
	u32 freq;
	struct clk *clk;
	const struct clk_hw *hwclk;
	struct cpufreq_frequency_table *table;
	struct cpu_data *data;
	unsigned int cpu = policy->cpu;
	u64 u64temp;

	np = of_get_cpu_node(cpu, NULL);
	if (!np)
		return -ENODEV;

	data = kzalloc(sizeof(*data), GFP_KERNEL);
	if (!data)
		goto err_np;

	policy->clk = of_clk_get(np, 0);
	if (IS_ERR(policy->clk)) {
		pr_err("%s: no clock information\n", __func__);
		goto err_nomem2;
	}

	hwclk = __clk_get_hw(policy->clk);
	count = clk_hw_get_num_parents(hwclk);

	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	if (!data->pclk) {
		pr_err("%s: no memory\n", __func__);
		goto err_nomem2;
	}

	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	if (!table) {
		pr_err("%s: no memory\n", __func__);
		goto err_pclk;
	}

	for (i = 0; i < count; i++) {
		clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
		data->pclk[i] = clk;
		freq = clk_get_rate(clk);
		table[i].frequency = freq / 1000;
		table[i].driver_data = i;
	}
	freq_table_redup(table, count);
	freq_table_sort(table, count);
	table[i].frequency = CPUFREQ_TABLE_END;

	/* set the min and max frequency properly */
	ret = cpufreq_table_validate_and_show(policy, table);
	if (ret) {
		pr_err("invalid frequency table: %d\n", ret);
		goto err_nomem1;
	}

	data->table = table;

	/* update ->cpus if we have cluster, no harm if not */
	set_affected_cpus(policy);
	policy->driver_data = data;

	/* Minimum transition latency is 12 platform clocks */
	u64temp = 12ULL * NSEC_PER_SEC;
	do_div(u64temp, get_bus_freq());
	policy->cpuinfo.transition_latency = u64temp + 1;

	of_node_put(np);

	return 0;

err_nomem1:
	kfree(table);
err_pclk:
	kfree(data->pclk);
err_nomem2:
	kfree(data);
err_np:
	of_node_put(np);

	return -ENODEV;
}

static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
	struct cpu_data *data = policy->driver_data;

	cpufreq_cooling_unregister(data->cdev);
	kfree(data->pclk);
	kfree(data->table);
	kfree(data);
	policy->driver_data = NULL;

	return 0;
}

static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
		unsigned int index)
{
	struct clk *parent;
	struct cpu_data *data = policy->driver_data;

	parent = data->pclk[data->table[index].driver_data];
	return clk_set_parent(policy->clk, parent);
}


static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
{
	struct cpu_data *cpud = policy->driver_data;
	struct device_node *np = of_get_cpu_node(policy->cpu, NULL);

	if (of_find_property(np, "#cooling-cells", NULL)) {
		cpud->cdev = of_cpufreq_cooling_register(np,
							 policy->related_cpus);

		if (IS_ERR(cpud->cdev) && PTR_ERR(cpud->cdev) != -ENOSYS) {
			pr_err("cpu%d is not running as cooling device: %ld\n",
					policy->cpu, PTR_ERR(cpud->cdev));

			cpud->cdev = NULL;
		}
	}

	of_node_put(np);
}

static struct cpufreq_driver qoriq_cpufreq_driver = {
	.name		= "qoriq_cpufreq",
	.flags		= CPUFREQ_CONST_LOOPS,
	.init		= qoriq_cpufreq_cpu_init,
	.exit		= qoriq_cpufreq_cpu_exit,
	.verify		= cpufreq_generic_frequency_table_verify,
	.target_index	= qoriq_cpufreq_target,
	.get		= cpufreq_generic_get,
	.ready		= qoriq_cpufreq_ready,
	.attr		= cpufreq_generic_attr,
};

static const struct soc_data blacklist = {
	.flags = SOC_BLACKLIST,
};

static const struct of_device_id node_matches[] __initconst = {
	/* e6500 cannot use cpufreq due to erratum A-008083 */
	{ .compatible = "fsl,b4420-clockgen", &blacklist },
	{ .compatible = "fsl,b4860-clockgen", &blacklist },
	{ .compatible = "fsl,t2080-clockgen", &blacklist },
	{ .compatible = "fsl,t4240-clockgen", &blacklist },

	{ .compatible = "fsl,ls1012a-clockgen", },
	{ .compatible = "fsl,ls1021a-clockgen", },
	{ .compatible = "fsl,ls1043a-clockgen", },
	{ .compatible = "fsl,ls1046a-clockgen", },
	{ .compatible = "fsl,ls1088a-clockgen", },
	{ .compatible = "fsl,ls2080a-clockgen", },
	{ .compatible = "fsl,p4080-clockgen", },
	{ .compatible = "fsl,qoriq-clockgen-1.0", },
	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	{}
};

static int __init qoriq_cpufreq_init(void)
{
	int ret;
	struct device_node  *np;
	const struct of_device_id *match;
	const struct soc_data *data;

	np = of_find_matching_node(NULL, node_matches);
	if (!np)
		return -ENODEV;

	match = of_match_node(node_matches, np);
	data = match->data;

	of_node_put(np);

	if (data && data->flags & SOC_BLACKLIST)
		return -ENODEV;

	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
	if (!ret)
		pr_info("Freescale QorIQ CPU frequency scaling driver\n");

	return ret;
}
module_init(qoriq_cpufreq_init);

static void __exit qoriq_cpufreq_exit(void)
{
	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
}
module_exit(qoriq_cpufreq_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");
Commit	Line	Data
defa4c73 TY	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
a4f20742	4	* CPU Frequency Scaling driver for Freescale QorIQ SoCs.
defa4c73 TY	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	12
	13	#include <linux/clk.h>
b1e9a649	14	#include <linux/clk-provider.h>
defa4c73	15	#include <linux/cpufreq.h>
8ae1702a	16	#include <linux/cpu_cooling.h>
defa4c73	17	#include <linux/errno.h>
defa4c73 TY	18	#include <linux/init.h>
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/mutex.h>
	22	#include <linux/of.h>
	23	#include <linux/slab.h>
	24	#include <linux/smp.h>
	25
4492d1a2	26	#if !defined(CONFIG_ARM)
5877b4f4	27	#include <asm/smp.h> /* for get_hard_smp_processor_id() in UP configs */
4492d1a2	28	#endif
5877b4f4	29
defa4c73	30	/**
a4f20742	31	* struct cpu_data
8a95c144	32	* @pclk: the parent clock of cpu
defa4c73 TY	33	* @table: frequency table
	34	*/
	35	struct cpu_data {
8a95c144	36	struct clk **pclk;
defa4c73	37	struct cpufreq_frequency_table *table;
8ae1702a	38	struct thermal_cooling_device *cdev;
defa4c73 TY	39	};
defa4c73 TY	40
b1e9a649 TY	41	/*
	42	* Don't use cpufreq on this SoC -- used when the SoC would have otherwise
	43	* matched a more generic compatible.
	44	*/
	45	#define SOC_BLACKLIST 1
	46
defa4c73 TY	47	/**
defa4c73 TY	48	* struct soc_data - SoC specific data
b1e9a649	49	* @flags: SOC_xxx
defa4c73 TY	50	*/
defa4c73 TY	51	struct soc_data {
b1e9a649	52	u32 flags;
defa4c73 TY	53	};
defa4c73 TY	54
a4f20742 TY	55	static u32 get_bus_freq(void)
	56	{
	57	struct device_node *soc;
	58	u32 sysfreq;
	59
	60	soc = of_find_node_by_type(NULL, "soc");
	61	if (!soc)
	62	return 0;
	63
	64	if (of_property_read_u32(soc, "bus-frequency", &sysfreq))
	65	sysfreq = 0;
	66
	67	of_node_put(soc);
defa4c73	68
a4f20742 TY	69	return sysfreq;
a4f20742 TY	70	}
defa4c73	71
b1e9a649	72	static struct clk *cpu_to_clk(int cpu)
defa4c73	73	{
b1e9a649 TY	74	struct device_node *np;
b1e9a649 TY	75	struct clk *clk;
a4f20742 TY	76
	77	if (!cpu_present(cpu))
	78	return NULL;
	79
	80	np = of_get_cpu_node(cpu, NULL);
	81	if (!np)
	82	return NULL;
	83
b1e9a649	84	clk = of_clk_get(np, 0);
a4f20742	85	of_node_put(np);
b1e9a649	86	return clk;
a4f20742 TY	87	}
	88
	89	/* traverse cpu nodes to get cpu mask of sharing clock wire */
	90	static void set_affected_cpus(struct cpufreq_policy *policy)
	91	{
a4f20742	92	struct cpumask *dstp = policy->cpus;
b1e9a649	93	struct clk *clk;
a4f20742 TY	94	int i;
a4f20742 TY	95
a4f20742	96	for_each_present_cpu(i) {
b1e9a649 TY	97	clk = cpu_to_clk(i);
	98	if (IS_ERR(clk)) {
	99	pr_err("%s: no clock for cpu %d\n", __func__, i);
a4f20742	100	continue;
b1e9a649	101	}
a4f20742	102
b1e9a649	103	if (clk_is_match(policy->clk, clk))
a4f20742	104	cpumask_set_cpu(i, dstp);
a4f20742	105	}
defa4c73	106	}
defa4c73	107
defa4c73 TY	108	/* reduce the duplicated frequencies in frequency table */
	109	static void freq_table_redup(struct cpufreq_frequency_table *freq_table,
	110	int count)
	111	{
	112	int i, j;
	113
	114	for (i = 1; i < count; i++) {
	115	for (j = 0; j < i; j++) {
	116	if (freq_table[j].frequency == CPUFREQ_ENTRY_INVALID \|\|
	117	freq_table[j].frequency !=
	118	freq_table[i].frequency)
	119	continue;
	120
	121	freq_table[i].frequency = CPUFREQ_ENTRY_INVALID;
	122	break;
	123	}
	124	}
	125	}
	126
	127	/* sort the frequencies in frequency table in descenting order */
	128	static void freq_table_sort(struct cpufreq_frequency_table *freq_table,
	129	int count)
	130	{
	131	int i, j, ind;
	132	unsigned int freq, max_freq;
	133	struct cpufreq_frequency_table table;
a4f20742	134
defa4c73 TY	135	for (i = 0; i < count - 1; i++) {
	136	max_freq = freq_table[i].frequency;
	137	ind = i;
	138	for (j = i + 1; j < count; j++) {
	139	freq = freq_table[j].frequency;
	140	if (freq == CPUFREQ_ENTRY_INVALID \|\|
	141	freq <= max_freq)
	142	continue;
	143	ind = j;
	144	max_freq = freq;
	145	}
	146
	147	if (ind != i) {
	148	/* exchange the frequencies */
	149	table.driver_data = freq_table[i].driver_data;
	150	table.frequency = freq_table[i].frequency;
	151	freq_table[i].driver_data = freq_table[ind].driver_data;
	152	freq_table[i].frequency = freq_table[ind].frequency;
	153	freq_table[ind].driver_data = table.driver_data;
	154	freq_table[ind].frequency = table.frequency;
	155	}
	156	}
	157	}
	158
a4f20742	159	static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
defa4c73	160	{
b1e9a649	161	struct device_node *np;
defa4c73	162	int i, count, ret;
b1e9a649	163	u32 freq;
defa4c73	164	struct clk *clk;
b1e9a649	165	const struct clk_hw *hwclk;
defa4c73 TY	166	struct cpufreq_frequency_table *table;
	167	struct cpu_data *data;
	168	unsigned int cpu = policy->cpu;
906fe033	169	u64 u64temp;
defa4c73 TY	170
	171	np = of_get_cpu_node(cpu, NULL);
	172	if (!np)
	173	return -ENODEV;
	174
	175	data = kzalloc(sizeof(*data), GFP_KERNEL);
a4f20742	176	if (!data)
defa4c73	177	goto err_np;
defa4c73	178
652ed95d VK	179	policy->clk = of_clk_get(np, 0);
652ed95d VK	180	if (IS_ERR(policy->clk)) {
defa4c73 TY	181	pr_err("%s: no clock information\n", __func__);
	182	goto err_nomem2;
	183	}
	184
b1e9a649 TY	185	hwclk = __clk_get_hw(policy->clk);
b1e9a649 TY	186	count = clk_hw_get_num_parents(hwclk);
defa4c73	187
8a95c144 TY	188	data->pclk = kcalloc(count, sizeof(struct clk *), GFP_KERNEL);
	189	if (!data->pclk) {
	190	pr_err("%s: no memory\n", __func__);
b1e9a649	191	goto err_nomem2;
8a95c144 TY	192	}
8a95c144 TY	193
defa4c73 TY	194	table = kcalloc(count + 1, sizeof(*table), GFP_KERNEL);
	195	if (!table) {
	196	pr_err("%s: no memory\n", __func__);
8a95c144	197	goto err_pclk;
defa4c73 TY	198	}
defa4c73 TY	199
defa4c73	200	for (i = 0; i < count; i++) {
b1e9a649	201	clk = clk_hw_get_parent_by_index(hwclk, i)->clk;
8a95c144	202	data->pclk[i] = clk;
defa4c73	203	freq = clk_get_rate(clk);
b1e9a649	204	table[i].frequency = freq / 1000;
defa4c73 TY	205	table[i].driver_data = i;
	206	}
	207	freq_table_redup(table, count);
	208	freq_table_sort(table, count);
	209	table[i].frequency = CPUFREQ_TABLE_END;
	210
	211	/* set the min and max frequency properly */
6b4147db	212	ret = cpufreq_table_validate_and_show(policy, table);
defa4c73 TY	213	if (ret) {
	214	pr_err("invalid frequency table: %d\n", ret);
	215	goto err_nomem1;
	216	}
	217
	218	data->table = table;
defa4c73 TY	219
defa4c73 TY	220	/* update ->cpus if we have cluster, no harm if not */
a4f20742 TY	221	set_affected_cpus(policy);
a4f20742 TY	222	policy->driver_data = data;
defa4c73	223
906fe033 ES	224	/* Minimum transition latency is 12 platform clocks */
906fe033 ES	225	u64temp = 12ULL * NSEC_PER_SEC;
a4f20742	226	do_div(u64temp, get_bus_freq());
906fe033	227	policy->cpuinfo.transition_latency = u64temp + 1;
6712d293	228
defa4c73 TY	229	of_node_put(np);
	230
	231	return 0;
	232
	233	err_nomem1:
	234	kfree(table);
8a95c144 TY	235	err_pclk:
8a95c144 TY	236	kfree(data->pclk);
defa4c73	237	err_nomem2:
defa4c73 TY	238	kfree(data);
	239	err_np:
	240	of_node_put(np);
	241
	242	return -ENODEV;
	243	}
	244
495c716f	245	static int qoriq_cpufreq_cpu_exit(struct cpufreq_policy *policy)
defa4c73	246	{
a4f20742	247	struct cpu_data *data = policy->driver_data;
defa4c73	248
394cb831	249	cpufreq_cooling_unregister(data->cdev);
8a95c144	250	kfree(data->pclk);
defa4c73 TY	251	kfree(data->table);
defa4c73 TY	252	kfree(data);
a4f20742	253	policy->driver_data = NULL;
defa4c73 TY	254
	255	return 0;
	256	}
	257
a4f20742	258	static int qoriq_cpufreq_target(struct cpufreq_policy *policy,
9c0ebcf7	259	unsigned int index)
defa4c73	260	{
defa4c73	261	struct clk *parent;
a4f20742	262	struct cpu_data *data = policy->driver_data;
defa4c73	263
8a95c144	264	parent = data->pclk[data->table[index].driver_data];
652ed95d	265	return clk_set_parent(policy->clk, parent);
defa4c73 TY	266	}
defa4c73 TY	267
8ae1702a HJ	268
	269	static void qoriq_cpufreq_ready(struct cpufreq_policy *policy)
	270	{
	271	struct cpu_data *cpud = policy->driver_data;
	272	struct device_node *np = of_get_cpu_node(policy->cpu, NULL);
	273
	274	if (of_find_property(np, "#cooling-cells", NULL)) {
	275	cpud->cdev = of_cpufreq_cooling_register(np,
	276	policy->related_cpus);
	277
27b8fe8d JH	278	if (IS_ERR(cpud->cdev) && PTR_ERR(cpud->cdev) != -ENOSYS) {
27b8fe8d JH	279	pr_err("cpu%d is not running as cooling device: %ld\n",
8ae1702a HJ	280	policy->cpu, PTR_ERR(cpud->cdev));
	281
	282	cpud->cdev = NULL;
	283	}
	284	}
	285
	286	of_node_put(np);
	287	}
	288
a4f20742 TY	289	static struct cpufreq_driver qoriq_cpufreq_driver = {
a4f20742 TY	290	.name = "qoriq_cpufreq",
defa4c73	291	.flags = CPUFREQ_CONST_LOOPS,
a4f20742	292	.init = qoriq_cpufreq_cpu_init,
495c716f	293	.exit = qoriq_cpufreq_cpu_exit,
dc2398d7	294	.verify = cpufreq_generic_frequency_table_verify,
a4f20742	295	.target_index = qoriq_cpufreq_target,
652ed95d	296	.get = cpufreq_generic_get,
8ae1702a	297	.ready = qoriq_cpufreq_ready,
dc2398d7	298	.attr = cpufreq_generic_attr,
defa4c73 TY	299	};
defa4c73 TY	300
b1e9a649 TY	301	static const struct soc_data blacklist = {
	302	.flags = SOC_BLACKLIST,
	303	};
	304
a4f20742	305	static const struct of_device_id node_matches[] __initconst = {
b1e9a649 TY	306	/* e6500 cannot use cpufreq due to erratum A-008083 */
	307	{ .compatible = "fsl,b4420-clockgen", &blacklist },
	308	{ .compatible = "fsl,b4860-clockgen", &blacklist },
	309	{ .compatible = "fsl,t2080-clockgen", &blacklist },
	310	{ .compatible = "fsl,t4240-clockgen", &blacklist },
	311
	312	{ .compatible = "fsl,ls1012a-clockgen", },
	313	{ .compatible = "fsl,ls1021a-clockgen", },
	314	{ .compatible = "fsl,ls1043a-clockgen", },
	315	{ .compatible = "fsl,ls1046a-clockgen", },
	316	{ .compatible = "fsl,ls1088a-clockgen", },
	317	{ .compatible = "fsl,ls2080a-clockgen", },
	318	{ .compatible = "fsl,p4080-clockgen", },
	319	{ .compatible = "fsl,qoriq-clockgen-1.0", },
defa4c73 TY	320	{ .compatible = "fsl,qoriq-clockgen-2.0", },
	321	{}
	322	};
	323
a4f20742	324	static int __init qoriq_cpufreq_init(void)
defa4c73 TY	325	{
	326	int ret;
	327	struct device_node *np;
	328	const struct of_device_id *match;
	329	const struct soc_data *data;
defa4c73 TY	330
	331	np = of_find_matching_node(NULL, node_matches);
	332	if (!np)
	333	return -ENODEV;
	334
defa4c73 TY	335	match = of_match_node(node_matches, np);
defa4c73 TY	336	data = match->data;
defa4c73 TY	337
	338	of_node_put(np);
	339
b1e9a649 TY	340	if (data && data->flags & SOC_BLACKLIST)
	341	return -ENODEV;
	342
a4f20742	343	ret = cpufreq_register_driver(&qoriq_cpufreq_driver);
defa4c73	344	if (!ret)
a4f20742	345	pr_info("Freescale QorIQ CPU frequency scaling driver\n");
defa4c73 TY	346
defa4c73 TY	347	return ret;
defa4c73	348	}
a4f20742	349	module_init(qoriq_cpufreq_init);
defa4c73	350
a4f20742	351	static void __exit qoriq_cpufreq_exit(void)
defa4c73	352	{
a4f20742	353	cpufreq_unregister_driver(&qoriq_cpufreq_driver);
defa4c73	354	}
a4f20742	355	module_exit(qoriq_cpufreq_exit);
defa4c73 TY	356
	357	MODULE_LICENSE("GPL");
	358	MODULE_AUTHOR("Tang Yuantian <Yuantian.Tang@freescale.com>");
a4f20742	359	MODULE_DESCRIPTION("cpufreq driver for Freescale QorIQ series SoCs");