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34ee5507 HS |
1 | /* |
2 | * S3C2416/2450 CPUfreq Support | |
3 | * | |
4 | * Copyright 2011 Heiko Stuebner <heiko@sntech.de> | |
5 | * | |
6 | * based on s3c64xx_cpufreq.c | |
7 | * | |
8 | * Copyright 2009 Wolfson Microelectronics plc | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/types.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/cpufreq.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/regulator/consumer.h> | |
22 | #include <linux/reboot.h> | |
23 | #include <linux/module.h> | |
24 | ||
25 | static DEFINE_MUTEX(cpufreq_lock); | |
26 | ||
27 | struct s3c2416_data { | |
28 | struct clk *armdiv; | |
29 | struct clk *armclk; | |
30 | struct clk *hclk; | |
31 | ||
32 | unsigned long regulator_latency; | |
33 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
34 | struct regulator *vddarm; | |
35 | #endif | |
36 | ||
37 | struct cpufreq_frequency_table *freq_table; | |
38 | ||
39 | bool is_dvs; | |
40 | bool disable_dvs; | |
41 | }; | |
42 | ||
43 | static struct s3c2416_data s3c2416_cpufreq; | |
44 | ||
45 | struct s3c2416_dvfs { | |
46 | unsigned int vddarm_min; | |
47 | unsigned int vddarm_max; | |
48 | }; | |
49 | ||
50 | /* pseudo-frequency for dvs mode */ | |
51 | #define FREQ_DVS 132333 | |
52 | ||
53 | /* frequency to sleep and reboot in | |
54 | * it's essential to leave dvs, as some boards do not reconfigure the | |
55 | * regulator on reboot | |
56 | */ | |
57 | #define FREQ_SLEEP 133333 | |
58 | ||
59 | /* Sources for the ARMCLK */ | |
60 | #define SOURCE_HCLK 0 | |
61 | #define SOURCE_ARMDIV 1 | |
62 | ||
63 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
64 | /* S3C2416 only supports changing the voltage in the dvs-mode. | |
65 | * Voltages down to 1.0V seem to work, so we take what the regulator | |
66 | * can get us. | |
67 | */ | |
68 | static struct s3c2416_dvfs s3c2416_dvfs_table[] = { | |
69 | [SOURCE_HCLK] = { 950000, 1250000 }, | |
70 | [SOURCE_ARMDIV] = { 1250000, 1350000 }, | |
71 | }; | |
72 | #endif | |
73 | ||
74 | static struct cpufreq_frequency_table s3c2416_freq_table[] = { | |
75 | { SOURCE_HCLK, FREQ_DVS }, | |
76 | { SOURCE_ARMDIV, 133333 }, | |
77 | { SOURCE_ARMDIV, 266666 }, | |
78 | { SOURCE_ARMDIV, 400000 }, | |
79 | { 0, CPUFREQ_TABLE_END }, | |
80 | }; | |
81 | ||
82 | static struct cpufreq_frequency_table s3c2450_freq_table[] = { | |
83 | { SOURCE_HCLK, FREQ_DVS }, | |
84 | { SOURCE_ARMDIV, 133500 }, | |
85 | { SOURCE_ARMDIV, 267000 }, | |
86 | { SOURCE_ARMDIV, 534000 }, | |
87 | { 0, CPUFREQ_TABLE_END }, | |
88 | }; | |
89 | ||
34ee5507 HS |
90 | static unsigned int s3c2416_cpufreq_get_speed(unsigned int cpu) |
91 | { | |
92 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
93 | ||
94 | if (cpu != 0) | |
95 | return 0; | |
96 | ||
97 | /* return our pseudo-frequency when in dvs mode */ | |
98 | if (s3c_freq->is_dvs) | |
99 | return FREQ_DVS; | |
100 | ||
101 | return clk_get_rate(s3c_freq->armclk) / 1000; | |
102 | } | |
103 | ||
104 | static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq, | |
105 | unsigned int freq) | |
106 | { | |
107 | int ret; | |
108 | ||
109 | if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) { | |
110 | ret = clk_set_rate(s3c_freq->armdiv, freq * 1000); | |
111 | if (ret < 0) { | |
112 | pr_err("cpufreq: Failed to set armdiv rate %dkHz: %d\n", | |
113 | freq, ret); | |
114 | return ret; | |
115 | } | |
116 | } | |
117 | ||
118 | return 0; | |
119 | } | |
120 | ||
121 | static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx) | |
122 | { | |
123 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
124 | struct s3c2416_dvfs *dvfs; | |
125 | #endif | |
126 | int ret; | |
127 | ||
128 | if (s3c_freq->is_dvs) { | |
129 | pr_debug("cpufreq: already in dvs mode, nothing to do\n"); | |
130 | return 0; | |
131 | } | |
132 | ||
133 | pr_debug("cpufreq: switching armclk to hclk (%lukHz)\n", | |
134 | clk_get_rate(s3c_freq->hclk) / 1000); | |
135 | ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk); | |
136 | if (ret < 0) { | |
137 | pr_err("cpufreq: Failed to switch armclk to hclk: %d\n", ret); | |
138 | return ret; | |
139 | } | |
140 | ||
141 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
142 | /* changing the core voltage is only allowed when in dvs mode */ | |
143 | if (s3c_freq->vddarm) { | |
144 | dvfs = &s3c2416_dvfs_table[idx]; | |
145 | ||
c03c3013 | 146 | pr_debug("cpufreq: setting regulator to %d-%d\n", |
34ee5507 HS |
147 | dvfs->vddarm_min, dvfs->vddarm_max); |
148 | ret = regulator_set_voltage(s3c_freq->vddarm, | |
149 | dvfs->vddarm_min, | |
150 | dvfs->vddarm_max); | |
151 | ||
152 | /* when lowering the voltage failed, there is nothing to do */ | |
153 | if (ret != 0) | |
154 | pr_err("cpufreq: Failed to set VDDARM: %d\n", ret); | |
155 | } | |
156 | #endif | |
157 | ||
158 | s3c_freq->is_dvs = 1; | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx) | |
164 | { | |
165 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
166 | struct s3c2416_dvfs *dvfs; | |
167 | #endif | |
168 | int ret; | |
169 | ||
170 | if (!s3c_freq->is_dvs) { | |
171 | pr_debug("cpufreq: not in dvs mode, so can't leave\n"); | |
172 | return 0; | |
173 | } | |
174 | ||
175 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
176 | if (s3c_freq->vddarm) { | |
177 | dvfs = &s3c2416_dvfs_table[idx]; | |
178 | ||
c03c3013 | 179 | pr_debug("cpufreq: setting regulator to %d-%d\n", |
34ee5507 HS |
180 | dvfs->vddarm_min, dvfs->vddarm_max); |
181 | ret = regulator_set_voltage(s3c_freq->vddarm, | |
182 | dvfs->vddarm_min, | |
183 | dvfs->vddarm_max); | |
184 | if (ret != 0) { | |
185 | pr_err("cpufreq: Failed to set VDDARM: %d\n", ret); | |
186 | return ret; | |
187 | } | |
188 | } | |
189 | #endif | |
190 | ||
191 | /* force armdiv to hclk frequency for transition from dvs*/ | |
192 | if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) { | |
193 | pr_debug("cpufreq: force armdiv to hclk frequency (%lukHz)\n", | |
194 | clk_get_rate(s3c_freq->hclk) / 1000); | |
195 | ret = s3c2416_cpufreq_set_armdiv(s3c_freq, | |
196 | clk_get_rate(s3c_freq->hclk) / 1000); | |
197 | if (ret < 0) { | |
278cee05 | 198 | pr_err("cpufreq: Failed to set the armdiv to %lukHz: %d\n", |
34ee5507 HS |
199 | clk_get_rate(s3c_freq->hclk) / 1000, ret); |
200 | return ret; | |
201 | } | |
202 | } | |
203 | ||
204 | pr_debug("cpufreq: switching armclk parent to armdiv (%lukHz)\n", | |
205 | clk_get_rate(s3c_freq->armdiv) / 1000); | |
206 | ||
207 | ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv); | |
208 | if (ret < 0) { | |
209 | pr_err("cpufreq: Failed to switch armclk clock parent to armdiv: %d\n", | |
210 | ret); | |
211 | return ret; | |
212 | } | |
213 | ||
214 | s3c_freq->is_dvs = 0; | |
215 | ||
216 | return 0; | |
217 | } | |
218 | ||
219 | static int s3c2416_cpufreq_set_target(struct cpufreq_policy *policy, | |
220 | unsigned int target_freq, | |
221 | unsigned int relation) | |
222 | { | |
223 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
224 | struct cpufreq_freqs freqs; | |
225 | int idx, ret, to_dvs = 0; | |
226 | unsigned int i; | |
227 | ||
228 | mutex_lock(&cpufreq_lock); | |
229 | ||
230 | pr_debug("cpufreq: to %dKHz, relation %d\n", target_freq, relation); | |
231 | ||
232 | ret = cpufreq_frequency_table_target(policy, s3c_freq->freq_table, | |
233 | target_freq, relation, &i); | |
234 | if (ret != 0) | |
235 | goto out; | |
236 | ||
50701588 | 237 | idx = s3c_freq->freq_table[i].driver_data; |
34ee5507 HS |
238 | |
239 | if (idx == SOURCE_HCLK) | |
240 | to_dvs = 1; | |
241 | ||
242 | /* switching to dvs when it's not allowed */ | |
243 | if (to_dvs && s3c_freq->disable_dvs) { | |
244 | pr_debug("cpufreq: entering dvs mode not allowed\n"); | |
245 | ret = -EINVAL; | |
246 | goto out; | |
247 | } | |
248 | ||
34ee5507 HS |
249 | freqs.flags = 0; |
250 | freqs.old = s3c_freq->is_dvs ? FREQ_DVS | |
251 | : clk_get_rate(s3c_freq->armclk) / 1000; | |
252 | ||
253 | /* When leavin dvs mode, always switch the armdiv to the hclk rate | |
254 | * The S3C2416 has stability issues when switching directly to | |
255 | * higher frequencies. | |
256 | */ | |
257 | freqs.new = (s3c_freq->is_dvs && !to_dvs) | |
258 | ? clk_get_rate(s3c_freq->hclk) / 1000 | |
259 | : s3c_freq->freq_table[i].frequency; | |
260 | ||
261 | pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new); | |
262 | ||
263 | if (!to_dvs && freqs.old == freqs.new) | |
264 | goto out; | |
265 | ||
b43a7ffb | 266 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE); |
34ee5507 HS |
267 | |
268 | if (to_dvs) { | |
269 | pr_debug("cpufreq: enter dvs\n"); | |
270 | ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx); | |
271 | } else if (s3c_freq->is_dvs) { | |
272 | pr_debug("cpufreq: leave dvs\n"); | |
273 | ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx); | |
274 | } else { | |
275 | pr_debug("cpufreq: change armdiv to %dkHz\n", freqs.new); | |
276 | ret = s3c2416_cpufreq_set_armdiv(s3c_freq, freqs.new); | |
277 | } | |
278 | ||
b43a7ffb | 279 | cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE); |
34ee5507 HS |
280 | |
281 | out: | |
282 | mutex_unlock(&cpufreq_lock); | |
283 | ||
284 | return ret; | |
285 | } | |
286 | ||
287 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
288 | static void __init s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq) | |
289 | { | |
290 | int count, v, i, found; | |
291 | struct cpufreq_frequency_table *freq; | |
292 | struct s3c2416_dvfs *dvfs; | |
293 | ||
294 | count = regulator_count_voltages(s3c_freq->vddarm); | |
295 | if (count < 0) { | |
296 | pr_err("cpufreq: Unable to check supported voltages\n"); | |
297 | return; | |
298 | } | |
299 | ||
300 | freq = s3c_freq->freq_table; | |
301 | while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) { | |
302 | if (freq->frequency == CPUFREQ_ENTRY_INVALID) | |
303 | continue; | |
304 | ||
166b9add | 305 | dvfs = &s3c2416_dvfs_table[freq->driver_data]; |
34ee5507 HS |
306 | found = 0; |
307 | ||
308 | /* Check only the min-voltage, more is always ok on S3C2416 */ | |
309 | for (i = 0; i < count; i++) { | |
310 | v = regulator_list_voltage(s3c_freq->vddarm, i); | |
311 | if (v >= dvfs->vddarm_min) | |
312 | found = 1; | |
313 | } | |
314 | ||
315 | if (!found) { | |
316 | pr_debug("cpufreq: %dkHz unsupported by regulator\n", | |
317 | freq->frequency); | |
318 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
319 | } | |
320 | ||
321 | freq++; | |
322 | } | |
323 | ||
324 | /* Guessed */ | |
325 | s3c_freq->regulator_latency = 1 * 1000 * 1000; | |
326 | } | |
327 | #endif | |
328 | ||
329 | static int s3c2416_cpufreq_reboot_notifier_evt(struct notifier_block *this, | |
330 | unsigned long event, void *ptr) | |
331 | { | |
332 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
333 | int ret; | |
334 | ||
335 | mutex_lock(&cpufreq_lock); | |
336 | ||
337 | /* disable further changes */ | |
338 | s3c_freq->disable_dvs = 1; | |
339 | ||
340 | mutex_unlock(&cpufreq_lock); | |
341 | ||
342 | /* some boards don't reconfigure the regulator on reboot, which | |
343 | * could lead to undervolting the cpu when the clock is reset. | |
344 | * Therefore we always leave the DVS mode on reboot. | |
345 | */ | |
346 | if (s3c_freq->is_dvs) { | |
347 | pr_debug("cpufreq: leave dvs on reboot\n"); | |
348 | ret = cpufreq_driver_target(cpufreq_cpu_get(0), FREQ_SLEEP, 0); | |
349 | if (ret < 0) | |
350 | return NOTIFY_BAD; | |
351 | } | |
352 | ||
353 | return NOTIFY_DONE; | |
354 | } | |
355 | ||
356 | static struct notifier_block s3c2416_cpufreq_reboot_notifier = { | |
357 | .notifier_call = s3c2416_cpufreq_reboot_notifier_evt, | |
358 | }; | |
359 | ||
360 | static int __init s3c2416_cpufreq_driver_init(struct cpufreq_policy *policy) | |
361 | { | |
362 | struct s3c2416_data *s3c_freq = &s3c2416_cpufreq; | |
363 | struct cpufreq_frequency_table *freq; | |
364 | struct clk *msysclk; | |
365 | unsigned long rate; | |
366 | int ret; | |
367 | ||
368 | if (policy->cpu != 0) | |
369 | return -EINVAL; | |
370 | ||
371 | msysclk = clk_get(NULL, "msysclk"); | |
372 | if (IS_ERR(msysclk)) { | |
373 | ret = PTR_ERR(msysclk); | |
374 | pr_err("cpufreq: Unable to obtain msysclk: %d\n", ret); | |
375 | return ret; | |
376 | } | |
377 | ||
378 | /* | |
379 | * S3C2416 and S3C2450 share the same processor-ID and also provide no | |
380 | * other means to distinguish them other than through the rate of | |
381 | * msysclk. On S3C2416 msysclk runs at 800MHz and on S3C2450 at 533MHz. | |
382 | */ | |
383 | rate = clk_get_rate(msysclk); | |
384 | if (rate == 800 * 1000 * 1000) { | |
385 | pr_info("cpufreq: msysclk running at %lukHz, using S3C2416 frequency table\n", | |
386 | rate / 1000); | |
387 | s3c_freq->freq_table = s3c2416_freq_table; | |
388 | policy->cpuinfo.max_freq = 400000; | |
389 | } else if (rate / 1000 == 534000) { | |
390 | pr_info("cpufreq: msysclk running at %lukHz, using S3C2450 frequency table\n", | |
391 | rate / 1000); | |
392 | s3c_freq->freq_table = s3c2450_freq_table; | |
393 | policy->cpuinfo.max_freq = 534000; | |
394 | } | |
395 | ||
396 | /* not needed anymore */ | |
397 | clk_put(msysclk); | |
398 | ||
399 | if (s3c_freq->freq_table == NULL) { | |
400 | pr_err("cpufreq: No frequency information for this CPU, msysclk at %lukHz\n", | |
401 | rate / 1000); | |
402 | return -ENODEV; | |
403 | } | |
404 | ||
405 | s3c_freq->is_dvs = 0; | |
406 | ||
407 | s3c_freq->armdiv = clk_get(NULL, "armdiv"); | |
408 | if (IS_ERR(s3c_freq->armdiv)) { | |
409 | ret = PTR_ERR(s3c_freq->armdiv); | |
410 | pr_err("cpufreq: Unable to obtain ARMDIV: %d\n", ret); | |
411 | return ret; | |
412 | } | |
413 | ||
414 | s3c_freq->hclk = clk_get(NULL, "hclk"); | |
415 | if (IS_ERR(s3c_freq->hclk)) { | |
416 | ret = PTR_ERR(s3c_freq->hclk); | |
417 | pr_err("cpufreq: Unable to obtain HCLK: %d\n", ret); | |
418 | goto err_hclk; | |
419 | } | |
420 | ||
421 | /* chech hclk rate, we only support the common 133MHz for now | |
422 | * hclk could also run at 66MHz, but this not often used | |
423 | */ | |
424 | rate = clk_get_rate(s3c_freq->hclk); | |
425 | if (rate < 133 * 1000 * 1000) { | |
426 | pr_err("cpufreq: HCLK not at 133MHz\n"); | |
427 | clk_put(s3c_freq->hclk); | |
428 | ret = -EINVAL; | |
429 | goto err_armclk; | |
430 | } | |
431 | ||
432 | s3c_freq->armclk = clk_get(NULL, "armclk"); | |
433 | if (IS_ERR(s3c_freq->armclk)) { | |
434 | ret = PTR_ERR(s3c_freq->armclk); | |
435 | pr_err("cpufreq: Unable to obtain ARMCLK: %d\n", ret); | |
436 | goto err_armclk; | |
437 | } | |
438 | ||
439 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
440 | s3c_freq->vddarm = regulator_get(NULL, "vddarm"); | |
441 | if (IS_ERR(s3c_freq->vddarm)) { | |
442 | ret = PTR_ERR(s3c_freq->vddarm); | |
443 | pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret); | |
444 | goto err_vddarm; | |
445 | } | |
446 | ||
447 | s3c2416_cpufreq_cfg_regulator(s3c_freq); | |
448 | #else | |
449 | s3c_freq->regulator_latency = 0; | |
450 | #endif | |
451 | ||
452 | freq = s3c_freq->freq_table; | |
453 | while (freq->frequency != CPUFREQ_TABLE_END) { | |
454 | /* special handling for dvs mode */ | |
166b9add | 455 | if (freq->driver_data == 0) { |
34ee5507 HS |
456 | if (!s3c_freq->hclk) { |
457 | pr_debug("cpufreq: %dkHz unsupported as it would need unavailable dvs mode\n", | |
458 | freq->frequency); | |
459 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
460 | } else { | |
461 | freq++; | |
462 | continue; | |
463 | } | |
464 | } | |
465 | ||
466 | /* Check for frequencies we can generate */ | |
467 | rate = clk_round_rate(s3c_freq->armdiv, | |
468 | freq->frequency * 1000); | |
469 | rate /= 1000; | |
470 | if (rate != freq->frequency) { | |
471 | pr_debug("cpufreq: %dkHz unsupported by clock (clk_round_rate return %lu)\n", | |
472 | freq->frequency, rate); | |
473 | freq->frequency = CPUFREQ_ENTRY_INVALID; | |
474 | } | |
475 | ||
476 | freq++; | |
477 | } | |
478 | ||
34ee5507 HS |
479 | /* Datasheet says PLL stabalisation time must be at least 300us, |
480 | * so but add some fudge. (reference in LOCKCON0 register description) | |
481 | */ | |
482 | policy->cpuinfo.transition_latency = (500 * 1000) + | |
483 | s3c_freq->regulator_latency; | |
484 | ||
4974b8ea | 485 | ret = cpufreq_table_validate_and_show(policy, s3c_freq->freq_table); |
34ee5507 HS |
486 | if (ret) |
487 | goto err_freq_table; | |
488 | ||
34ee5507 HS |
489 | register_reboot_notifier(&s3c2416_cpufreq_reboot_notifier); |
490 | ||
491 | return 0; | |
492 | ||
493 | err_freq_table: | |
494 | #ifdef CONFIG_ARM_S3C2416_CPUFREQ_VCORESCALE | |
495 | regulator_put(s3c_freq->vddarm); | |
496 | err_vddarm: | |
497 | #endif | |
498 | clk_put(s3c_freq->armclk); | |
499 | err_armclk: | |
500 | clk_put(s3c_freq->hclk); | |
501 | err_hclk: | |
502 | clk_put(s3c_freq->armdiv); | |
503 | ||
504 | return ret; | |
505 | } | |
506 | ||
34ee5507 | 507 | static struct cpufreq_driver s3c2416_cpufreq_driver = { |
34ee5507 | 508 | .flags = 0, |
e96a4105 | 509 | .verify = cpufreq_generic_frequency_table_verify, |
34ee5507 HS |
510 | .target = s3c2416_cpufreq_set_target, |
511 | .get = s3c2416_cpufreq_get_speed, | |
512 | .init = s3c2416_cpufreq_driver_init, | |
513 | .name = "s3c2416", | |
e96a4105 | 514 | .attr = cpufreq_generic_attr, |
34ee5507 HS |
515 | }; |
516 | ||
517 | static int __init s3c2416_cpufreq_init(void) | |
518 | { | |
519 | return cpufreq_register_driver(&s3c2416_cpufreq_driver); | |
520 | } | |
521 | module_init(s3c2416_cpufreq_init); |