[mirror_ubuntu-zesty-kernel.git] / drivers / cpufreq / s3c2440-cpufreq.c

/*
 * Copyright (c) 2006-2009 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *	Vincent Sanders <vince@simtec.co.uk>
 *
 * S3C2440/S3C2442 CPU Frequency scaling
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/init.h>
#include <linux/module.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/cpufreq.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>

#include <mach/regs-clock.h>

#include <plat/cpu.h>
#include <plat/cpu-freq-core.h>

static struct clk *xtal;
static struct clk *fclk;
static struct clk *hclk;
static struct clk *armclk;

/* HDIV: 1, 2, 3, 4, 6, 8 */

static inline int within_khz(unsigned long a, unsigned long b)
{
	long diff = a - b;

	return (diff >= -1000 && diff <= 1000);
}

/**
 * s3c2440_cpufreq_calcdivs - calculate divider settings
 * @cfg: The cpu frequency settings.
 *
 * Calcualte the divider values for the given frequency settings
 * specified in @cfg. The values are stored in @cfg for later use
 * by the relevant set routine if the request settings can be reached.
 */
static int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
{
	unsigned int hdiv, pdiv;
	unsigned long hclk, fclk, armclk;
	unsigned long hclk_max;

	fclk = cfg->freq.fclk;
	armclk = cfg->freq.armclk;
	hclk_max = cfg->max.hclk;

	s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
		     __func__, fclk, armclk, hclk_max);

	if (armclk > fclk) {
		pr_warn("%s: armclk > fclk\n", __func__);
		armclk = fclk;
	}

	/* if we are in DVS, we need HCLK to be <= ARMCLK */
	if (armclk < fclk && armclk < hclk_max)
		hclk_max = armclk;

	for (hdiv = 1; hdiv < 9; hdiv++) {
		if (hdiv == 5 || hdiv == 7)
			hdiv++;

		hclk = (fclk / hdiv);
		if (hclk <= hclk_max || within_khz(hclk, hclk_max))
			break;
	}

	s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);

	if (hdiv > 8)
		goto invalid;

	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;

	if ((hclk / pdiv) > cfg->max.pclk)
		pdiv++;

	s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);

	if (pdiv > 2)
		goto invalid;

	pdiv *= hdiv;

	/* calculate a valid armclk */

	if (armclk < hclk)
		armclk = hclk;

	/* if we're running armclk lower than fclk, this really means
	 * that the system should go into dvs mode, which means that
	 * armclk is connected to hclk. */
	if (armclk < fclk) {
		cfg->divs.dvs = 1;
		armclk = hclk;
	} else
		cfg->divs.dvs = 0;

	cfg->freq.armclk = armclk;

	/* store the result, and then return */

	cfg->divs.h_divisor = hdiv;
	cfg->divs.p_divisor = pdiv;

	return 0;

 invalid:
	return -EINVAL;
}

#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
			   S3C2440_CAMDIVN_HCLK4_HALF)

/**
 * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
 * @cfg: The cpu frequency settings.
 *
 * Set the divisors from the settings in @cfg, which where generated
 * during the calculation phase by s3c2440_cpufreq_calcdivs().
 */
static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
{
	unsigned long clkdiv, camdiv;

	s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
		     cfg->divs.h_divisor, cfg->divs.p_divisor);

	clkdiv = __raw_readl(S3C2410_CLKDIVN);
	camdiv = __raw_readl(S3C2440_CAMDIVN);

	clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
	camdiv &= ~CAMDIVN_HCLK_HALF;

	switch (cfg->divs.h_divisor) {
	case 1:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
		break;

	case 2:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
		break;

	case 6:
		camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
	case 3:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
		break;

	case 8:
		camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
	case 4:
		clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
		break;

	default:
		BUG();	/* we don't expect to get here. */
	}

	if (cfg->divs.p_divisor != cfg->divs.h_divisor)
		clkdiv |= S3C2440_CLKDIVN_PDIVN;

	/* todo - set pclk. */

	/* Write the divisors first with hclk intentionally halved so that
	 * when we write clkdiv we will under-frequency instead of over. We
	 * then make a short delay and remove the hclk halving if necessary.
	 */

	__raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
	__raw_writel(clkdiv, S3C2410_CLKDIVN);

	ndelay(20);
	__raw_writel(camdiv, S3C2440_CAMDIVN);

	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
}

static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
			int *divs,
			struct cpufreq_frequency_table *table,
			size_t table_size)
{
	unsigned long freq;
	int index = 0;
	int div;

	for (div = *divs; div > 0; div = *divs++) {
		freq = fclk / div;

		if (freq > max_hclk && div != 1)
			continue;

		freq /= 1000; /* table is in kHz */
		index = s3c_cpufreq_addfreq(table, index, table_size, freq);
		if (index < 0)
			break;
	}

	return index;
}

static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };

static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
				     struct cpufreq_frequency_table *table,
				     size_t table_size)
{
	int ret;

	WARN_ON(cfg->info == NULL);
	WARN_ON(cfg->board == NULL);

	ret = run_freq_for(cfg->info->max.hclk,
			   cfg->info->max.fclk,
			   hclk_divs,
			   table, table_size);

	s3c_freq_dbg("%s: returning %d\n", __func__, ret);

	return ret;
}

static struct s3c_cpufreq_info s3c2440_cpufreq_info = {
	.max		= {
		.fclk	= 400000000,
		.hclk	= 133333333,
		.pclk	=  66666666,
	},

	.locktime_m	= 300,
	.locktime_u	= 300,
	.locktime_bits	= 16,

	.name		= "s3c244x",
	.calc_iotiming	= s3c2410_iotiming_calc,
	.set_iotiming	= s3c2410_iotiming_set,
	.get_iotiming	= s3c2410_iotiming_get,
	.set_fvco	= s3c2410_set_fvco,

	.set_refresh	= s3c2410_cpufreq_setrefresh,
	.set_divs	= s3c2440_cpufreq_setdivs,
	.calc_divs	= s3c2440_cpufreq_calcdivs,
	.calc_freqtable	= s3c2440_cpufreq_calctable,

	.debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
};

static int s3c2440_cpufreq_add(struct device *dev,
			       struct subsys_interface *sif)
{
	xtal = s3c_cpufreq_clk_get(NULL, "xtal");
	hclk = s3c_cpufreq_clk_get(NULL, "hclk");
	fclk = s3c_cpufreq_clk_get(NULL, "fclk");
	armclk = s3c_cpufreq_clk_get(NULL, "armclk");

	if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
		pr_err("%s: failed to get clocks\n", __func__);
		return -ENOENT;
	}

	return s3c_cpufreq_register(&s3c2440_cpufreq_info);
}

static struct subsys_interface s3c2440_cpufreq_interface = {
	.name		= "s3c2440_cpufreq",
	.subsys		= &s3c2440_subsys,
	.add_dev	= s3c2440_cpufreq_add,
};

static int s3c2440_cpufreq_init(void)
{
	return subsys_interface_register(&s3c2440_cpufreq_interface);
}

/* arch_initcall adds the clocks we need, so use subsys_initcall. */
subsys_initcall(s3c2440_cpufreq_init);

static struct subsys_interface s3c2442_cpufreq_interface = {
	.name		= "s3c2442_cpufreq",
	.subsys		= &s3c2442_subsys,
	.add_dev	= s3c2440_cpufreq_add,
};

static int s3c2442_cpufreq_init(void)
{
	return subsys_interface_register(&s3c2442_cpufreq_interface);
}
subsys_initcall(s3c2442_cpufreq_init);
Commit	Line	Data
5aa93c0a	1	/*
ccae941e	2	* Copyright (c) 2006-2009 Simtec Electronics
342e20f1 BD	3	* http://armlinux.simtec.co.uk/
	4	* Ben Dooks <ben@simtec.co.uk>
	5	* Vincent Sanders <vince@simtec.co.uk>
	6	*
	7	* S3C2440/S3C2442 CPU Frequency scaling
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
1c5864e2 JP	14	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1c5864e2 JP	15
342e20f1 BD	16	#include <linux/init.h>
	17	#include <linux/module.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/ioport.h>
	20	#include <linux/cpufreq.h>
4a858cfc	21	#include <linux/device.h>
342e20f1 BD	22	#include <linux/delay.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26
342e20f1 BD	27	#include <asm/mach/arch.h>
	28	#include <asm/mach/map.h>
	29
	30	#include <mach/regs-clock.h>
	31
	32	#include <plat/cpu.h>
	33	#include <plat/cpu-freq-core.h>
342e20f1 BD	34
	35	static struct clk *xtal;
	36	static struct clk *fclk;
	37	static struct clk *hclk;
	38	static struct clk *armclk;
	39
	40	/* HDIV: 1, 2, 3, 4, 6, 8 */
	41
	42	static inline int within_khz(unsigned long a, unsigned long b)
	43	{
	44	long diff = a - b;
	45
	46	return (diff >= -1000 && diff <= 1000);
	47	}
	48
	49	/**
	50	* s3c2440_cpufreq_calcdivs - calculate divider settings
	51	* @cfg: The cpu frequency settings.
	52	*
	53	* Calcualte the divider values for the given frequency settings
	54	* specified in @cfg. The values are stored in @cfg for later use
	55	* by the relevant set routine if the request settings can be reached.
	56	*/
8f82b196	57	static int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
342e20f1 BD	58	{
	59	unsigned int hdiv, pdiv;
	60	unsigned long hclk, fclk, armclk;
	61	unsigned long hclk_max;
	62
	63	fclk = cfg->freq.fclk;
	64	armclk = cfg->freq.armclk;
	65	hclk_max = cfg->max.hclk;
	66
	67	s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
	68	__func__, fclk, armclk, hclk_max);
	69
	70	if (armclk > fclk) {
b49c22a6	71	pr_warn("%s: armclk > fclk\n", __func__);
342e20f1 BD	72	armclk = fclk;
	73	}
	74
	75	/* if we are in DVS, we need HCLK to be <= ARMCLK */
	76	if (armclk < fclk && armclk < hclk_max)
	77	hclk_max = armclk;
	78
	79	for (hdiv = 1; hdiv < 9; hdiv++) {
	80	if (hdiv == 5 \|\| hdiv == 7)
	81	hdiv++;
	82
	83	hclk = (fclk / hdiv);
	84	if (hclk <= hclk_max \|\| within_khz(hclk, hclk_max))
	85	break;
	86	}
	87
	88	s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
	89
	90	if (hdiv > 8)
	91	goto invalid;
	92
	93	pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
	94
	95	if ((hclk / pdiv) > cfg->max.pclk)
	96	pdiv++;
	97
	98	s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
	99
	100	if (pdiv > 2)
	101	goto invalid;
	102
	103	pdiv *= hdiv;
	104
	105	/* calculate a valid armclk */
	106
	107	if (armclk < hclk)
	108	armclk = hclk;
	109
	110	/* if we're running armclk lower than fclk, this really means
	111	* that the system should go into dvs mode, which means that
	112	* armclk is connected to hclk. */
	113	if (armclk < fclk) {
	114	cfg->divs.dvs = 1;
	115	armclk = hclk;
	116	} else
	117	cfg->divs.dvs = 0;
	118
	119	cfg->freq.armclk = armclk;
	120
	121	/* store the result, and then return */
	122
	123	cfg->divs.h_divisor = hdiv;
	124	cfg->divs.p_divisor = pdiv;
	125
	126	return 0;
	127
	128	invalid:
	129	return -EINVAL;
	130	}
	131
	132	#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF \| \
	133	S3C2440_CAMDIVN_HCLK4_HALF)
	134
	135	/**
136	* s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
137	* @cfg: The cpu frequency settings.
138	*
139	* Set the divisors from the settings in @cfg, which where generated
140	* during the calculation phase by s3c2440_cpufreq_calcdivs().
141	*/
142	static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
143	{
144	unsigned long clkdiv, camdiv;
145
146	s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
147	cfg->divs.h_divisor, cfg->divs.p_divisor);
148
149	clkdiv = __raw_readl(S3C2410_CLKDIVN);
150	camdiv = __raw_readl(S3C2440_CAMDIVN);
151
152	clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK \| S3C2440_CLKDIVN_PDIVN);
153	camdiv &= ~CAMDIVN_HCLK_HALF;
154
155	switch (cfg->divs.h_divisor) {
156	case 1:
157	clkdiv \|= S3C2440_CLKDIVN_HDIVN_1;
158	break;
159
160	case 2:
161	clkdiv \|= S3C2440_CLKDIVN_HDIVN_2;
162	break;
163
164	case 6:
165	camdiv \|= S3C2440_CAMDIVN_HCLK3_HALF;
166	case 3:
167	clkdiv \|= S3C2440_CLKDIVN_HDIVN_3_6;
168	break;
169
170	case 8:
171	camdiv \|= S3C2440_CAMDIVN_HCLK4_HALF;
172	case 4:
173	clkdiv \|= S3C2440_CLKDIVN_HDIVN_4_8;
174	break;
175
176	default:
177	BUG(); /* we don't expect to get here. */
178	}
179
180	if (cfg->divs.p_divisor != cfg->divs.h_divisor)
181	clkdiv \|= S3C2440_CLKDIVN_PDIVN;
182
183	/* todo - set pclk. */
184
185	/* Write the divisors first with hclk intentionally halved so that
186	* when we write clkdiv we will under-frequency instead of over. We
187	* then make a short delay and remove the hclk halving if necessary.
188	*/
189
190	__raw_writel(camdiv \| CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
191	__raw_writel(clkdiv, S3C2410_CLKDIVN);
192
193	ndelay(20);
194	__raw_writel(camdiv, S3C2440_CAMDIVN);
195
196	clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
197	}
198
199	static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
200	int *divs,
201	struct cpufreq_frequency_table *table,
202	size_t table_size)
203	{
204	unsigned long freq;
205	int index = 0;
206	int div;
207
208	for (div = divs; div > 0; div = divs++) {
209	freq = fclk / div;
210
211	if (freq > max_hclk && div != 1)
212	continue;
213
214	freq /= 1000; /* table is in kHz */
215	index = s3c_cpufreq_addfreq(table, index, table_size, freq);
216	if (index < 0)
217	break;
218	}
219
220	return index;
221	}
222
223	static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
224
225	static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
226	struct cpufreq_frequency_table *table,
227	size_t table_size)
228	{
229	int ret;
230
231	WARN_ON(cfg->info == NULL);
232	WARN_ON(cfg->board == NULL);
233
234	ret = run_freq_for(cfg->info->max.hclk,
235	cfg->info->max.fclk,
236	hclk_divs,
237	table, table_size);
238
239	s3c_freq_dbg("%s: returning %d\n", __func__, ret);
240
241	return ret;
242	}
243
8f82b196	244	static struct s3c_cpufreq_info s3c2440_cpufreq_info = {
342e20f1 BD	245	.max = {
	246	.fclk = 400000000,
	247	.hclk = 133333333,
	248	.pclk = 66666666,
	249	},
	250
	251	.locktime_m = 300,
	252	.locktime_u = 300,
	253	.locktime_bits = 16,
	254
	255	.name = "s3c244x",
	256	.calc_iotiming = s3c2410_iotiming_calc,
	257	.set_iotiming = s3c2410_iotiming_set,
	258	.get_iotiming = s3c2410_iotiming_get,
	259	.set_fvco = s3c2410_set_fvco,
	260
	261	.set_refresh = s3c2410_cpufreq_setrefresh,
	262	.set_divs = s3c2440_cpufreq_setdivs,
	263	.calc_divs = s3c2440_cpufreq_calcdivs,
	264	.calc_freqtable = s3c2440_cpufreq_calctable,
	265
e6d197a6	266	.debug_io_show = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
342e20f1 BD	267	};
342e20f1 BD	268
04511a6f HS	269	static int s3c2440_cpufreq_add(struct device *dev,
04511a6f HS	270	struct subsys_interface *sif)
342e20f1 BD	271	{
	272	xtal = s3c_cpufreq_clk_get(NULL, "xtal");
	273	hclk = s3c_cpufreq_clk_get(NULL, "hclk");
	274	fclk = s3c_cpufreq_clk_get(NULL, "fclk");
	275	armclk = s3c_cpufreq_clk_get(NULL, "armclk");
	276
	277	if (IS_ERR(xtal) \|\| IS_ERR(hclk) \|\| IS_ERR(fclk) \|\| IS_ERR(armclk)) {
b49c22a6	278	pr_err("%s: failed to get clocks\n", __func__);
342e20f1 BD	279	return -ENOENT;
	280	}
	281
	282	return s3c_cpufreq_register(&s3c2440_cpufreq_info);
	283	}
	284
4a858cfc KS	285	static struct subsys_interface s3c2440_cpufreq_interface = {
	286	.name = "s3c2440_cpufreq",
	287	.subsys = &s3c2440_subsys,
	288	.add_dev = s3c2440_cpufreq_add,
342e20f1 BD	289	};
	290
	291	static int s3c2440_cpufreq_init(void)
	292	{
4a858cfc	293	return subsys_interface_register(&s3c2440_cpufreq_interface);
342e20f1 BD	294	}
	295
	296	/* arch_initcall adds the clocks we need, so use subsys_initcall. */
	297	subsys_initcall(s3c2440_cpufreq_init);
	298
4a858cfc KS	299	static struct subsys_interface s3c2442_cpufreq_interface = {
	300	.name = "s3c2442_cpufreq",
	301	.subsys = &s3c2442_subsys,
	302	.add_dev = s3c2440_cpufreq_add,
342e20f1 BD	303	};
	304
	305	static int s3c2442_cpufreq_init(void)
	306	{
4a858cfc	307	return subsys_interface_register(&s3c2442_cpufreq_interface);
342e20f1	308	}
342e20f1	309	subsys_initcall(s3c2442_cpufreq_init);