[mirror_ubuntu-zesty-kernel.git] / drivers / cpufreq / s5pv210-cpufreq.c

/*
 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * CPU frequency scaling for S5PC110/S5PV210
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cpufreq.h>

#include <mach/map.h>
#include <mach/regs-clock.h>

static struct clk *cpu_clk;
static struct clk *dmc0_clk;
static struct clk *dmc1_clk;
static struct cpufreq_freqs freqs;

/* APLL M,P,S values for 1G/800Mhz */
#define APLL_VAL_1000	((1 << 31) | (125 << 16) | (3 << 8) | 1)
#define APLL_VAL_800	((1 << 31) | (100 << 16) | (3 << 8) | 1)

/*
 * DRAM configurations to calculate refresh counter for changing
 * frequency of memory.
 */
struct dram_conf {
	unsigned long freq;	/* HZ */
	unsigned long refresh;	/* DRAM refresh counter * 1000 */
};

/* DRAM configuration (DMC0 and DMC1) */
static struct dram_conf s5pv210_dram_conf[2];

enum perf_level {
	L0, L1, L2, L3, L4,
};

enum s5pv210_mem_type {
	LPDDR	= 0x1,
	LPDDR2	= 0x2,
	DDR2	= 0x4,
};

enum s5pv210_dmc_port {
	DMC0 = 0,
	DMC1,
};

static struct cpufreq_frequency_table s5pv210_freq_table[] = {
	{L0, 1000*1000},
	{L1, 800*1000},
	{L2, 400*1000},
	{L3, 200*1000},
	{L4, 100*1000},
	{0, CPUFREQ_TABLE_END},
};

static u32 clkdiv_val[5][11] = {
	/*
	 * Clock divider value for following
	 * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
	 *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
	 *   ONEDRAM, MFC, G3D }
	 */

	/* L0 : [1000/200/100][166/83][133/66][200/200] */
	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L1 : [800/200/100][166/83][133/66][200/200] */
	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L2 : [400/200/100][166/83][133/66][200/200] */
	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L3 : [200/200/100][166/83][133/66][200/200] */
	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},

	/* L4 : [100/100/100][83/83][66/66][100/100] */
	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
};

/*
 * This function set DRAM refresh counter
 * accoriding to operating frequency of DRAM
 * ch: DMC port number 0 or 1
 * freq: Operating frequency of DRAM(KHz)
 */
static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
{
	unsigned long tmp, tmp1;
	void __iomem *reg = NULL;

	if (ch == DMC0) {
		reg = (S5P_VA_DMC0 + 0x30);
	} else if (ch == DMC1) {
		reg = (S5P_VA_DMC1 + 0x30);
	} else {
		printk(KERN_ERR "Cannot find DMC port\n");
		return;
	}

	/* Find current DRAM frequency */
	tmp = s5pv210_dram_conf[ch].freq;

	do_div(tmp, freq);

	tmp1 = s5pv210_dram_conf[ch].refresh;

	do_div(tmp1, tmp);

	__raw_writel(tmp1, reg);
}

int s5pv210_verify_speed(struct cpufreq_policy *policy)
{
	if (policy->cpu)
		return -EINVAL;

	return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
}

unsigned int s5pv210_getspeed(unsigned int cpu)
{
	if (cpu)
		return 0;

	return clk_get_rate(cpu_clk) / 1000;
}

static int s5pv210_target(struct cpufreq_policy *policy,
			  unsigned int target_freq,
			  unsigned int relation)
{
	unsigned long reg;
	unsigned int index, priv_index;
	unsigned int pll_changing = 0;
	unsigned int bus_speed_changing = 0;

	freqs.old = s5pv210_getspeed(0);

	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
					   target_freq, relation, &index))
		return -EINVAL;

	freqs.new = s5pv210_freq_table[index].frequency;
	freqs.cpu = 0;

	if (freqs.new == freqs.old)
		return 0;

	/* Finding current running level index */
	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
					   freqs.old, relation, &priv_index))
		return -EINVAL;

	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);

	if (freqs.new > freqs.old) {
		/* Voltage up: will be implemented */
	}

	/* Check if there need to change PLL */
	if ((index == L0) || (priv_index == L0))
		pll_changing = 1;

	/* Check if there need to change System bus clock */
	if ((index == L4) || (priv_index == L4))
		bus_speed_changing = 1;

	if (bus_speed_changing) {
		/*
		 * Reconfigure DRAM refresh counter value for minimum
		 * temporary clock while changing divider.
		 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
		 */
		if (pll_changing)
			s5pv210_set_refresh(DMC1, 83000);
		else
			s5pv210_set_refresh(DMC1, 100000);

		s5pv210_set_refresh(DMC0, 83000);
	}

	/*
	 * APLL should be changed in this level
	 * APLL -> MPLL(for stable transition) -> APLL
	 * Some clock source's clock API are not prepared.
	 * Do not use clock API in below code.
	 */
	if (pll_changing) {
		/*
		 * 1. Temporary Change divider for MFC and G3D
		 * SCLKA2M(200/1=200)->(200/4=50)Mhz
		 */
		reg = __raw_readl(S5P_CLK_DIV2);
		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
		reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
			(3 << S5P_CLKDIV2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV2);

		/* For MFC, G3D dividing */
		do {
			reg = __raw_readl(S5P_CLKDIV_STAT0);
		} while (reg & ((1 << 16) | (1 << 17)));

		/*
		 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
		 * (200/4=50)->(667/4=166)Mhz
		 */
		reg = __raw_readl(S5P_CLK_SRC2);
		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
		reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
			(1 << S5P_CLKSRC2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC2);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT1);
		} while (reg & ((1 << 7) | (1 << 3)));

		/*
		 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
		 * true refresh counter is already programed in upper
		 * code. 0x287@83Mhz
		 */
		if (!bus_speed_changing)
			s5pv210_set_refresh(DMC1, 133000);

		/* 4. SCLKAPLL -> SCLKMPLL */
		reg = __raw_readl(S5P_CLK_SRC0);
		reg &= ~(S5P_CLKSRC0_MUX200_MASK);
		reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC0);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT0);
		} while (reg & (0x1 << 18));

	}

	/* Change divider */
	reg = __raw_readl(S5P_CLK_DIV0);

	reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
		S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
		S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
		S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);

	reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
		(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
		(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
		(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
		(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
		(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
		(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
		(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));

	__raw_writel(reg, S5P_CLK_DIV0);

	do {
		reg = __raw_readl(S5P_CLKDIV_STAT0);
	} while (reg & 0xff);

	/* ARM MCS value changed */
	reg = __raw_readl(S5P_ARM_MCS_CON);
	reg &= ~0x3;
	if (index >= L3)
		reg |= 0x3;
	else
		reg |= 0x1;

	__raw_writel(reg, S5P_ARM_MCS_CON);

	if (pll_changing) {
		/* 5. Set Lock time = 30us*24Mhz = 0x2cf */
		__raw_writel(0x2cf, S5P_APLL_LOCK);

		/*
		 * 6. Turn on APLL
		 * 6-1. Set PMS values
		 * 6-2. Wait untile the PLL is locked
		 */
		if (index == L0)
			__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
		else
			__raw_writel(APLL_VAL_800, S5P_APLL_CON);

		do {
			reg = __raw_readl(S5P_APLL_CON);
		} while (!(reg & (0x1 << 29)));

		/*
		 * 7. Change souce clock from SCLKMPLL(667Mhz)
		 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
		 * (667/4=166)->(200/4=50)Mhz
		 */
		reg = __raw_readl(S5P_CLK_SRC2);
		reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
		reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
			(0 << S5P_CLKSRC2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC2);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT1);
		} while (reg & ((1 << 7) | (1 << 3)));

		/*
		 * 8. Change divider for MFC and G3D
		 * (200/4=50)->(200/1=200)Mhz
		 */
		reg = __raw_readl(S5P_CLK_DIV2);
		reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
		reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
			(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV2);

		/* For MFC, G3D dividing */
		do {
			reg = __raw_readl(S5P_CLKDIV_STAT0);
		} while (reg & ((1 << 16) | (1 << 17)));

		/* 9. Change MPLL to APLL in MSYS_MUX */
		reg = __raw_readl(S5P_CLK_SRC0);
		reg &= ~(S5P_CLKSRC0_MUX200_MASK);
		reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
		__raw_writel(reg, S5P_CLK_SRC0);

		do {
			reg = __raw_readl(S5P_CLKMUX_STAT0);
		} while (reg & (0x1 << 18));

		/*
		 * 10. DMC1 refresh counter
		 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
		 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
		 */
		if (!bus_speed_changing)
			s5pv210_set_refresh(DMC1, 200000);
	}

	/*
	 * L4 level need to change memory bus speed, hence onedram clock divier
	 * and memory refresh parameter should be changed
	 */
	if (bus_speed_changing) {
		reg = __raw_readl(S5P_CLK_DIV6);
		reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
		reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
		__raw_writel(reg, S5P_CLK_DIV6);

		do {
			reg = __raw_readl(S5P_CLKDIV_STAT1);
		} while (reg & (1 << 15));

		/* Reconfigure DRAM refresh counter value */
		if (index != L4) {
			/*
			 * DMC0 : 166Mhz
			 * DMC1 : 200Mhz
			 */
			s5pv210_set_refresh(DMC0, 166000);
			s5pv210_set_refresh(DMC1, 200000);
		} else {
			/*
			 * DMC0 : 83Mhz
			 * DMC1 : 100Mhz
			 */
			s5pv210_set_refresh(DMC0, 83000);
			s5pv210_set_refresh(DMC1, 100000);
		}
	}

	if (freqs.new < freqs.old) {
		/* Voltage down: will be implemented */
	}

	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);

	printk(KERN_DEBUG "Perf changed[L%d]\n", index);

	return 0;
}

#ifdef CONFIG_PM
static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
{
	return 0;
}

static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
{
	return 0;
}
#endif

static int check_mem_type(void __iomem *dmc_reg)
{
	unsigned long val;

	val = __raw_readl(dmc_reg + 0x4);
	val = (val & (0xf << 8));

	return val >> 8;
}

static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
{
	unsigned long mem_type;

	cpu_clk = clk_get(NULL, "armclk");
	if (IS_ERR(cpu_clk))
		return PTR_ERR(cpu_clk);

	dmc0_clk = clk_get(NULL, "sclk_dmc0");
	if (IS_ERR(dmc0_clk)) {
		clk_put(cpu_clk);
		return PTR_ERR(dmc0_clk);
	}

	dmc1_clk = clk_get(NULL, "hclk_msys");
	if (IS_ERR(dmc1_clk)) {
		clk_put(dmc0_clk);
		clk_put(cpu_clk);
		return PTR_ERR(dmc1_clk);
	}

	if (policy->cpu != 0)
		return -EINVAL;

	/*
	 * check_mem_type : This driver only support LPDDR & LPDDR2.
	 * other memory type is not supported.
	 */
	mem_type = check_mem_type(S5P_VA_DMC0);

	if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
		printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
		return -EINVAL;
	}

	/* Find current refresh counter and frequency each DMC */
	s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);

	s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);

	policy->cur = policy->min = policy->max = s5pv210_getspeed(0);

	cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);

	policy->cpuinfo.transition_latency = 40000;

	return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
}

static struct cpufreq_driver s5pv210_driver = {
	.flags		= CPUFREQ_STICKY,
	.verify		= s5pv210_verify_speed,
	.target		= s5pv210_target,
	.get		= s5pv210_getspeed,
	.init		= s5pv210_cpu_init,
	.name		= "s5pv210",
#ifdef CONFIG_PM
	.suspend	= s5pv210_cpufreq_suspend,
	.resume		= s5pv210_cpufreq_resume,
#endif
};

static int __init s5pv210_cpufreq_init(void)
{
	return cpufreq_register_driver(&s5pv210_driver);
}

late_initcall(s5pv210_cpufreq_init);
Commit	Line	Data
f7d77079	1	/*
83efc743 JL	2	* Copyright (c) 2010 Samsung Electronics Co., Ltd.
	3	* http://www.samsung.com
	4	*
	5	* CPU frequency scaling for S5PC110/S5PV210
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/types.h>
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/err.h>
	16	#include <linux/clk.h>
	17	#include <linux/io.h>
	18	#include <linux/cpufreq.h>
	19
	20	#include <mach/map.h>
	21	#include <mach/regs-clock.h>
	22
	23	static struct clk *cpu_clk;
	24	static struct clk *dmc0_clk;
	25	static struct clk *dmc1_clk;
	26	static struct cpufreq_freqs freqs;
	27
	28	/* APLL M,P,S values for 1G/800Mhz */
	29	#define APLL_VAL_1000 ((1 << 31) \| (125 << 16) \| (3 << 8) \| 1)
	30	#define APLL_VAL_800 ((1 << 31) \| (100 << 16) \| (3 << 8) \| 1)
	31
	32	/*
	33	* DRAM configurations to calculate refresh counter for changing
	34	* frequency of memory.
	35	*/
	36	struct dram_conf {
	37	unsigned long freq; /* HZ */
	38	unsigned long refresh; /* DRAM refresh counter * 1000 */
	39	};
	40
	41	/* DRAM configuration (DMC0 and DMC1) */
	42	static struct dram_conf s5pv210_dram_conf[2];
	43
	44	enum perf_level {
	45	L0, L1, L2, L3, L4,
	46	};
	47
	48	enum s5pv210_mem_type {
	49	LPDDR = 0x1,
	50	LPDDR2 = 0x2,
	51	DDR2 = 0x4,
	52	};
	53
	54	enum s5pv210_dmc_port {
	55	DMC0 = 0,
	56	DMC1,
	57	};
	58
	59	static struct cpufreq_frequency_table s5pv210_freq_table[] = {
	60	{L0, 1000*1000},
	61	{L1, 800*1000},
	62	{L2, 400*1000},
	63	{L3, 200*1000},
	64	{L4, 100*1000},
	65	{0, CPUFREQ_TABLE_END},
66	};
67
68	static u32 clkdiv_val[5][11] = {
69	/*
70	* Clock divider value for following
71	* { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
72	* HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
73	* ONEDRAM, MFC, G3D }
74	*/
75
76	/* L0 : [1000/200/100][166/83][133/66][200/200] */
77	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
78
79	/* L1 : [800/200/100][166/83][133/66][200/200] */
80	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
81
82	/* L2 : [400/200/100][166/83][133/66][200/200] */
83	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
84
85	/* L3 : [200/200/100][166/83][133/66][200/200] */
86	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
87
88	/* L4 : [100/100/100][83/83][66/66][100/100] */
89	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
90	};
91
92	/*
93	* This function set DRAM refresh counter
94	* accoriding to operating frequency of DRAM
95	* ch: DMC port number 0 or 1
96	* freq: Operating frequency of DRAM(KHz)
97	*/
98	static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
99	{
100	unsigned long tmp, tmp1;
101	void __iomem *reg = NULL;
102
d62fa311	103	if (ch == DMC0) {
83efc743	104	reg = (S5P_VA_DMC0 + 0x30);
d62fa311	105	} else if (ch == DMC1) {
83efc743	106	reg = (S5P_VA_DMC1 + 0x30);
d62fa311	107	} else {
83efc743	108	printk(KERN_ERR "Cannot find DMC port\n");
d62fa311 JC	109	return;
d62fa311 JC	110	}
83efc743 JL	111
	112	/* Find current DRAM frequency */
	113	tmp = s5pv210_dram_conf[ch].freq;
	114
	115	do_div(tmp, freq);
	116
	117	tmp1 = s5pv210_dram_conf[ch].refresh;
	118
	119	do_div(tmp1, tmp);
	120
	121	__raw_writel(tmp1, reg);
	122	}
	123
	124	int s5pv210_verify_speed(struct cpufreq_policy *policy)
	125	{
	126	if (policy->cpu)
	127	return -EINVAL;
	128
	129	return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
	130	}
	131
	132	unsigned int s5pv210_getspeed(unsigned int cpu)
	133	{
	134	if (cpu)
	135	return 0;
	136
	137	return clk_get_rate(cpu_clk) / 1000;
	138	}
	139
	140	static int s5pv210_target(struct cpufreq_policy *policy,
	141	unsigned int target_freq,
	142	unsigned int relation)
	143	{
	144	unsigned long reg;
	145	unsigned int index, priv_index;
	146	unsigned int pll_changing = 0;
	147	unsigned int bus_speed_changing = 0;
	148
	149	freqs.old = s5pv210_getspeed(0);
	150
	151	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
	152	target_freq, relation, &index))
	153	return -EINVAL;
	154
	155	freqs.new = s5pv210_freq_table[index].frequency;
	156	freqs.cpu = 0;
	157
	158	if (freqs.new == freqs.old)
	159	return 0;
	160
	161	/* Finding current running level index */
	162	if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
	163	freqs.old, relation, &priv_index))
	164	return -EINVAL;
	165
	166	cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
	167
	168	if (freqs.new > freqs.old) {
	169	/* Voltage up: will be implemented */
	170	}
	171
	172	/* Check if there need to change PLL */
	173	if ((index == L0) \|\| (priv_index == L0))
	174	pll_changing = 1;
175
176	/* Check if there need to change System bus clock */
177	if ((index == L4) \|\| (priv_index == L4))
178	bus_speed_changing = 1;
179
180	if (bus_speed_changing) {
181	/*
182	* Reconfigure DRAM refresh counter value for minimum
183	* temporary clock while changing divider.
184	* expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
185	*/
186	if (pll_changing)
187	s5pv210_set_refresh(DMC1, 83000);
188	else
189	s5pv210_set_refresh(DMC1, 100000);
190
191	s5pv210_set_refresh(DMC0, 83000);
192	}
193
194	/*
195	* APLL should be changed in this level
196	* APLL -> MPLL(for stable transition) -> APLL
197	* Some clock source's clock API are not prepared.
198	* Do not use clock API in below code.
199	*/
200	if (pll_changing) {
201	/*
202	* 1. Temporary Change divider for MFC and G3D
203	* SCLKA2M(200/1=200)->(200/4=50)Mhz
204	*/
205	reg = __raw_readl(S5P_CLK_DIV2);
206	reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK);
207	reg \|= (3 << S5P_CLKDIV2_G3D_SHIFT) \|
208	(3 << S5P_CLKDIV2_MFC_SHIFT);
209	__raw_writel(reg, S5P_CLK_DIV2);
210
211	/* For MFC, G3D dividing */
212	do {
213	reg = __raw_readl(S5P_CLKDIV_STAT0);
214	} while (reg & ((1 << 16) \| (1 << 17)));
215
216	/*
217	* 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
218	* (200/4=50)->(667/4=166)Mhz
219	*/
220	reg = __raw_readl(S5P_CLK_SRC2);
221	reg &= ~(S5P_CLKSRC2_G3D_MASK \| S5P_CLKSRC2_MFC_MASK);
222	reg \|= (1 << S5P_CLKSRC2_G3D_SHIFT) \|
223	(1 << S5P_CLKSRC2_MFC_SHIFT);
224	__raw_writel(reg, S5P_CLK_SRC2);
225
226	do {
227	reg = __raw_readl(S5P_CLKMUX_STAT1);
228	} while (reg & ((1 << 7) \| (1 << 3)));
229
230	/*
231	* 3. DMC1 refresh count for 133Mhz if (index == L4) is
232	* true refresh counter is already programed in upper
233	* code. 0x287@83Mhz
234	*/
235	if (!bus_speed_changing)
236	s5pv210_set_refresh(DMC1, 133000);
237
238	/* 4. SCLKAPLL -> SCLKMPLL */
239	reg = __raw_readl(S5P_CLK_SRC0);
240	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
241	reg \|= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
242	__raw_writel(reg, S5P_CLK_SRC0);
243
244	do {
245	reg = __raw_readl(S5P_CLKMUX_STAT0);
246	} while (reg & (0x1 << 18));
247
248	}
249
250	/* Change divider */
251	reg = __raw_readl(S5P_CLK_DIV0);
252
253	reg &= ~(S5P_CLKDIV0_APLL_MASK \| S5P_CLKDIV0_A2M_MASK \|
254	S5P_CLKDIV0_HCLK200_MASK \| S5P_CLKDIV0_PCLK100_MASK \|
255	S5P_CLKDIV0_HCLK166_MASK \| S5P_CLKDIV0_PCLK83_MASK \|
256	S5P_CLKDIV0_HCLK133_MASK \| S5P_CLKDIV0_PCLK66_MASK);
257
258	reg \|= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) \|
259	(clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) \|
260	(clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) \|
261	(clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) \|
262	(clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) \|
263	(clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) \|
264	(clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) \|
265	(clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
266
267	__raw_writel(reg, S5P_CLK_DIV0);
268
269	do {
270	reg = __raw_readl(S5P_CLKDIV_STAT0);
271	} while (reg & 0xff);
272
273	/* ARM MCS value changed */
274	reg = __raw_readl(S5P_ARM_MCS_CON);
275	reg &= ~0x3;
276	if (index >= L3)
277	reg \|= 0x3;
278	else
279	reg \|= 0x1;
280
281	__raw_writel(reg, S5P_ARM_MCS_CON);
282
283	if (pll_changing) {
284	/* 5. Set Lock time = 30us24Mhz = 0x2cf /
285	__raw_writel(0x2cf, S5P_APLL_LOCK);
286
287	/*
288	* 6. Turn on APLL
289	* 6-1. Set PMS values
290	* 6-2. Wait untile the PLL is locked
291	*/
292	if (index == L0)
293	__raw_writel(APLL_VAL_1000, S5P_APLL_CON);
294	else
295	__raw_writel(APLL_VAL_800, S5P_APLL_CON);
296
297	do {
298	reg = __raw_readl(S5P_APLL_CON);
299	} while (!(reg & (0x1 << 29)));
300
301	/*
302	* 7. Change souce clock from SCLKMPLL(667Mhz)
303	* to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
304	* (667/4=166)->(200/4=50)Mhz
305	*/
306	reg = __raw_readl(S5P_CLK_SRC2);
307	reg &= ~(S5P_CLKSRC2_G3D_MASK \| S5P_CLKSRC2_MFC_MASK);
308	reg \|= (0 << S5P_CLKSRC2_G3D_SHIFT) \|
309	(0 << S5P_CLKSRC2_MFC_SHIFT);
310	__raw_writel(reg, S5P_CLK_SRC2);
311
312	do {
313	reg = __raw_readl(S5P_CLKMUX_STAT1);
314	} while (reg & ((1 << 7) \| (1 << 3)));
315
316	/*
317	* 8. Change divider for MFC and G3D
318	* (200/4=50)->(200/1=200)Mhz
319	*/
320	reg = __raw_readl(S5P_CLK_DIV2);
321	reg &= ~(S5P_CLKDIV2_G3D_MASK \| S5P_CLKDIV2_MFC_MASK);
322	reg \|= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) \|
323	(clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
324	__raw_writel(reg, S5P_CLK_DIV2);
325
326	/* For MFC, G3D dividing */
327	do {
328	reg = __raw_readl(S5P_CLKDIV_STAT0);
329	} while (reg & ((1 << 16) \| (1 << 17)));
330
331	/* 9. Change MPLL to APLL in MSYS_MUX */
332	reg = __raw_readl(S5P_CLK_SRC0);
333	reg &= ~(S5P_CLKSRC0_MUX200_MASK);
334	reg \|= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
335	__raw_writel(reg, S5P_CLK_SRC0);
336
337	do {
338	reg = __raw_readl(S5P_CLKMUX_STAT0);
339	} while (reg & (0x1 << 18));
340
341	/*
342	* 10. DMC1 refresh counter
343	* L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
344	* Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
345	*/
346	if (!bus_speed_changing)
347	s5pv210_set_refresh(DMC1, 200000);
348	}
349
350	/*
351	* L4 level need to change memory bus speed, hence onedram clock divier
352	* and memory refresh parameter should be changed
353	*/
354	if (bus_speed_changing) {
355	reg = __raw_readl(S5P_CLK_DIV6);
356	reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
357	reg \|= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
358	__raw_writel(reg, S5P_CLK_DIV6);
359
360	do {
361	reg = __raw_readl(S5P_CLKDIV_STAT1);
362	} while (reg & (1 << 15));
363
364	/* Reconfigure DRAM refresh counter value */
365	if (index != L4) {
366	/*
367	* DMC0 : 166Mhz
368	* DMC1 : 200Mhz
369	*/
370	s5pv210_set_refresh(DMC0, 166000);
371	s5pv210_set_refresh(DMC1, 200000);
372	} else {
373	/*
374	* DMC0 : 83Mhz
375	* DMC1 : 100Mhz
376	*/
377	s5pv210_set_refresh(DMC0, 83000);
378	s5pv210_set_refresh(DMC1, 100000);
379	}
380	}
381
382	if (freqs.new < freqs.old) {
383	/* Voltage down: will be implemented */
384	}
385
386	cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
387
388	printk(KERN_DEBUG "Perf changed[L%d]\n", index);
389
390	return 0;
391	}
392
393	#ifdef CONFIG_PM
7ca64e2d	394	static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
83efc743 JL	395	{
	396	return 0;
	397	}
	398
	399	static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
	400	{
	401	return 0;
	402	}
	403	#endif
	404
	405	static int check_mem_type(void __iomem *dmc_reg)
	406	{
	407	unsigned long val;
	408
	409	val = __raw_readl(dmc_reg + 0x4);
	410	val = (val & (0xf << 8));
	411
	412	return val >> 8;
	413	}
	414
	415	static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
	416	{
	417	unsigned long mem_type;
	418
	419	cpu_clk = clk_get(NULL, "armclk");
	420	if (IS_ERR(cpu_clk))
	421	return PTR_ERR(cpu_clk);
	422
	423	dmc0_clk = clk_get(NULL, "sclk_dmc0");
	424	if (IS_ERR(dmc0_clk)) {
	425	clk_put(cpu_clk);
	426	return PTR_ERR(dmc0_clk);
	427	}
	428
	429	dmc1_clk = clk_get(NULL, "hclk_msys");
	430	if (IS_ERR(dmc1_clk)) {
	431	clk_put(dmc0_clk);
	432	clk_put(cpu_clk);
	433	return PTR_ERR(dmc1_clk);
	434	}
	435
	436	if (policy->cpu != 0)
	437	return -EINVAL;
	438
	439	/*
	440	* check_mem_type : This driver only support LPDDR & LPDDR2.
	441	* other memory type is not supported.
	442	*/
	443	mem_type = check_mem_type(S5P_VA_DMC0);
	444
	445	if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
	446	printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
	447	return -EINVAL;
	448	}
	449
	450	/* Find current refresh counter and frequency each DMC */
	451	s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
	452	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
	453
	454	s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
	455	s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
	456
	457	policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
	458
459	cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
460
461	policy->cpuinfo.transition_latency = 40000;
462
463	return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
464	}
465
466	static struct cpufreq_driver s5pv210_driver = {
467	.flags = CPUFREQ_STICKY,
468	.verify = s5pv210_verify_speed,
469	.target = s5pv210_target,
470	.get = s5pv210_getspeed,
471	.init = s5pv210_cpu_init,
472	.name = "s5pv210",
473	#ifdef CONFIG_PM
474	.suspend = s5pv210_cpufreq_suspend,
475	.resume = s5pv210_cpufreq_resume,
476	#endif
477	};
478
479	static int __init s5pv210_cpufreq_init(void)
480	{
481	return cpufreq_register_driver(&s5pv210_driver);
482	}
483
484	late_initcall(s5pv210_cpufreq_init);